Commit 2e5367566819ca7878baa9600ae7a93eb0e37bbf | rust

author	bors <bors@rust-lang.org> 2025-07-22 15:25:31 UTC
committer	bors <bors@rust-lang.org> 2025-07-22 15:25:31 UTC
log	2e5367566819ca7878baa9600ae7a93eb0e37bbf
tree	6b65029625eb4b6e726b826197e617728788430e
parent	35487a2e7c80012129c38f55c970109a1538c91f
parent	9b7d31c851cabc2e6e541d3cf146787d597a9166

Auto merge of #144222 - Kobzol:stdarch-push, r=folkertdev

stdarch subtree update

Subtree update of `stdarch` to https://github.com/rust-lang/stdarch/commit/5531955678494ee28ec02130a6d94082ad4532da.

Created using https://github.com/rust-lang/josh-sync.

I saw that there were non-trivial changes made to `std_detect` in `stdarch` recently. So I want to get them merged here before we move forward with https://github.com/rust-lang/rust/pull/143412.

r? `@folkertdev`

72 files changed, 4642 insertions(+), 5042 deletions(-)

library/stdarch/.github/workflows/main.yml+23

...	@@ -255,6 +255,28 @@ jobs:	...	@@ -255,6 +255,28 @@ jobs:
255	env:	255	env:
256	TARGET: ${{ matrix.target.tuple }}	256	TARGET: ${{ matrix.target.tuple }}
257		257
		258	# Check that the generated files agree with the checked-in versions.
		259	check-stdarch-gen:
		260	needs: [style]
		261	name: Check stdarch-gen-{arm, loongarch} output
		262	runs-on: ubuntu-latest
		263	steps:
		264	- uses: actions/checkout@v4
		265	- name: Install Rust
		266	run: rustup update nightly && rustup default nightly && rustup component add rustfmt
		267	- name: Check arm spec
		268	run: \|
		269	cargo run --bin=stdarch-gen-arm --release -- crates/stdarch-gen-arm/spec
		270	git diff --exit-code
		271	- name: Check lsx.spec
		272	run: \|
		273	cargo run --bin=stdarch-gen-loongarch --release -- crates/stdarch-gen-loongarch/lsx.spec
		274	git diff --exit-code
		275	- name: Check lasx.spec
		276	run: \|
		277	cargo run --bin=stdarch-gen-loongarch --release -- crates/stdarch-gen-loongarch/lasx.spec
		278	git diff --exit-code
		279
258	build-std-detect:	280	build-std-detect:
259	needs: [style]	281	needs: [style]
260	name: Build std_detect	282	name: Build std_detect
...	@@ -271,6 +293,7 @@ jobs:	...	@@ -271,6 +293,7 @@ jobs:
271	- verify	293	- verify
272	- test	294	- test
273	- build-std-detect	295	- build-std-detect
		296	- check-stdarch-gen
274	runs-on: ubuntu-latest	297	runs-on: ubuntu-latest
275	# We need to ensure this job does not get skipped if its dependencies fail,	298	# We need to ensure this job does not get skipped if its dependencies fail,
276	# because a skipped job is considered a success by GitHub. So we have to	299	# because a skipped job is considered a success by GitHub. So we have to

library/stdarch/.github/workflows/rustc-pull.yml created+22

...	@@ -0,0 +1,22 @@
1	# Perform a subtree sync (pull) using the josh-sync tool once every few days (or on demand).
2	name: rustc-pull
3
4	on:
5	workflow_dispatch:
6	schedule:
7	# Run at 04:00 UTC every Monday and Thursday
8	- cron: '0 4 * * 1,4'
9
10	jobs:
11	pull:
12	if: github.repository == 'rust-lang/stdarch'
13	uses: rust-lang/josh-sync/.github/workflows/rustc-pull.yml@main
14	with:
15	# https://rust-lang.zulipchat.com/#narrow/channel/208962-t-libs.2Fstdarch/topic/Subtree.20sync.20automation/with/528461782
16	zulip-stream-id: 208962
17	zulip-bot-email: "stdarch-ci-bot@rust-lang.zulipchat.com"
18	pr-base-branch: master
19	branch-name: rustc-pull
20	secrets:
21	zulip-api-token: ${{ secrets.ZULIP_API_TOKEN }}
22	token: ${{ secrets.GITHUB_TOKEN }}

library/stdarch/Cargo.lock+39-33

 @@ -73,20 +73,26 @@ version = "0.1.0"
 dependencies = [
  "proc-macro2",
  "quote",
- "syn 2.0.102",
+ "syn 2.0.104",
 ]
 [[package]]
 name = "autocfg"
-version = "1.4.0"
+version = "1.5.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "ace50bade8e6234aa140d9a2f552bbee1db4d353f69b8217bc503490fc1a9f26"
+checksum = "c08606f8c3cbf4ce6ec8e28fb0014a2c086708fe954eaa885384a6165172e7e8"
+[[package]]
+name = "bitflags"
+version = "2.9.1"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "1b8e56985ec62d17e9c1001dc89c88ecd7dc08e47eba5ec7c29c7b5eeecde967"
 [[package]]
 name = "cc"
-version = "1.2.26"
+version = "1.2.30"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "956a5e21988b87f372569b66183b78babf23ebc2e744b733e4350a752c4dafac"
+checksum = "deec109607ca693028562ed836a5f1c4b8bd77755c4e132fc5ce11b0b6211ae7"
 dependencies = [
  "shlex",
 ]
 @@ -99,9 +105,9 @@ checksum = "9555578bc9e57714c812a1f84e4fc5b4d21fcb063490c624de019f7464c91268"
 [[package]]
 name = "clap"
-version = "4.5.40"
+version = "4.5.41"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "40b6887a1d8685cebccf115538db5c0efe625ccac9696ad45c409d96566e910f"
+checksum = "be92d32e80243a54711e5d7ce823c35c41c9d929dc4ab58e1276f625841aadf9"
 dependencies = [
  "clap_builder",
  "clap_derive",
 @@ -109,9 +115,9 @@ dependencies = [
 [[package]]
 name = "clap_builder"
-version = "4.5.40"
+version = "4.5.41"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "e0c66c08ce9f0c698cbce5c0279d0bb6ac936d8674174fe48f736533b964f59e"
+checksum = "707eab41e9622f9139419d573eca0900137718000c517d47da73045f54331c3d"
 dependencies = [
  "anstream",
  "anstyle",
 @@ -121,14 +127,14 @@ dependencies = [
 [[package]]
 name = "clap_derive"
-version = "4.5.40"
+version = "4.5.41"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "d2c7947ae4cc3d851207c1adb5b5e260ff0cca11446b1d6d1423788e442257ce"
+checksum = "ef4f52386a59ca4c860f7393bcf8abd8dfd91ecccc0f774635ff68e92eeef491"
 dependencies = [
  "heck",
  "proc-macro2",
  "quote",
- "syn 2.0.102",
+ "syn 2.0.104",
 ]
 [[package]]
 @@ -338,9 +344,9 @@ dependencies = [
 [[package]]
 name = "indexmap"
-version = "2.9.0"
+version = "2.10.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "cea70ddb795996207ad57735b50c5982d8844f38ba9ee5f1aedcfb708a2aa11e"
+checksum = "fe4cd85333e22411419a0bcae1297d25e58c9443848b11dc6a86fefe8c78a661"
 dependencies = [
  "equivalent",
  "hashbrown 0.15.4",
 @@ -403,9 +409,9 @@ checksum = "bbd2bcb4c963f2ddae06a2efc7e9f3591312473c50c6685e1f298068316e66fe"
 [[package]]
 name = "libc"
-version = "0.2.172"
+version = "0.2.174"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "d750af042f7ef4f724306de029d18836c26c1765a54a6a3f094cbd23a7267ffa"
+checksum = "1171693293099992e19cddea4e8b849964e9846f4acee11b3948bcc337be8776"
 [[package]]
 name = "linked-hash-map"
 @@ -624,7 +630,7 @@ checksum = "5b0276cf7f2c73365f7157c8123c21cd9a50fbbd844757af28ca1f5925fc2a00"
 dependencies = [
  "proc-macro2",
  "quote",
- "syn 2.0.102",
+ "syn 2.0.104",
 ]
 [[package]]
 @@ -685,7 +691,7 @@ version = "0.1.0"
 dependencies = [
  "proc-macro2",
  "quote",
- "syn 2.0.102",
+ "syn 2.0.104",
 ]
 [[package]]
 @@ -703,7 +709,6 @@ name = "stdarch-gen-arm"
 version = "0.1.0"
 dependencies = [
  "itertools",
- "lazy_static",
  "proc-macro2",
  "quote",
  "regex",
 @@ -727,7 +732,6 @@ dependencies = [
  "assert-instr-macro",
  "cc",
  "cfg-if",
- "lazy_static",
  "rustc-demangle",
  "simd-test-macro",
  "wasmprinter",
 @@ -742,7 +746,7 @@ dependencies = [
  "quote",
  "serde",
  "serde_json",
- "syn 2.0.102",
+ "syn 2.0.104",
 ]
 [[package]]
 @@ -780,9 +784,9 @@ dependencies = [
 [[package]]
 name = "syn"
-version = "2.0.102"
+version = "2.0.104"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "f6397daf94fa90f058bd0fd88429dd9e5738999cca8d701813c80723add80462"
+checksum = "17b6f705963418cdb9927482fa304bc562ece2fdd4f616084c50b7023b435a40"
 dependencies = [
  "proc-macro2",
  "quote",
 @@ -834,21 +838,23 @@ checksum = "ccf3ec651a847eb01de73ccad15eb7d99f80485de043efb2f370cd654f4ea44b"
 [[package]]
 name = "wasmparser"
-version = "0.113.3"
+version = "0.235.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "286049849b5a5bd09a8773171be96824afabffc7cc3df6caaf33a38db6cd07ae"
+checksum = "161296c618fa2d63f6ed5fffd1112937e803cb9ec71b32b01a76321555660917"
 dependencies = [
- "indexmap 2.9.0",
+ "bitflags",
+ "indexmap 2.10.0",
  "semver",
 ]
 [[package]]
 name = "wasmprinter"
-version = "0.2.67"
+version = "0.235.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "f6615a5587149e753bf4b93f90fa3c3f41c88597a7a2da72879afcabeda9648f"
+checksum = "75aa8e9076de6b9544e6dab4badada518cca0bf4966d35b131bbd057aed8fa0a"
 dependencies = [
  "anyhow",
+ "termcolor",
  "wasmparser",
 ]
 @@ -945,20 +951,20 @@ dependencies = [
 [[package]]
 name = "zerocopy"
-version = "0.8.25"
+version = "0.8.26"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "a1702d9583232ddb9174e01bb7c15a2ab8fb1bc6f227aa1233858c351a3ba0cb"
+checksum = "1039dd0d3c310cf05de012d8a39ff557cb0d23087fd44cad61df08fc31907a2f"
 dependencies = [
  "zerocopy-derive",
 ]
 [[package]]
 name = "zerocopy-derive"
-version = "0.8.25"
+version = "0.8.26"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "28a6e20d751156648aa063f3800b706ee209a32c0b4d9f24be3d980b01be55ef"
+checksum = "9ecf5b4cc5364572d7f4c329661bcc82724222973f2cab6f050a4e5c22f75181"
 dependencies = [
  "proc-macro2",
  "quote",
- "syn 2.0.102",
+ "syn 2.0.104",
 ]

library/stdarch/Cargo.toml+2-1

...	@@ -5,7 +5,8 @@ members = [	...	@@ -5,7 +5,8 @@ members = [
5	"examples",	5	"examples",
6	]	6	]
7	exclude = [	7	exclude = [
8	"crates/wasm-assert-instr-tests"	8	"crates/wasm-assert-instr-tests",
		9	"rust_programs",
9	]	10	]
10		11
11	[profile.release]	12	[profile.release]

library/stdarch/ci/docker/aarch64-unknown-linux-gnu/Dockerfile+2-2

...	@@ -1,4 +1,4 @@	...	@@ -1,4 +1,4 @@
1	FROM ubuntu:25.04	1	FROM ubuntu:25.10
2	RUN apt-get update && apt-get install -y --no-install-recommends \	2	RUN apt-get update && apt-get install -y --no-install-recommends \
3	gcc \	3	gcc \
4	g++ \	4	g++ \
...	@@ -10,7 +10,7 @@ RUN apt-get update && apt-get install -y --no-install-recommends \	...	@@ -10,7 +10,7 @@ RUN apt-get update && apt-get install -y --no-install-recommends \
10	qemu-user \	10	qemu-user \
11	make \	11	make \
12	file \	12	file \
13	clang-19 \	13	clang \
14	lld	14	lld
15		15
16	ENV CARGO_TARGET_AARCH64_UNKNOWN_LINUX_GNU_LINKER=aarch64-linux-gnu-gcc \	16	ENV CARGO_TARGET_AARCH64_UNKNOWN_LINUX_GNU_LINKER=aarch64-linux-gnu-gcc \

library/stdarch/ci/docker/aarch64_be-unknown-linux-gnu/Dockerfile+4-4

...	@@ -1,4 +1,4 @@	...	@@ -1,4 +1,4 @@
1	FROM ubuntu:25.04	1	FROM ubuntu:25.10
2		2
3	RUN apt-get update && apt-get install -y --no-install-recommends \	3	RUN apt-get update && apt-get install -y --no-install-recommends \
4	gcc \	4	gcc \
...	@@ -9,15 +9,15 @@ RUN apt-get update && apt-get install -y --no-install-recommends \	...	@@ -9,15 +9,15 @@ RUN apt-get update && apt-get install -y --no-install-recommends \
9	qemu-user \	9	qemu-user \
10	make \	10	make \
11	file \	11	file \
12	clang-19 \	12	clang \
13	curl \	13	curl \
14	xz-utils \	14	xz-utils \
15	lld	15	lld
16		16
17	ENV TOOLCHAIN="arm-gnu-toolchain-14.2.rel1-x86_64-aarch64_be-none-linux-gnu"	17	ENV TOOLCHAIN="arm-gnu-toolchain-14.3.rel1-x86_64-aarch64_be-none-linux-gnu"
18		18
19	# Download the aarch64_be gcc toolchain	19	# Download the aarch64_be gcc toolchain
20	RUN curl -L "https://developer.arm.com/-/media/Files/downloads/gnu/14.2.rel1/binrel/${TOOLCHAIN}.tar.xz" -o "${TOOLCHAIN}.tar.xz"	20	RUN curl -L "https://developer.arm.com/-/media/Files/downloads/gnu/14.3.rel1/binrel/${TOOLCHAIN}.tar.xz" -o "${TOOLCHAIN}.tar.xz"
21	RUN tar -xvf "${TOOLCHAIN}.tar.xz"	21	RUN tar -xvf "${TOOLCHAIN}.tar.xz"
22	RUN mkdir /toolchains && mv "./${TOOLCHAIN}" /toolchains	22	RUN mkdir /toolchains && mv "./${TOOLCHAIN}" /toolchains
23		23

library/stdarch/ci/docker/arm-unknown-linux-gnueabihf/Dockerfile+1-1

...	@@ -1,4 +1,4 @@	...	@@ -1,4 +1,4 @@
1	FROM ubuntu:25.04	1	FROM ubuntu:25.10
2	RUN apt-get update && apt-get install -y --no-install-recommends \	2	RUN apt-get update && apt-get install -y --no-install-recommends \
3	gcc \	3	gcc \
4	ca-certificates \	4	ca-certificates \

library/stdarch/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile+1-1

...	@@ -10,7 +10,7 @@ RUN apt-get update && apt-get install -y --no-install-recommends \	...	@@ -10,7 +10,7 @@ RUN apt-get update && apt-get install -y --no-install-recommends \
10	qemu-user \	10	qemu-user \
11	make \	11	make \
12	file \	12	file \
13	clang-19 \	13	clang \
14	lld	14	lld
15	ENV CARGO_TARGET_ARMV7_UNKNOWN_LINUX_GNUEABIHF_LINKER=arm-linux-gnueabihf-gcc \	15	ENV CARGO_TARGET_ARMV7_UNKNOWN_LINUX_GNUEABIHF_LINKER=arm-linux-gnueabihf-gcc \
16	CARGO_TARGET_ARMV7_UNKNOWN_LINUX_GNUEABIHF_RUNNER="qemu-arm -cpu max -L /usr/arm-linux-gnueabihf" \	16	CARGO_TARGET_ARMV7_UNKNOWN_LINUX_GNUEABIHF_RUNNER="qemu-arm -cpu max -L /usr/arm-linux-gnueabihf" \

library/stdarch/ci/docker/i586-unknown-linux-gnu/Dockerfile+1-1

...	@@ -1,4 +1,4 @@	...	@@ -1,4 +1,4 @@
1	FROM ubuntu:25.04	1	FROM ubuntu:25.10
2	RUN apt-get update && apt-get install -y --no-install-recommends \	2	RUN apt-get update && apt-get install -y --no-install-recommends \
3	gcc-multilib \	3	gcc-multilib \
4	libc6-dev \	4	libc6-dev \

library/stdarch/ci/docker/i686-unknown-linux-gnu/Dockerfile+1-1

...	@@ -1,4 +1,4 @@	...	@@ -1,4 +1,4 @@
1	FROM ubuntu:25.04	1	FROM ubuntu:25.10
2	RUN apt-get update && apt-get install -y --no-install-recommends \	2	RUN apt-get update && apt-get install -y --no-install-recommends \
3	gcc-multilib \	3	gcc-multilib \
4	libc6-dev \	4	libc6-dev \

library/stdarch/ci/docker/loongarch64-unknown-linux-gnu/Dockerfile+2-2

...	@@ -1,9 +1,9 @@	...	@@ -1,9 +1,9 @@
1	FROM ubuntu:25.04	1	FROM ubuntu:25.10
2		2
3	RUN apt-get update && \	3	RUN apt-get update && \
4	apt-get install -y --no-install-recommends \	4	apt-get install -y --no-install-recommends \
5	gcc libc6-dev qemu-user-static ca-certificates \	5	gcc libc6-dev qemu-user-static ca-certificates \
6	gcc-14-loongarch64-linux-gnu libc6-dev-loong64-cross	6	gcc-loongarch64-linux-gnu libc6-dev-loong64-cross
7		7
8		8
9	ENV CARGO_TARGET_LOONGARCH64_UNKNOWN_LINUX_GNU_LINKER=loongarch64-linux-gnu-gcc-14 \	9	ENV CARGO_TARGET_LOONGARCH64_UNKNOWN_LINUX_GNU_LINKER=loongarch64-linux-gnu-gcc-14 \

library/stdarch/ci/docker/mips-unknown-linux-gnu/Dockerfile+1-1

...	@@ -1,4 +1,4 @@	...	@@ -1,4 +1,4 @@
1	FROM ubuntu:25.04	1	FROM ubuntu:25.10
2		2
3	RUN apt-get update && apt-get install -y --no-install-recommends \	3	RUN apt-get update && apt-get install -y --no-install-recommends \
4	gcc libc6-dev qemu-user ca-certificates \	4	gcc libc6-dev qemu-user ca-certificates \

library/stdarch/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile+1-1

...	@@ -1,4 +1,4 @@	...	@@ -1,4 +1,4 @@
1	FROM ubuntu:25.04	1	FROM ubuntu:25.10
2		2
3	RUN apt-get update && apt-get install -y --no-install-recommends \	3	RUN apt-get update && apt-get install -y --no-install-recommends \
4	gcc libc6-dev qemu-user ca-certificates \	4	gcc libc6-dev qemu-user ca-certificates \

library/stdarch/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile+1-1

...	@@ -1,4 +1,4 @@	...	@@ -1,4 +1,4 @@
1	FROM ubuntu:25.04	1	FROM ubuntu:25.10
2		2
3	RUN apt-get update && apt-get install -y --no-install-recommends \	3	RUN apt-get update && apt-get install -y --no-install-recommends \
4	gcc libc6-dev qemu-user ca-certificates \	4	gcc libc6-dev qemu-user ca-certificates \

library/stdarch/ci/docker/mipsel-unknown-linux-musl/Dockerfile+1-1

...	@@ -1,4 +1,4 @@	...	@@ -1,4 +1,4 @@
1	FROM ubuntu:25.04	1	FROM ubuntu:25.10
2		2
3	RUN apt-get update && \	3	RUN apt-get update && \
4	apt-get install -y --no-install-recommends \	4	apt-get install -y --no-install-recommends \

library/stdarch/ci/docker/nvptx64-nvidia-cuda/Dockerfile+1-1

...	@@ -1,4 +1,4 @@	...	@@ -1,4 +1,4 @@
1	FROM ubuntu:25.04	1	FROM ubuntu:25.10
2	RUN apt-get update && apt-get install -y --no-install-recommends \	2	RUN apt-get update && apt-get install -y --no-install-recommends \
3	gcc \	3	gcc \
4	libc6-dev \	4	libc6-dev \

library/stdarch/ci/docker/powerpc-unknown-linux-gnu/Dockerfile+1-1

...	@@ -1,4 +1,4 @@	...	@@ -1,4 +1,4 @@
1	FROM ubuntu:25.04	1	FROM ubuntu:25.10
2		2
3	RUN apt-get update && apt-get install -y --no-install-recommends \	3	RUN apt-get update && apt-get install -y --no-install-recommends \
4	gcc libc6-dev qemu-user ca-certificates \	4	gcc libc6-dev qemu-user ca-certificates \

library/stdarch/ci/docker/powerpc64-unknown-linux-gnu/Dockerfile+1-1

...	@@ -1,4 +1,4 @@	...	@@ -1,4 +1,4 @@
1	FROM ubuntu:25.04	1	FROM ubuntu:25.10
2		2
3	RUN apt-get update && apt-get install -y --no-install-recommends \	3	RUN apt-get update && apt-get install -y --no-install-recommends \
4	gcc libc6-dev qemu-user ca-certificates \	4	gcc libc6-dev qemu-user ca-certificates \

library/stdarch/ci/docker/powerpc64le-unknown-linux-gnu/Dockerfile+1-1

...	@@ -1,4 +1,4 @@	...	@@ -1,4 +1,4 @@
1	FROM ubuntu:25.04	1	FROM ubuntu:25.10
2		2
3	RUN apt-get update && apt-get install -y --no-install-recommends \	3	RUN apt-get update && apt-get install -y --no-install-recommends \
4	gcc libc6-dev qemu-user ca-certificates \	4	gcc libc6-dev qemu-user ca-certificates \

library/stdarch/ci/docker/riscv32gc-unknown-linux-gnu/Dockerfile+2-2

...	@@ -1,10 +1,10 @@	...	@@ -1,10 +1,10 @@
1	FROM ubuntu:25.04	1	FROM ubuntu:25.10
2		2
3	RUN apt-get update && apt-get install -y --no-install-recommends \	3	RUN apt-get update && apt-get install -y --no-install-recommends \
4	gcc libc6-dev qemu-user ca-certificates \	4	gcc libc6-dev qemu-user ca-certificates \
5	wget xz-utils make file llvm	5	wget xz-utils make file llvm
6		6
7	ENV VERSION=2025.01.20	7	ENV VERSION=2025.07.03
8		8
9	RUN wget "https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/${VERSION}/riscv32-glibc-ubuntu-24.04-gcc-nightly-${VERSION}-nightly.tar.xz" \	9	RUN wget "https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/${VERSION}/riscv32-glibc-ubuntu-24.04-gcc-nightly-${VERSION}-nightly.tar.xz" \
10	-O riscv-toolchain.tar.xz	10	-O riscv-toolchain.tar.xz

library/stdarch/ci/docker/riscv64gc-unknown-linux-gnu/Dockerfile+1-1

...	@@ -1,4 +1,4 @@	...	@@ -1,4 +1,4 @@
1	FROM ubuntu:25.04	1	FROM ubuntu:25.10
2		2
3	RUN apt-get update && apt-get install -y --no-install-recommends \	3	RUN apt-get update && apt-get install -y --no-install-recommends \
4	gcc libc6-dev qemu-user ca-certificates \	4	gcc libc6-dev qemu-user ca-certificates \

library/stdarch/ci/docker/s390x-unknown-linux-gnu/Dockerfile+1-1

...	@@ -1,4 +1,4 @@	...	@@ -1,4 +1,4 @@
1	FROM ubuntu:25.04	1	FROM ubuntu:25.10
2		2
3	RUN apt-get update && apt-get install -y --no-install-recommends \	3	RUN apt-get update && apt-get install -y --no-install-recommends \
4	curl ca-certificates \	4	curl ca-certificates \

library/stdarch/ci/docker/wasm32-wasip1/Dockerfile+5-3

...	@@ -1,4 +1,4 @@	...	@@ -1,4 +1,4 @@
1	FROM ubuntu:25.04	1	FROM ubuntu:25.10
2		2
3	ENV DEBIAN_FRONTEND=noninteractive	3	ENV DEBIAN_FRONTEND=noninteractive
4	RUN apt-get update -y && apt-get install -y --no-install-recommends \	4	RUN apt-get update -y && apt-get install -y --no-install-recommends \
...	@@ -7,7 +7,9 @@ RUN apt-get update -y && apt-get install -y --no-install-recommends \	...	@@ -7,7 +7,9 @@ RUN apt-get update -y && apt-get install -y --no-install-recommends \
7	xz-utils \	7	xz-utils \
8	clang	8	clang
9		9
10	RUN curl -L https://github.com/bytecodealliance/wasmtime/releases/download/v18.0.2/wasmtime-v18.0.2-x86_64-linux.tar.xz \| tar xJf -	10	ENV VERSION=v34.0.1
11	ENV PATH=$PATH:/wasmtime-v18.0.2-x86_64-linux	11
		12	RUN curl -L https://github.com/bytecodealliance/wasmtime/releases/download/${VERSION}/wasmtime-${VERSION}-x86_64-linux.tar.xz \| tar xJf -
		13	ENV PATH=$PATH:/wasmtime-${VERSION}-x86_64-linux
12		14
13	ENV CARGO_TARGET_WASM32_WASIP1_RUNNER="wasmtime --dir /checkout/target/wasm32-wasip1/release/deps::."	15	ENV CARGO_TARGET_WASM32_WASIP1_RUNNER="wasmtime --dir /checkout/target/wasm32-wasip1/release/deps::."

library/stdarch/ci/docker/x86_64-unknown-linux-gnu/Dockerfile+2-2

...	@@ -1,4 +1,4 @@	...	@@ -1,4 +1,4 @@
1	FROM ubuntu:25.04	1	FROM ubuntu:25.10
2	RUN apt-get update && apt-get install -y --no-install-recommends \	2	RUN apt-get update && apt-get install -y --no-install-recommends \
3	gcc \	3	gcc \
4	libc6-dev \	4	libc6-dev \
...	@@ -8,7 +8,7 @@ RUN apt-get update && apt-get install -y --no-install-recommends \	...	@@ -8,7 +8,7 @@ RUN apt-get update && apt-get install -y --no-install-recommends \
8	wget \	8	wget \
9	xz-utils	9	xz-utils
10		10
11	RUN wget http://ci-mirrors.rust-lang.org/stdarch/sde-external-9.53.0-2025-03-16-lin.tar.xz -O sde.tar.xz	11	RUN wget http://ci-mirrors.rust-lang.org/stdarch/sde-external-9.58.0-2025-06-16-lin.tar.xz -O sde.tar.xz
12	RUN mkdir intel-sde	12	RUN mkdir intel-sde
13	RUN tar -xJf sde.tar.xz --strip-components=1 -C intel-sde	13	RUN tar -xJf sde.tar.xz --strip-components=1 -C intel-sde
14	ENV CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER="/intel-sde/sde64 \	14	ENV CARGO_TARGET_X86_64_UNKNOWN_LINUX_GNU_RUNNER="/intel-sde/sde64 \

library/stdarch/ci/docker/x86_64-unknown-linux-gnu/cpuid.def+14-22

 @@ -1,41 +1,35 @@
-# Copyright (C) 2024-2024 Intel Corporation.
+# Copyright (C) 2017-2025 Intel Corporation.
 #
 # This software and the related documents are Intel copyrighted materials, and your
 # use of them is governed by the express license under which they were provided to
 # you ("License"). Unless the License provides otherwise, you may not use, modify,
 # copy, publish, distribute, disclose or transmit this software or the related
 # documents without Intel's prior written permission.
 #
 # This software and the related documents are provided as is, with no express or
 # implied warranties, other than those that are expressly stated in the License.
 #
-# The CPUID information in this file is for software enabling purposes only and
-# it is not a full and accurate representation of the CPU under development which
-# it represents.
-# The CPUID information in this file is not a guarantee of the availability of
-# features or characteristics in the final released CPU.
-#
 # CPUID_VERSION = 1.0
 #      Input      =>               Output
 # EAX      ECX    =>   EAX      EBX      ECX      EDX
 00000000 ******** => 00000024 68747541 444d4163 69746e65
-00000001 ******** => 000d06f0 00100800 7ffaf3ff bfebfbff
+00000001 ******** => 00400f10 00100800 7ffaf3ff bfebfbff
 00000002 ******** => 76035a01 00f0b6ff 00000000 00c10000
 00000003 ******** => 00000000 00000000 00000000 00000000
-00000004 00000000 => 7c004121 02c0003f 0000003f 00000000 #Deterministic Cache
+00000004 00000000 => 7c004121 01c0003f 0000003f 00000000 #Deterministic Cache
 00000004 00000001 => 7c004122 01c0003f 0000003f 00000000
-00000004 00000002 => 7c004143 03c0003f 000007ff 00000000
+00000004 00000002 => 7c004143 03c0003f 000003ff 00000000
-00000004 00000003 => 7c0fc163 04c0003f 0005ffff 00000004
+00000004 00000003 => 7c0fc163 0280003f 0000dfff 00000004
 00000004 00000004 => 00000000 00000000 00000000 00000000
 00000005 ******** => 00000040 00000040 00000003 00042120 #MONITOR/MWAIT
 00000006 ******** => 00000077 00000002 00000001 00000000 #Thermal and Power
-00000007 00000000 => 00000001 f3bfbfbf bbc05ffe 03d55130 #Extended Features
+00000007 00000000 => 00000001 f3bfbfbf bac05ffe 03d54130 #Extended Features
-00000007 00000001 => 88ee00bf 00000002 00000000 1d29cd3e
+00000007 00000001 => 98ee00bf 00000002 00000020 1d29cd3e
 00000008 ******** => 00000000 00000000 00000000 00000000
 00000009 ******** => 00000000 00000000 00000000 00000000 #Direct Cache
 0000000a ******** => 07300403 00000000 00000000 00000603
-0000000b 00000000 => 00000001 00000002 00000100 0000001e #Extended Topology
+0000000b 00000000 => 00000001 00000002 00000100 00000000 #Extended Topology
-0000000b 00000001 => 00000004 00000002 00000201 0000001e
+0000000b 00000001 => 00000004 00000002 00000201 00000000
 0000000c ******** => 00000000 00000000 00000000 00000000
 0000000d 00000000 => 000e02e7 00002b00 00002b00 00000000 #xcr0
 0000000d 00000001 => 0000001f 00000240 00000100 00000000
 @@ -52,10 +46,8 @@
 0000001d 00000001 => 04002000 00080040 00000010 00000000 #AMX Palette1
 0000001e 00000000 => 00000001 00004010 00000000 00000000 #AMX Tmul
 0000001e 00000001 => 000001ff 00000000 00000000 00000000
-0000001f 00000000 => 00000001 00000002 00000100 0000001e
+00000024 00000000 => 00000001 00070002 00000000 00000000 #AVX10
-0000001f 00000001 => 00000007 00000070 00000201 0000001e
+00000024 00000001 => 00000000 00000000 00000004 00000000
-0000001f 00000002 => 00000000 00000000 00000002 0000001e
-00000024 00000000 => 00000000 00070002 00000000 00000000 #AVX10
 80000000 ******** => 80000008 00000000 00000000 00000000
 80000001 ******** => 00000000 00000000 00200961 2c100000
 80000002 ******** => 00000000 00000000 00000000 00000000
 @@ -66,6 +58,6 @@
 80000007 ******** => 00000000 00000000 00000000 00000100
 80000008 ******** => 00003028 00000200 00000200 00000000
-# This file was copied from intel-sde/misc/cpuid/dmr/cpuid.def, and modified to
+# This file was copied from intel-sde/misc/cpuid/future/cpuid.def, and modified to
 # use "AuthenticAMD" as the vendor and the support for `XOP`, `SSE4a`, `TBM`,
 # `AVX512_VP2INTERSECT` and the VEX variants of AVX512 was added in the CPUID.

library/stdarch/ci/run.sh+3-3

library/stdarch/crates/core_arch/src/aarch64/neon/generated.rs+100-496

 @@ -51,7 +51,7 @@ pub fn __crc32d(crc: u32, data: u64) -> u32 {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal2))]
 pub fn vabal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t {
     unsafe {
         let d: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
 @@ -66,7 +66,7 @@ pub fn vabal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal2))]
 pub fn vabal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
     unsafe {
         let d: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
 @@ -81,7 +81,7 @@ pub fn vabal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal2))]
 pub fn vabal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
     unsafe {
         let d: int32x2_t = simd_shuffle!(b, b, [2, 3]);
 @@ -96,7 +96,7 @@ pub fn vabal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal2))]
 pub fn vabal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t {
     unsafe {
         let d: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
 @@ -110,7 +110,7 @@ pub fn vabal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal2))]
 pub fn vabal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t {
     unsafe {
         let d: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
 @@ -124,7 +124,7 @@ pub fn vabal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal))]
+#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal2))]
 pub fn vabal_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t {
     unsafe {
         let d: uint32x2_t = simd_shuffle!(b, b, [2, 3]);
 @@ -197,7 +197,7 @@ pub fn vabdh_f16(a: f16, b: f16) -> f16 {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(sabdl))]
+#[cfg_attr(test, assert_instr(sabdl2))]
 pub fn vabdl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
     unsafe {
         let c: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
 @@ -211,7 +211,7 @@ pub fn vabdl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(sabdl))]
+#[cfg_attr(test, assert_instr(sabdl2))]
 pub fn vabdl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
     unsafe {
         let c: int32x2_t = simd_shuffle!(a, a, [2, 3]);
 @@ -225,7 +225,7 @@ pub fn vabdl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(sabdl))]
+#[cfg_attr(test, assert_instr(sabdl2))]
 pub fn vabdl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
     unsafe {
         let c: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
 @@ -238,7 +238,7 @@ pub fn vabdl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u8)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(uabdl))]
+#[cfg_attr(test, assert_instr(uabdl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vabdl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
     unsafe {
 @@ -251,7 +251,7 @@ pub fn vabdl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u16)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(uabdl))]
+#[cfg_attr(test, assert_instr(uabdl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vabdl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
     unsafe {
 @@ -264,7 +264,7 @@ pub fn vabdl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(uabdl))]
+#[cfg_attr(test, assert_instr(uabdl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vabdl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
     unsafe {
 @@ -298,46 +298,40 @@ pub fn vabsq_f64(a: float64x2_t) -> float64x2_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(abs))]
 pub fn vabs_s64(a: int64x1_t) -> int64x1_t {
-    unsafe extern "unadjusted" {
+    unsafe {
-        #[cfg_attr(
+        let neg: int64x1_t = simd_neg(a);
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
+        let mask: int64x1_t = simd_ge(a, neg);
-            link_name = "llvm.aarch64.neon.abs.v1i64"
+        simd_select(mask, a, neg)
-        )]
-        fn _vabs_s64(a: int64x1_t) -> int64x1_t;
     }
-    unsafe { _vabs_s64(a) }
 }
 #[doc = "Absolute Value (wrapping)."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsd_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s64)"]
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(abs))]
-pub fn vabsd_s64(a: i64) -> i64 {
+pub fn vabsq_s64(a: int64x2_t) -> int64x2_t {
-    unsafe extern "unadjusted" {
+    unsafe {
-        #[cfg_attr(
+        let neg: int64x2_t = simd_neg(a);
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
+        let mask: int64x2_t = simd_ge(a, neg);
-            link_name = "llvm.aarch64.neon.abs.i64"
+        simd_select(mask, a, neg)
-        )]
-        fn _vabsd_s64(a: i64) -> i64;
     }
-    unsafe { _vabsd_s64(a) }
 }
 #[doc = "Absolute Value (wrapping)."]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s64)"]
+#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsd_s64)"]
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(abs))]
-pub fn vabsq_s64(a: int64x2_t) -> int64x2_t {
+pub fn vabsd_s64(a: i64) -> i64 {
     unsafe extern "unadjusted" {
         #[cfg_attr(
             any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.abs.v2i64"
+            link_name = "llvm.aarch64.neon.abs.i64"
         )]
-        fn _vabsq_s64(a: int64x2_t) -> int64x2_t;
+        fn _vabsd_s64(a: i64) -> i64;
     }
-    unsafe { _vabsq_s64(a) }
+    unsafe { _vabsd_s64(a) }
 }
 #[doc = "Add"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddd_s64)"]
 @@ -604,14 +598,7 @@ pub fn vaddvq_f64(a: float64x2_t) -> f64 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
 pub fn vaddv_s32(a: int32x2_t) -> i32 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_add_unordered(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.saddv.i32.v2i32"
-        )]
-        fn _vaddv_s32(a: int32x2_t) -> i32;
-    }
-    unsafe { _vaddv_s32(a) }
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_s8)"]
 @@ -620,14 +607,7 @@ pub fn vaddv_s32(a: int32x2_t) -> i32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
 pub fn vaddv_s8(a: int8x8_t) -> i8 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_add_unordered(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.saddv.i8.v8i8"
-        )]
-        fn _vaddv_s8(a: int8x8_t) -> i8;
-    }
-    unsafe { _vaddv_s8(a) }
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s8)"]
 @@ -636,14 +616,7 @@ pub fn vaddv_s8(a: int8x8_t) -> i8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
 pub fn vaddvq_s8(a: int8x16_t) -> i8 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_add_unordered(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.saddv.i8.v16i8"
-        )]
-        fn _vaddvq_s8(a: int8x16_t) -> i8;
-    }
-    unsafe { _vaddvq_s8(a) }
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_s16)"]
 @@ -652,14 +625,7 @@ pub fn vaddvq_s8(a: int8x16_t) -> i8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
 pub fn vaddv_s16(a: int16x4_t) -> i16 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_add_unordered(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.saddv.i16.v4i16"
-        )]
-        fn _vaddv_s16(a: int16x4_t) -> i16;
-    }
-    unsafe { _vaddv_s16(a) }
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s16)"]
 @@ -668,14 +634,7 @@ pub fn vaddv_s16(a: int16x4_t) -> i16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
 pub fn vaddvq_s16(a: int16x8_t) -> i16 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_add_unordered(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.saddv.i16.v8i16"
-        )]
-        fn _vaddvq_s16(a: int16x8_t) -> i16;
-    }
-    unsafe { _vaddvq_s16(a) }
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s32)"]
 @@ -684,14 +643,7 @@ pub fn vaddvq_s16(a: int16x8_t) -> i16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
 pub fn vaddvq_s32(a: int32x4_t) -> i32 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_add_unordered(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.saddv.i32.v4i32"
-        )]
-        fn _vaddvq_s32(a: int32x4_t) -> i32;
-    }
-    unsafe { _vaddvq_s32(a) }
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_u32)"]
 @@ -700,14 +652,7 @@ pub fn vaddvq_s32(a: int32x4_t) -> i32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
 pub fn vaddv_u32(a: uint32x2_t) -> u32 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_add_unordered(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.uaddv.i32.v2i32"
-        )]
-        fn _vaddv_u32(a: uint32x2_t) -> u32;
-    }
-    unsafe { _vaddv_u32(a) }
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_u8)"]
 @@ -716,14 +661,7 @@ pub fn vaddv_u32(a: uint32x2_t) -> u32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
 pub fn vaddv_u8(a: uint8x8_t) -> u8 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_add_unordered(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.uaddv.i8.v8i8"
-        )]
-        fn _vaddv_u8(a: uint8x8_t) -> u8;
-    }
-    unsafe { _vaddv_u8(a) }
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u8)"]
 @@ -732,14 +670,7 @@ pub fn vaddv_u8(a: uint8x8_t) -> u8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
 pub fn vaddvq_u8(a: uint8x16_t) -> u8 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_add_unordered(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.uaddv.i8.v16i8"
-        )]
-        fn _vaddvq_u8(a: uint8x16_t) -> u8;
-    }
-    unsafe { _vaddvq_u8(a) }
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_u16)"]
 @@ -748,14 +679,7 @@ pub fn vaddvq_u8(a: uint8x16_t) -> u8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
 pub fn vaddv_u16(a: uint16x4_t) -> u16 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_add_unordered(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.uaddv.i16.v4i16"
-        )]
-        fn _vaddv_u16(a: uint16x4_t) -> u16;
-    }
-    unsafe { _vaddv_u16(a) }
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u16)"]
 @@ -764,14 +688,7 @@ pub fn vaddv_u16(a: uint16x4_t) -> u16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
 pub fn vaddvq_u16(a: uint16x8_t) -> u16 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_add_unordered(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.uaddv.i16.v8i16"
-        )]
-        fn _vaddvq_u16(a: uint16x8_t) -> u16;
-    }
-    unsafe { _vaddvq_u16(a) }
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u32)"]
 @@ -780,14 +697,7 @@ pub fn vaddvq_u16(a: uint16x8_t) -> u16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addv))]
 pub fn vaddvq_u32(a: uint32x4_t) -> u32 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_add_unordered(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.uaddv.i32.v4i32"
-        )]
-        fn _vaddvq_u32(a: uint32x4_t) -> u32;
-    }
-    unsafe { _vaddvq_u32(a) }
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s64)"]
 @@ -796,14 +706,7 @@ pub fn vaddvq_u32(a: uint32x4_t) -> u32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
 pub fn vaddvq_s64(a: int64x2_t) -> i64 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_add_unordered(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.saddv.i64.v2i64"
-        )]
-        fn _vaddvq_s64(a: int64x2_t) -> i64;
-    }
-    unsafe { _vaddvq_s64(a) }
 }
 #[doc = "Add across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u64)"]
 @@ -812,14 +715,7 @@ pub fn vaddvq_s64(a: int64x2_t) -> i64 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
 pub fn vaddvq_u64(a: uint64x2_t) -> u64 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_add_unordered(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.uaddv.i64.v2i64"
-        )]
-        fn _vaddvq_u64(a: uint64x2_t) -> u64;
-    }
-    unsafe { _vaddvq_u64(a) }
 }
 #[doc = "Multi-vector floating-point absolute maximum"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vamax_f32)"]
 @@ -7281,7 +7177,7 @@ pub fn vcvt_high_f32_f16(a: float16x8_t) -> float32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f32_f64)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(fcvtn))]
+#[cfg_attr(test, assert_instr(fcvtn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcvt_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t {
     unsafe { simd_shuffle!(a, simd_cast(b), [0, 1, 2, 3]) }
 @@ -7290,7 +7186,7 @@ pub fn vcvt_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f64_f32)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(fcvtl))]
+#[cfg_attr(test, assert_instr(fcvtl2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcvt_high_f64_f32(a: float32x4_t) -> float64x2_t {
     unsafe {
 @@ -9390,7 +9286,7 @@ pub fn vcvtx_f32_f64(a: float64x2_t) -> float32x2_t {
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtx_high_f32_f64)"]
 #[inline]
 #[target_feature(enable = "neon")]
-#[cfg_attr(test, assert_instr(fcvtxn))]
+#[cfg_attr(test, assert_instr(fcvtxn2))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vcvtx_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t {
     unsafe { simd_shuffle!(a, vcvtx_f32_f64(b), [0, 1, 2, 3]) }
 @@ -13229,14 +13125,7 @@ pub fn vmaxh_f16(a: f16, b: f16) -> f16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxnm))]
 pub fn vmaxnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
-    unsafe extern "unadjusted" {
+    unsafe { simd_fmax(a, b) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.fmaxnm.v1f64"
-        )]
-        fn _vmaxnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t;
-    }
-    unsafe { _vmaxnm_f64(a, b) }
 }
 #[doc = "Floating-point Maximum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f64)"]
 @@ -13245,14 +13134,7 @@ pub fn vmaxnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxnm))]
 pub fn vmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
-    unsafe extern "unadjusted" {
+    unsafe { simd_fmax(a, b) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.fmaxnm.v2f64"
-        )]
-        fn _vmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t;
-    }
-    unsafe { _vmaxnmq_f64(a, b) }
 }
 #[doc = "Floating-point Maximum Number"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmh_f16)"]
 @@ -13261,14 +13143,7 @@ pub fn vmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg_attr(test, assert_instr(fmaxnm))]
 pub fn vmaxnmh_f16(a: f16, b: f16) -> f16 {
-    unsafe extern "unadjusted" {
+    f16::max(a, b)
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.fmaxnm.f16"
-        )]
-        fn _vmaxnmh_f16(a: f16, b: f16) -> f16;
-    }
-    unsafe { _vmaxnmh_f16(a, b) }
 }
 #[doc = "Floating-point maximum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmv_f16)"]
 @@ -13277,14 +13152,7 @@ pub fn vmaxnmh_f16(a: f16, b: f16) -> f16 {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg_attr(test, assert_instr(fmaxnmv))]
 pub fn vmaxnmv_f16(a: float16x4_t) -> f16 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_max(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.fmaxnmv.f16.v4f16"
-        )]
-        fn _vmaxnmv_f16(a: float16x4_t) -> f16;
-    }
-    unsafe { _vmaxnmv_f16(a) }
 }
 #[doc = "Floating-point maximum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f16)"]
 @@ -13293,14 +13161,7 @@ pub fn vmaxnmv_f16(a: float16x4_t) -> f16 {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg_attr(test, assert_instr(fmaxnmv))]
 pub fn vmaxnmvq_f16(a: float16x8_t) -> f16 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_max(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.fmaxnmv.f16.v8f16"
-        )]
-        fn _vmaxnmvq_f16(a: float16x8_t) -> f16;
-    }
-    unsafe { _vmaxnmvq_f16(a) }
 }
 #[doc = "Floating-point maximum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmv_f32)"]
 @@ -13309,14 +13170,7 @@ pub fn vmaxnmvq_f16(a: float16x8_t) -> f16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxnmp))]
 pub fn vmaxnmv_f32(a: float32x2_t) -> f32 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_max(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.fmaxnmv.f32.v2f32"
-        )]
-        fn _vmaxnmv_f32(a: float32x2_t) -> f32;
-    }
-    unsafe { _vmaxnmv_f32(a) }
 }
 #[doc = "Floating-point maximum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f64)"]
 @@ -13325,14 +13179,7 @@ pub fn vmaxnmv_f32(a: float32x2_t) -> f32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxnmp))]
 pub fn vmaxnmvq_f64(a: float64x2_t) -> f64 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_max(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.fmaxnmv.f64.v2f64"
-        )]
-        fn _vmaxnmvq_f64(a: float64x2_t) -> f64;
-    }
-    unsafe { _vmaxnmvq_f64(a) }
 }
 #[doc = "Floating-point maximum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f32)"]
 @@ -13341,14 +13188,7 @@ pub fn vmaxnmvq_f64(a: float64x2_t) -> f64 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fmaxnmv))]
 pub fn vmaxnmvq_f32(a: float32x4_t) -> f32 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_max(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.fmaxnmv.f32.v4f32"
-        )]
-        fn _vmaxnmvq_f32(a: float32x4_t) -> f32;
-    }
-    unsafe { _vmaxnmvq_f32(a) }
 }
 #[doc = "Floating-point maximum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_f16)"]
 @@ -13437,14 +13277,7 @@ pub fn vmaxvq_f64(a: float64x2_t) -> f64 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxv))]
 pub fn vmaxv_s8(a: int8x8_t) -> i8 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_max(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.smaxv.i8.v8i8"
-        )]
-        fn _vmaxv_s8(a: int8x8_t) -> i8;
-    }
-    unsafe { _vmaxv_s8(a) }
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s8)"]
 @@ -13453,14 +13286,7 @@ pub fn vmaxv_s8(a: int8x8_t) -> i8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxv))]
 pub fn vmaxvq_s8(a: int8x16_t) -> i8 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_max(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.smaxv.i8.v16i8"
-        )]
-        fn _vmaxvq_s8(a: int8x16_t) -> i8;
-    }
-    unsafe { _vmaxvq_s8(a) }
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_s16)"]
 @@ -13469,14 +13295,7 @@ pub fn vmaxvq_s8(a: int8x16_t) -> i8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxv))]
 pub fn vmaxv_s16(a: int16x4_t) -> i16 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_max(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.smaxv.i16.v4i16"
-        )]
-        fn _vmaxv_s16(a: int16x4_t) -> i16;
-    }
-    unsafe { _vmaxv_s16(a) }
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s16)"]
 @@ -13485,14 +13304,7 @@ pub fn vmaxv_s16(a: int16x4_t) -> i16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxv))]
 pub fn vmaxvq_s16(a: int16x8_t) -> i16 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_max(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.smaxv.i16.v8i16"
-        )]
-        fn _vmaxvq_s16(a: int16x8_t) -> i16;
-    }
-    unsafe { _vmaxvq_s16(a) }
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_s32)"]
 @@ -13501,14 +13313,7 @@ pub fn vmaxvq_s16(a: int16x8_t) -> i16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxp))]
 pub fn vmaxv_s32(a: int32x2_t) -> i32 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_max(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.smaxv.i32.v2i32"
-        )]
-        fn _vmaxv_s32(a: int32x2_t) -> i32;
-    }
-    unsafe { _vmaxv_s32(a) }
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s32)"]
 @@ -13517,14 +13322,7 @@ pub fn vmaxv_s32(a: int32x2_t) -> i32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(smaxv))]
 pub fn vmaxvq_s32(a: int32x4_t) -> i32 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_max(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.smaxv.i32.v4i32"
-        )]
-        fn _vmaxvq_s32(a: int32x4_t) -> i32;
-    }
-    unsafe { _vmaxvq_s32(a) }
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_u8)"]
 @@ -13533,14 +13331,7 @@ pub fn vmaxvq_s32(a: int32x4_t) -> i32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxv))]
 pub fn vmaxv_u8(a: uint8x8_t) -> u8 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_max(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.umaxv.i8.v8i8"
-        )]
-        fn _vmaxv_u8(a: uint8x8_t) -> u8;
-    }
-    unsafe { _vmaxv_u8(a) }
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u8)"]
 @@ -13549,14 +13340,7 @@ pub fn vmaxv_u8(a: uint8x8_t) -> u8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxv))]
 pub fn vmaxvq_u8(a: uint8x16_t) -> u8 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_max(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.umaxv.i8.v16i8"
-        )]
-        fn _vmaxvq_u8(a: uint8x16_t) -> u8;
-    }
-    unsafe { _vmaxvq_u8(a) }
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_u16)"]
 @@ -13565,14 +13349,7 @@ pub fn vmaxvq_u8(a: uint8x16_t) -> u8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxv))]
 pub fn vmaxv_u16(a: uint16x4_t) -> u16 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_max(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.umaxv.i16.v4i16"
-        )]
-        fn _vmaxv_u16(a: uint16x4_t) -> u16;
-    }
-    unsafe { _vmaxv_u16(a) }
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u16)"]
 @@ -13581,14 +13358,7 @@ pub fn vmaxv_u16(a: uint16x4_t) -> u16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxv))]
 pub fn vmaxvq_u16(a: uint16x8_t) -> u16 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_max(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.umaxv.i16.v8i16"
-        )]
-        fn _vmaxvq_u16(a: uint16x8_t) -> u16;
-    }
-    unsafe { _vmaxvq_u16(a) }
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_u32)"]
 @@ -13597,14 +13367,7 @@ pub fn vmaxvq_u16(a: uint16x8_t) -> u16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxp))]
 pub fn vmaxv_u32(a: uint32x2_t) -> u32 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_max(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.umaxv.i32.v2i32"
-        )]
-        fn _vmaxv_u32(a: uint32x2_t) -> u32;
-    }
-    unsafe { _vmaxv_u32(a) }
 }
 #[doc = "Horizontal vector max."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u32)"]
 @@ -13613,14 +13376,7 @@ pub fn vmaxv_u32(a: uint32x2_t) -> u32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(umaxv))]
 pub fn vmaxvq_u32(a: uint32x4_t) -> u32 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_max(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.umaxv.i32.v4i32"
-        )]
-        fn _vmaxvq_u32(a: uint32x4_t) -> u32;
-    }
-    unsafe { _vmaxvq_u32(a) }
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f64)"]
 @@ -13677,14 +13433,7 @@ pub fn vminh_f16(a: f16, b: f16) -> f16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fminnm))]
 pub fn vminnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
-    unsafe extern "unadjusted" {
+    unsafe { simd_fmin(a, b) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.fminnm.v1f64"
-        )]
-        fn _vminnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t;
-    }
-    unsafe { _vminnm_f64(a, b) }
 }
 #[doc = "Floating-point Minimum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f64)"]
 @@ -13693,14 +13442,7 @@ pub fn vminnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(fminnm))]
 pub fn vminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
-    unsafe extern "unadjusted" {
+    unsafe { simd_fmin(a, b) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.fminnm.v2f64"
-        )]
-        fn _vminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t;
-    }
-    unsafe { _vminnmq_f64(a, b) }
 }
 #[doc = "Floating-point Minimum Number"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmh_f16)"]
 @@ -13709,14 +13451,7 @@ pub fn vminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg_attr(test, assert_instr(fminnm))]
 pub fn vminnmh_f16(a: f16, b: f16) -> f16 {
-    unsafe extern "unadjusted" {
+    f16::min(a, b)
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.fminnm.f16"
-        )]
-        fn _vminnmh_f16(a: f16, b: f16) -> f16;
-    }
-    unsafe { _vminnmh_f16(a, b) }
 }
 #[doc = "Floating-point minimum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmv_f16)"]
 @@ -13725,14 +13460,7 @@ pub fn vminnmh_f16(a: f16, b: f16) -> f16 {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg_attr(test, assert_instr(fminnmv))]
 pub fn vminnmv_f16(a: float16x4_t) -> f16 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_min(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.fminnmv.f16.v4f16"
-        )]
-        fn _vminnmv_f16(a: float16x4_t) -> f16;
-    }
-    unsafe { _vminnmv_f16(a) }
 }
 #[doc = "Floating-point minimum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f16)"]
 @@ -13741,14 +13469,7 @@ pub fn vminnmv_f16(a: float16x4_t) -> f16 {
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 #[cfg_attr(test, assert_instr(fminnmv))]
 pub fn vminnmvq_f16(a: float16x8_t) -> f16 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_min(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.fminnmv.f16.v8f16"
-        )]
-        fn _vminnmvq_f16(a: float16x8_t) -> f16;
-    }
-    unsafe { _vminnmvq_f16(a) }
 }
 #[doc = "Floating-point minimum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmv_f32)"]
 @@ -13757,14 +13478,7 @@ pub fn vminnmvq_f16(a: float16x8_t) -> f16 {
 #[cfg_attr(test, assert_instr(fminnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vminnmv_f32(a: float32x2_t) -> f32 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_min(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.fminnmv.f32.v2f32"
-        )]
-        fn _vminnmv_f32(a: float32x2_t) -> f32;
-    }
-    unsafe { _vminnmv_f32(a) }
 }
 #[doc = "Floating-point minimum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f64)"]
 @@ -13773,14 +13487,7 @@ pub fn vminnmv_f32(a: float32x2_t) -> f32 {
 #[cfg_attr(test, assert_instr(fminnmp))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vminnmvq_f64(a: float64x2_t) -> f64 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_min(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.fminnmv.f64.v2f64"
-        )]
-        fn _vminnmvq_f64(a: float64x2_t) -> f64;
-    }
-    unsafe { _vminnmvq_f64(a) }
 }
 #[doc = "Floating-point minimum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f32)"]
 @@ -13789,14 +13496,7 @@ pub fn vminnmvq_f64(a: float64x2_t) -> f64 {
 #[cfg_attr(test, assert_instr(fminnmv))]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 pub fn vminnmvq_f32(a: float32x4_t) -> f32 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_min(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.fminnmv.f32.v4f32"
-        )]
-        fn _vminnmvq_f32(a: float32x4_t) -> f32;
-    }
-    unsafe { _vminnmvq_f32(a) }
 }
 #[doc = "Floating-point minimum number across vector"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_f16)"]
 @@ -13885,14 +13585,7 @@ pub fn vminvq_f64(a: float64x2_t) -> f64 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminv))]
 pub fn vminv_s8(a: int8x8_t) -> i8 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_min(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.sminv.i8.v8i8"
-        )]
-        fn _vminv_s8(a: int8x8_t) -> i8;
-    }
-    unsafe { _vminv_s8(a) }
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_s8)"]
 @@ -13901,14 +13594,7 @@ pub fn vminv_s8(a: int8x8_t) -> i8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminv))]
 pub fn vminvq_s8(a: int8x16_t) -> i8 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_min(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.sminv.i8.v16i8"
-        )]
-        fn _vminvq_s8(a: int8x16_t) -> i8;
-    }
-    unsafe { _vminvq_s8(a) }
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_s16)"]
 @@ -13917,14 +13603,7 @@ pub fn vminvq_s8(a: int8x16_t) -> i8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminv))]
 pub fn vminv_s16(a: int16x4_t) -> i16 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_min(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.sminv.i16.v4i16"
-        )]
-        fn _vminv_s16(a: int16x4_t) -> i16;
-    }
-    unsafe { _vminv_s16(a) }
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_s16)"]
 @@ -13933,14 +13612,7 @@ pub fn vminv_s16(a: int16x4_t) -> i16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminv))]
 pub fn vminvq_s16(a: int16x8_t) -> i16 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_min(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.sminv.i16.v8i16"
-        )]
-        fn _vminvq_s16(a: int16x8_t) -> i16;
-    }
-    unsafe { _vminvq_s16(a) }
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_s32)"]
 @@ -13949,14 +13621,7 @@ pub fn vminvq_s16(a: int16x8_t) -> i16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminp))]
 pub fn vminv_s32(a: int32x2_t) -> i32 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_min(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.sminv.i32.v2i32"
-        )]
-        fn _vminv_s32(a: int32x2_t) -> i32;
-    }
-    unsafe { _vminv_s32(a) }
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_s32)"]
 @@ -13965,14 +13630,7 @@ pub fn vminv_s32(a: int32x2_t) -> i32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(sminv))]
 pub fn vminvq_s32(a: int32x4_t) -> i32 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_min(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.sminv.i32.v4i32"
-        )]
-        fn _vminvq_s32(a: int32x4_t) -> i32;
-    }
-    unsafe { _vminvq_s32(a) }
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_u8)"]
 @@ -13981,14 +13639,7 @@ pub fn vminvq_s32(a: int32x4_t) -> i32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminv))]
 pub fn vminv_u8(a: uint8x8_t) -> u8 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_min(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.uminv.i8.v8i8"
-        )]
-        fn _vminv_u8(a: uint8x8_t) -> u8;
-    }
-    unsafe { _vminv_u8(a) }
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u8)"]
 @@ -13997,14 +13648,7 @@ pub fn vminv_u8(a: uint8x8_t) -> u8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminv))]
 pub fn vminvq_u8(a: uint8x16_t) -> u8 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_min(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.uminv.i8.v16i8"
-        )]
-        fn _vminvq_u8(a: uint8x16_t) -> u8;
-    }
-    unsafe { _vminvq_u8(a) }
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_u16)"]
 @@ -14013,14 +13657,7 @@ pub fn vminvq_u8(a: uint8x16_t) -> u8 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminv))]
 pub fn vminv_u16(a: uint16x4_t) -> u16 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_min(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.uminv.i16.v4i16"
-        )]
-        fn _vminv_u16(a: uint16x4_t) -> u16;
-    }
-    unsafe { _vminv_u16(a) }
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u16)"]
 @@ -14029,14 +13666,7 @@ pub fn vminv_u16(a: uint16x4_t) -> u16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminv))]
 pub fn vminvq_u16(a: uint16x8_t) -> u16 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_min(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.uminv.i16.v8i16"
-        )]
-        fn _vminvq_u16(a: uint16x8_t) -> u16;
-    }
-    unsafe { _vminvq_u16(a) }
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_u32)"]
 @@ -14045,14 +13675,7 @@ pub fn vminvq_u16(a: uint16x8_t) -> u16 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminp))]
 pub fn vminv_u32(a: uint32x2_t) -> u32 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_min(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.uminv.i32.v2i32"
-        )]
-        fn _vminv_u32(a: uint32x2_t) -> u32;
-    }
-    unsafe { _vminv_u32(a) }
 }
 #[doc = "Horizontal vector min."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u32)"]
 @@ -14061,14 +13684,7 @@ pub fn vminv_u32(a: uint32x2_t) -> u32 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(uminv))]
 pub fn vminvq_u32(a: uint32x4_t) -> u32 {
-    unsafe extern "unadjusted" {
+    unsafe { simd_reduce_min(a) }
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.uminv.i32.v4i32"
-        )]
-        fn _vminvq_u32(a: uint32x4_t) -> u32;
-    }
-    unsafe { _vminvq_u32(a) }
 }
 #[doc = "Floating-point multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_f64)"]
 @@ -15277,7 +14893,7 @@ pub fn vmull_high_n_u32(a: uint32x4_t, b: u32) -> uint64x2_t {
 #[inline]
 #[target_feature(enable = "neon,aes")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(pmull))]
+#[cfg_attr(test, assert_instr(pmull2))]
 pub fn vmull_high_p64(a: poly64x2_t, b: poly64x2_t) -> p128 {
     unsafe { vmull_p64(simd_extract!(a, 1), simd_extract!(b, 1)) }
 }
 @@ -15286,7 +14902,7 @@ pub fn vmull_high_p64(a: poly64x2_t, b: poly64x2_t) -> p128 {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(pmull))]
+#[cfg_attr(test, assert_instr(pmull2))]
 pub fn vmull_high_p8(a: poly8x16_t, b: poly8x16_t) -> poly16x8_t {
     unsafe {
         let a: poly8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
 @@ -15951,23 +15567,11 @@ pub fn vpadds_f32(a: float32x2_t) -> f32 {
 #[doc = "Add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddd_s64)"]
 #[inline]
-#[cfg(target_endian = "little")]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
 pub fn vpaddd_s64(a: int64x2_t) -> i64 {
-    unsafe { transmute(vaddvq_u64(transmute(a))) }
+    unsafe { simd_reduce_add_unordered(a) }
-}
-#[doc = "Add pairwise"]
-#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddd_s64)"]
-#[inline]
-#[cfg(target_endian = "big")]
-#[target_feature(enable = "neon")]
-#[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(addp))]
-pub fn vpaddd_s64(a: int64x2_t) -> i64 {
-    let a: int64x2_t = unsafe { simd_shuffle!(a, a, [1, 0]) };
-    unsafe { transmute(vaddvq_u64(transmute(a))) }
 }
 #[doc = "Add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddd_u64)"]
 @@ -15976,7 +15580,7 @@ pub fn vpaddd_s64(a: int64x2_t) -> i64 {
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
 #[cfg_attr(test, assert_instr(addp))]
 pub fn vpaddd_u64(a: uint64x2_t) -> u64 {
-    vaddvq_u64(a)
+    unsafe { simd_reduce_add_unordered(a) }
 }
 #[doc = "Floating-point add pairwise"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f16)"]
 @@ -26893,7 +26497,7 @@ pub fn vsubh_f16(a: f16, b: f16) -> f16 {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(ssubl))]
+#[cfg_attr(test, assert_instr(ssubl2))]
 pub fn vsubl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
     unsafe {
         let c: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
 @@ -26908,7 +26512,7 @@ pub fn vsubl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(ssubl))]
+#[cfg_attr(test, assert_instr(ssubl2))]
 pub fn vsubl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
     unsafe {
         let c: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
 @@ -26923,7 +26527,7 @@ pub fn vsubl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(ssubl))]
+#[cfg_attr(test, assert_instr(ssubl2))]
 pub fn vsubl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
     unsafe {
         let c: int32x2_t = simd_shuffle!(a, a, [2, 3]);
 @@ -26938,7 +26542,7 @@ pub fn vsubl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(usubl))]
+#[cfg_attr(test, assert_instr(usubl2))]
 pub fn vsubl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
     unsafe {
         let c: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]);
 @@ -26953,7 +26557,7 @@ pub fn vsubl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(usubl))]
+#[cfg_attr(test, assert_instr(usubl2))]
 pub fn vsubl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
     unsafe {
         let c: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]);
 @@ -26968,7 +26572,7 @@ pub fn vsubl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(usubl))]
+#[cfg_attr(test, assert_instr(usubl2))]
 pub fn vsubl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
     unsafe {
         let c: uint32x2_t = simd_shuffle!(a, a, [2, 3]);
 @@ -26983,7 +26587,7 @@ pub fn vsubl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(ssubw))]
+#[cfg_attr(test, assert_instr(ssubw2))]
 pub fn vsubw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
     unsafe {
         let c: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
 @@ -26995,7 +26599,7 @@ pub fn vsubw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(ssubw))]
+#[cfg_attr(test, assert_instr(ssubw2))]
 pub fn vsubw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
     unsafe {
         let c: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
 @@ -27007,7 +26611,7 @@ pub fn vsubw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(ssubw))]
+#[cfg_attr(test, assert_instr(ssubw2))]
 pub fn vsubw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
     unsafe {
         let c: int32x2_t = simd_shuffle!(b, b, [2, 3]);
 @@ -27019,7 +26623,7 @@ pub fn vsubw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(usubw))]
+#[cfg_attr(test, assert_instr(usubw2))]
 pub fn vsubw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
     unsafe {
         let c: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]);
 @@ -27031,7 +26635,7 @@ pub fn vsubw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(usubw))]
+#[cfg_attr(test, assert_instr(usubw2))]
 pub fn vsubw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
     unsafe {
         let c: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]);
 @@ -27043,7 +26647,7 @@ pub fn vsubw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t {
 #[inline]
 #[target_feature(enable = "neon")]
 #[stable(feature = "neon_intrinsics", since = "1.59.0")]
-#[cfg_attr(test, assert_instr(usubw))]
+#[cfg_attr(test, assert_instr(usubw2))]
 pub fn vsubw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t {
     unsafe {
         let c: uint32x2_t = simd_shuffle!(b, b, [2, 3]);

library/stdarch/crates/core_arch/src/arm_shared/neon/generated.rs+445-508

 @@ -1483,15 +1483,11 @@ pub fn vabsq_f32(a: float32x4_t) -> float32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vabs_s8(a: int8x8_t) -> int8x8_t {
-    unsafe extern "unadjusted" {
+    unsafe {
-        #[cfg_attr(
+        let neg: int8x8_t = simd_neg(a);
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
+        let mask: int8x8_t = simd_ge(a, neg);
-            link_name = "llvm.aarch64.neon.abs.v8i8"
+        simd_select(mask, a, neg)
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v8i8")]
-        fn _vabs_s8(a: int8x8_t) -> int8x8_t;
     }
-    unsafe { _vabs_s8(a) }
 }
 #[doc = "Absolute value (wrapping)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s8)"]
 @@ -1512,15 +1508,11 @@ pub fn vabs_s8(a: int8x8_t) -> int8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vabsq_s8(a: int8x16_t) -> int8x16_t {
-    unsafe extern "unadjusted" {
+    unsafe {
-        #[cfg_attr(
+        let neg: int8x16_t = simd_neg(a);
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
+        let mask: int8x16_t = simd_ge(a, neg);
-            link_name = "llvm.aarch64.neon.abs.v16i8"
+        simd_select(mask, a, neg)
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v16i8")]
-        fn _vabsq_s8(a: int8x16_t) -> int8x16_t;
     }
-    unsafe { _vabsq_s8(a) }
 }
 #[doc = "Absolute value (wrapping)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s16)"]
 @@ -1541,15 +1533,11 @@ pub fn vabsq_s8(a: int8x16_t) -> int8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vabs_s16(a: int16x4_t) -> int16x4_t {
-    unsafe extern "unadjusted" {
+    unsafe {
-        #[cfg_attr(
+        let neg: int16x4_t = simd_neg(a);
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
+        let mask: int16x4_t = simd_ge(a, neg);
-            link_name = "llvm.aarch64.neon.abs.v4i16"
+        simd_select(mask, a, neg)
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v4i16")]
-        fn _vabs_s16(a: int16x4_t) -> int16x4_t;
     }
-    unsafe { _vabs_s16(a) }
 }
 #[doc = "Absolute value (wrapping)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s16)"]
 @@ -1570,15 +1558,11 @@ pub fn vabs_s16(a: int16x4_t) -> int16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vabsq_s16(a: int16x8_t) -> int16x8_t {
-    unsafe extern "unadjusted" {
+    unsafe {
-        #[cfg_attr(
+        let neg: int16x8_t = simd_neg(a);
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
+        let mask: int16x8_t = simd_ge(a, neg);
-            link_name = "llvm.aarch64.neon.abs.v8i16"
+        simd_select(mask, a, neg)
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v8i16")]
-        fn _vabsq_s16(a: int16x8_t) -> int16x8_t;
     }
-    unsafe { _vabsq_s16(a) }
 }
 #[doc = "Absolute value (wrapping)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s32)"]
 @@ -1599,15 +1583,11 @@ pub fn vabsq_s16(a: int16x8_t) -> int16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vabs_s32(a: int32x2_t) -> int32x2_t {
-    unsafe extern "unadjusted" {
+    unsafe {
-        #[cfg_attr(
+        let neg: int32x2_t = simd_neg(a);
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
+        let mask: int32x2_t = simd_ge(a, neg);
-            link_name = "llvm.aarch64.neon.abs.v2i32"
+        simd_select(mask, a, neg)
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v2i32")]
-        fn _vabs_s32(a: int32x2_t) -> int32x2_t;
     }
-    unsafe { _vabs_s32(a) }
 }
 #[doc = "Absolute value (wrapping)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s32)"]
 @@ -1628,15 +1608,11 @@ pub fn vabs_s32(a: int32x2_t) -> int32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vabsq_s32(a: int32x4_t) -> int32x4_t {
-    unsafe extern "unadjusted" {
+    unsafe {
-        #[cfg_attr(
+        let neg: int32x4_t = simd_neg(a);
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
+        let mask: int32x4_t = simd_ge(a, neg);
-            link_name = "llvm.aarch64.neon.abs.v4i32"
+        simd_select(mask, a, neg)
-        )]
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabs.v4i32")]
-        fn _vabsq_s32(a: int32x4_t) -> int32x4_t;
     }
-    unsafe { _vabsq_s32(a) }
 }
 #[doc = "Floating-point absolute value"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsh_f16)"]
 @@ -14322,8 +14298,7 @@ pub unsafe fn vld1q_dup_f16(ptr: *const f16) -> float16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_dup_f32(ptr: *const f32) -> float32x2_t {
-    let x = vld1_lane_f32::<0>(ptr, transmute(f32x2::splat(0.0)));
+    transmute(f32x2::splat(*ptr))
-    simd_shuffle!(x, x, [0, 0])
 }
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p16)"]
 @@ -14346,8 +14321,7 @@ pub unsafe fn vld1_dup_f32(ptr: *const f32) -> float32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_dup_p16(ptr: *const p16) -> poly16x4_t {
-    let x = vld1_lane_p16::<0>(ptr, transmute(u16x4::splat(0)));
+    transmute(u16x4::splat(*ptr))
-    simd_shuffle!(x, x, [0, 0, 0, 0])
 }
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p8)"]
 @@ -14370,8 +14344,7 @@ pub unsafe fn vld1_dup_p16(ptr: *const p16) -> poly16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_dup_p8(ptr: *const p8) -> poly8x8_t {
-    let x = vld1_lane_p8::<0>(ptr, transmute(u8x8::splat(0)));
+    transmute(u8x8::splat(*ptr))
-    simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0])
 }
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s16)"]
 @@ -14394,8 +14367,7 @@ pub unsafe fn vld1_dup_p8(ptr: *const p8) -> poly8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_dup_s16(ptr: *const i16) -> int16x4_t {
-    let x = vld1_lane_s16::<0>(ptr, transmute(i16x4::splat(0)));
+    transmute(i16x4::splat(*ptr))
-    simd_shuffle!(x, x, [0, 0, 0, 0])
 }
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s32)"]
 @@ -14418,8 +14390,7 @@ pub unsafe fn vld1_dup_s16(ptr: *const i16) -> int16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_dup_s32(ptr: *const i32) -> int32x2_t {
-    let x = vld1_lane_s32::<0>(ptr, transmute(i32x2::splat(0)));
+    transmute(i32x2::splat(*ptr))
-    simd_shuffle!(x, x, [0, 0])
 }
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s8)"]
 @@ -14442,8 +14413,7 @@ pub unsafe fn vld1_dup_s32(ptr: *const i32) -> int32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_dup_s8(ptr: *const i8) -> int8x8_t {
-    let x = vld1_lane_s8::<0>(ptr, transmute(i8x8::splat(0)));
+    transmute(i8x8::splat(*ptr))
-    simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0])
 }
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u16)"]
 @@ -14466,8 +14436,7 @@ pub unsafe fn vld1_dup_s8(ptr: *const i8) -> int8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_dup_u16(ptr: *const u16) -> uint16x4_t {
-    let x = vld1_lane_u16::<0>(ptr, transmute(u16x4::splat(0)));
+    transmute(u16x4::splat(*ptr))
-    simd_shuffle!(x, x, [0, 0, 0, 0])
 }
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u32)"]
 @@ -14490,8 +14459,7 @@ pub unsafe fn vld1_dup_u16(ptr: *const u16) -> uint16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_dup_u32(ptr: *const u32) -> uint32x2_t {
-    let x = vld1_lane_u32::<0>(ptr, transmute(u32x2::splat(0)));
+    transmute(u32x2::splat(*ptr))
-    simd_shuffle!(x, x, [0, 0])
 }
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u8)"]
 @@ -14514,8 +14482,7 @@ pub unsafe fn vld1_dup_u32(ptr: *const u32) -> uint32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1_dup_u8(ptr: *const u8) -> uint8x8_t {
-    let x = vld1_lane_u8::<0>(ptr, transmute(u8x8::splat(0)));
+    transmute(u8x8::splat(*ptr))
-    simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0])
 }
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f32)"]
 @@ -14538,8 +14505,7 @@ pub unsafe fn vld1_dup_u8(ptr: *const u8) -> uint8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_dup_f32(ptr: *const f32) -> float32x4_t {
-    let x = vld1q_lane_f32::<0>(ptr, transmute(f32x4::splat(0.0)));
+    transmute(f32x4::splat(*ptr))
-    simd_shuffle!(x, x, [0, 0, 0, 0])
 }
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p16)"]
 @@ -14562,8 +14528,7 @@ pub unsafe fn vld1q_dup_f32(ptr: *const f32) -> float32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_dup_p16(ptr: *const p16) -> poly16x8_t {
-    let x = vld1q_lane_p16::<0>(ptr, transmute(u16x8::splat(0)));
+    transmute(u16x8::splat(*ptr))
-    simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0])
 }
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_p8)"]
 @@ -14586,8 +14551,7 @@ pub unsafe fn vld1q_dup_p16(ptr: *const p16) -> poly16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_dup_p8(ptr: *const p8) -> poly8x16_t {
-    let x = vld1q_lane_p8::<0>(ptr, transmute(u8x16::splat(0)));
+    transmute(u8x16::splat(*ptr))
-    simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0])
 }
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s16)"]
 @@ -14610,8 +14574,7 @@ pub unsafe fn vld1q_dup_p8(ptr: *const p8) -> poly8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_dup_s16(ptr: *const i16) -> int16x8_t {
-    let x = vld1q_lane_s16::<0>(ptr, transmute(i16x8::splat(0)));
+    transmute(i16x8::splat(*ptr))
-    simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0])
 }
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s32)"]
 @@ -14634,8 +14597,7 @@ pub unsafe fn vld1q_dup_s16(ptr: *const i16) -> int16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_dup_s32(ptr: *const i32) -> int32x4_t {
-    let x = vld1q_lane_s32::<0>(ptr, transmute(i32x4::splat(0)));
+    transmute(i32x4::splat(*ptr))
-    simd_shuffle!(x, x, [0, 0, 0, 0])
 }
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s64)"]
 @@ -14647,7 +14609,7 @@ pub unsafe fn vld1q_dup_s32(ptr: *const i32) -> int32x4_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vldr"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld1r)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -14658,8 +14620,7 @@ pub unsafe fn vld1q_dup_s32(ptr: *const i32) -> int32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_dup_s64(ptr: *const i64) -> int64x2_t {
-    let x = vld1q_lane_s64::<0>(ptr, transmute(i64x2::splat(0)));
+    transmute(i64x2::splat(*ptr))
-    simd_shuffle!(x, x, [0, 0])
 }
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s8)"]
 @@ -14682,8 +14643,7 @@ pub unsafe fn vld1q_dup_s64(ptr: *const i64) -> int64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_dup_s8(ptr: *const i8) -> int8x16_t {
-    let x = vld1q_lane_s8::<0>(ptr, transmute(i8x16::splat(0)));
+    transmute(i8x16::splat(*ptr))
-    simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0])
 }
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u16)"]
 @@ -14706,8 +14666,7 @@ pub unsafe fn vld1q_dup_s8(ptr: *const i8) -> int8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_dup_u16(ptr: *const u16) -> uint16x8_t {
-    let x = vld1q_lane_u16::<0>(ptr, transmute(u16x8::splat(0)));
+    transmute(u16x8::splat(*ptr))
-    simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0])
 }
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u32)"]
 @@ -14730,8 +14689,7 @@ pub unsafe fn vld1q_dup_u16(ptr: *const u16) -> uint16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_dup_u32(ptr: *const u32) -> uint32x4_t {
-    let x = vld1q_lane_u32::<0>(ptr, transmute(u32x4::splat(0)));
+    transmute(u32x4::splat(*ptr))
-    simd_shuffle!(x, x, [0, 0, 0, 0])
 }
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u64)"]
 @@ -14743,7 +14701,7 @@ pub unsafe fn vld1q_dup_u32(ptr: *const u32) -> uint32x4_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vldr"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(ld1)
+    assert_instr(ld1r)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -14754,8 +14712,7 @@ pub unsafe fn vld1q_dup_u32(ptr: *const u32) -> uint32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_dup_u64(ptr: *const u64) -> uint64x2_t {
-    let x = vld1q_lane_u64::<0>(ptr, transmute(u64x2::splat(0)));
+    transmute(u64x2::splat(*ptr))
-    simd_shuffle!(x, x, [0, 0])
 }
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u8)"]
 @@ -14778,8 +14735,7 @@ pub unsafe fn vld1q_dup_u64(ptr: *const u64) -> uint64x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub unsafe fn vld1q_dup_u8(ptr: *const u8) -> uint8x16_t {
-    let x = vld1q_lane_u8::<0>(ptr, transmute(u8x16::splat(0)));
+    transmute(u8x16::splat(*ptr))
-    simd_shuffle!(x, x, [0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0])
 }
 #[doc = "Load one single-element structure and Replicate to all lanes (of one register)."]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_p64)"]
 @@ -27681,15 +27637,10 @@ pub fn vmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
-    unsafe extern "unadjusted" {
+    unsafe {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v8i8")]
+        let mask: int8x8_t = simd_ge(a, b);
-        #[cfg_attr(
+        simd_select(mask, a, b)
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.smax.v8i8"
-        )]
-        fn _vmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
     }
-    unsafe { _vmax_s8(a, b) }
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s8)"]
 @@ -27710,15 +27661,10 @@ pub fn vmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
-    unsafe extern "unadjusted" {
+    unsafe {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v16i8")]
+        let mask: int8x16_t = simd_ge(a, b);
-        #[cfg_attr(
+        simd_select(mask, a, b)
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.smax.v16i8"
-        )]
-        fn _vmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
     }
-    unsafe { _vmaxq_s8(a, b) }
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s16)"]
 @@ -27739,15 +27685,10 @@ pub fn vmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
-    unsafe extern "unadjusted" {
+    unsafe {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4i16")]
+        let mask: int16x4_t = simd_ge(a, b);
-        #[cfg_attr(
+        simd_select(mask, a, b)
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.smax.v4i16"
-        )]
-        fn _vmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
     }
-    unsafe { _vmax_s16(a, b) }
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s16)"]
 @@ -27768,15 +27709,10 @@ pub fn vmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
-    unsafe extern "unadjusted" {
+    unsafe {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v8i16")]
+        let mask: int16x8_t = simd_ge(a, b);
-        #[cfg_attr(
+        simd_select(mask, a, b)
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.smax.v8i16"
-        )]
-        fn _vmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
     }
-    unsafe { _vmaxq_s16(a, b) }
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s32)"]
 @@ -27797,15 +27733,10 @@ pub fn vmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
-    unsafe extern "unadjusted" {
+    unsafe {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v2i32")]
+        let mask: int32x2_t = simd_ge(a, b);
-        #[cfg_attr(
+        simd_select(mask, a, b)
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.smax.v2i32"
-        )]
-        fn _vmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
     }
-    unsafe { _vmax_s32(a, b) }
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s32)"]
 @@ -27826,15 +27757,10 @@ pub fn vmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
-    unsafe extern "unadjusted" {
+    unsafe {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4i32")]
+        let mask: int32x4_t = simd_ge(a, b);
-        #[cfg_attr(
+        simd_select(mask, a, b)
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.smax.v4i32"
-        )]
-        fn _vmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
     }
-    unsafe { _vmaxq_s32(a, b) }
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u8)"]
 @@ -27855,15 +27781,10 @@ pub fn vmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
-    unsafe extern "unadjusted" {
+    unsafe {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v8i8")]
+        let mask: uint8x8_t = simd_ge(a, b);
-        #[cfg_attr(
+        simd_select(mask, a, b)
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.umax.v8i8"
-        )]
-        fn _vmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
     }
-    unsafe { _vmax_u8(a, b) }
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u8)"]
 @@ -27884,15 +27805,10 @@ pub fn vmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
-    unsafe extern "unadjusted" {
+    unsafe {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v16i8")]
+        let mask: uint8x16_t = simd_ge(a, b);
-        #[cfg_attr(
+        simd_select(mask, a, b)
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.umax.v16i8"
-        )]
-        fn _vmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
     }
-    unsafe { _vmaxq_u8(a, b) }
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u16)"]
 @@ -27913,15 +27829,10 @@ pub fn vmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
-    unsafe extern "unadjusted" {
+    unsafe {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v4i16")]
+        let mask: uint16x4_t = simd_ge(a, b);
-        #[cfg_attr(
+        simd_select(mask, a, b)
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.umax.v4i16"
-        )]
-        fn _vmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
     }
-    unsafe { _vmax_u16(a, b) }
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u16)"]
 @@ -27942,15 +27853,10 @@ pub fn vmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
-    unsafe extern "unadjusted" {
+    unsafe {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v8i16")]
+        let mask: uint16x8_t = simd_ge(a, b);
-        #[cfg_attr(
+        simd_select(mask, a, b)
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.umax.v8i16"
-        )]
-        fn _vmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
     }
-    unsafe { _vmaxq_u16(a, b) }
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u32)"]
 @@ -27971,15 +27877,10 @@ pub fn vmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
-    unsafe extern "unadjusted" {
+    unsafe {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v2i32")]
+        let mask: uint32x2_t = simd_ge(a, b);
-        #[cfg_attr(
+        simd_select(mask, a, b)
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.umax.v2i32"
-        )]
-        fn _vmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
     }
-    unsafe { _vmax_u32(a, b) }
 }
 #[doc = "Maximum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u32)"]
 @@ -28000,15 +27901,10 @@ pub fn vmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
-    unsafe extern "unadjusted" {
+    unsafe {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v4i32")]
+        let mask: uint32x4_t = simd_ge(a, b);
-        #[cfg_attr(
+        simd_select(mask, a, b)
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.umax.v4i32"
-        )]
-        fn _vmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
     }
-    unsafe { _vmaxq_u32(a, b) }
 }
 #[doc = "Floating-point Maximum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f16)"]
 @@ -28022,15 +27918,7 @@ pub fn vmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 pub fn vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
-    unsafe extern "unadjusted" {
+    unsafe { simd_fmax(a, b) }
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v4f16")]
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.fmaxnm.v4f16"
-        )]
-        fn _vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
-    }
-    unsafe { _vmaxnm_f16(a, b) }
 }
 #[doc = "Floating-point Maximum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f16)"]
 @@ -28044,15 +27932,7 @@ pub fn vmaxnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 pub fn vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
-    unsafe extern "unadjusted" {
+    unsafe { simd_fmax(a, b) }
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v8f16")]
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.fmaxnm.v8f16"
-        )]
-        fn _vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
-    }
-    unsafe { _vmaxnmq_f16(a, b) }
 }
 #[doc = "Floating-point Maximum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f32)"]
 @@ -28073,15 +27953,7 @@ pub fn vmaxnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
-    unsafe extern "unadjusted" {
+    unsafe { simd_fmax(a, b) }
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v2f32")]
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.fmaxnm.v2f32"
-        )]
-        fn _vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
-    }
-    unsafe { _vmaxnm_f32(a, b) }
 }
 #[doc = "Floating-point Maximum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f32)"]
 @@ -28102,15 +27974,7 @@ pub fn vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
-    unsafe extern "unadjusted" {
+    unsafe { simd_fmax(a, b) }
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v4f32")]
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.fmaxnm.v4f32"
-        )]
-        fn _vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
-    }
-    unsafe { _vmaxnmq_f32(a, b) }
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f16)"]
 @@ -28233,15 +28097,10 @@ pub fn vminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
-    unsafe extern "unadjusted" {
+    unsafe {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v8i8")]
+        let mask: int8x8_t = simd_le(a, b);
-        #[cfg_attr(
+        simd_select(mask, a, b)
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.smin.v8i8"
-        )]
-        fn _vmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t;
     }
-    unsafe { _vmin_s8(a, b) }
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s8)"]
 @@ -28262,15 +28121,10 @@ pub fn vmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
-    unsafe extern "unadjusted" {
+    unsafe {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v16i8")]
+        let mask: int8x16_t = simd_le(a, b);
-        #[cfg_attr(
+        simd_select(mask, a, b)
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.smin.v16i8"
-        )]
-        fn _vminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t;
     }
-    unsafe { _vminq_s8(a, b) }
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s16)"]
 @@ -28291,15 +28145,10 @@ pub fn vminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
-    unsafe extern "unadjusted" {
+    unsafe {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4i16")]
+        let mask: int16x4_t = simd_le(a, b);
-        #[cfg_attr(
+        simd_select(mask, a, b)
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.smin.v4i16"
-        )]
-        fn _vmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t;
     }
-    unsafe { _vmin_s16(a, b) }
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s16)"]
 @@ -28320,15 +28169,10 @@ pub fn vmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
-    unsafe extern "unadjusted" {
+    unsafe {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v8i16")]
+        let mask: int16x8_t = simd_le(a, b);
-        #[cfg_attr(
+        simd_select(mask, a, b)
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.smin.v8i16"
-        )]
-        fn _vminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t;
     }
-    unsafe { _vminq_s16(a, b) }
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s32)"]
 @@ -28349,15 +28193,10 @@ pub fn vminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
-    unsafe extern "unadjusted" {
+    unsafe {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v2i32")]
+        let mask: int32x2_t = simd_le(a, b);
-        #[cfg_attr(
+        simd_select(mask, a, b)
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.smin.v2i32"
-        )]
-        fn _vmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t;
     }
-    unsafe { _vmin_s32(a, b) }
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s32)"]
 @@ -28378,15 +28217,10 @@ pub fn vmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
-    unsafe extern "unadjusted" {
+    unsafe {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4i32")]
+        let mask: int32x4_t = simd_le(a, b);
-        #[cfg_attr(
+        simd_select(mask, a, b)
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.smin.v4i32"
-        )]
-        fn _vminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t;
     }
-    unsafe { _vminq_s32(a, b) }
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u8)"]
 @@ -28407,15 +28241,10 @@ pub fn vminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
-    unsafe extern "unadjusted" {
+    unsafe {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v8i8")]
+        let mask: uint8x8_t = simd_le(a, b);
-        #[cfg_attr(
+        simd_select(mask, a, b)
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.umin.v8i8"
-        )]
-        fn _vmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t;
     }
-    unsafe { _vmin_u8(a, b) }
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u8)"]
 @@ -28436,15 +28265,10 @@ pub fn vmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
-    unsafe extern "unadjusted" {
+    unsafe {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v16i8")]
+        let mask: uint8x16_t = simd_le(a, b);
-        #[cfg_attr(
+        simd_select(mask, a, b)
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.umin.v16i8"
-        )]
-        fn _vminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t;
     }
-    unsafe { _vminq_u8(a, b) }
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u16)"]
 @@ -28465,15 +28289,10 @@ pub fn vminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
-    unsafe extern "unadjusted" {
+    unsafe {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v4i16")]
+        let mask: uint16x4_t = simd_le(a, b);
-        #[cfg_attr(
+        simd_select(mask, a, b)
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.umin.v4i16"
-        )]
-        fn _vmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t;
     }
-    unsafe { _vmin_u16(a, b) }
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u16)"]
 @@ -28494,15 +28313,10 @@ pub fn vmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
-    unsafe extern "unadjusted" {
+    unsafe {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v8i16")]
+        let mask: uint16x8_t = simd_le(a, b);
-        #[cfg_attr(
+        simd_select(mask, a, b)
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.umin.v8i16"
-        )]
-        fn _vminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t;
     }
-    unsafe { _vminq_u16(a, b) }
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u32)"]
 @@ -28523,15 +28337,10 @@ pub fn vminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
-    unsafe extern "unadjusted" {
+    unsafe {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v2i32")]
+        let mask: uint32x2_t = simd_le(a, b);
-        #[cfg_attr(
+        simd_select(mask, a, b)
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.umin.v2i32"
-        )]
-        fn _vmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t;
     }
-    unsafe { _vmin_u32(a, b) }
 }
 #[doc = "Minimum (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u32)"]
 @@ -28552,15 +28361,10 @@ pub fn vmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
-    unsafe extern "unadjusted" {
+    unsafe {
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v4i32")]
+        let mask: uint32x4_t = simd_le(a, b);
-        #[cfg_attr(
+        simd_select(mask, a, b)
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.umin.v4i32"
-        )]
-        fn _vminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t;
     }
-    unsafe { _vminq_u32(a, b) }
 }
 #[doc = "Floating-point Minimum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f16)"]
 @@ -28574,15 +28378,7 @@ pub fn vminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 pub fn vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
-    unsafe extern "unadjusted" {
+    unsafe { simd_fmin(a, b) }
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v4f16")]
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.fminnm.v4f16"
-        )]
-        fn _vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t;
-    }
-    unsafe { _vminnm_f16(a, b) }
 }
 #[doc = "Floating-point Minimum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f16)"]
 @@ -28596,15 +28392,7 @@ pub fn vminnm_f16(a: float16x4_t, b: float16x4_t) -> float16x4_t {
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 pub fn vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
-    unsafe extern "unadjusted" {
+    unsafe { simd_fmin(a, b) }
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v8f16")]
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.fminnm.v8f16"
-        )]
-        fn _vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t;
-    }
-    unsafe { _vminnmq_f16(a, b) }
 }
 #[doc = "Floating-point Minimum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f32)"]
 @@ -28625,15 +28413,7 @@ pub fn vminnmq_f16(a: float16x8_t, b: float16x8_t) -> float16x8_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
-    unsafe extern "unadjusted" {
+    unsafe { simd_fmin(a, b) }
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v2f32")]
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.fminnm.v2f32"
-        )]
-        fn _vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t;
-    }
-    unsafe { _vminnm_f32(a, b) }
 }
 #[doc = "Floating-point Minimum Number (vector)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f32)"]
 @@ -28654,15 +28434,7 @@ pub fn vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t {
     unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")
 )]
 pub fn vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t {
-    unsafe extern "unadjusted" {
+    unsafe { simd_fmin(a, b) }
-        #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v4f32")]
-        #[cfg_attr(
-            any(target_arch = "aarch64", target_arch = "arm64ec"),
-            link_name = "llvm.aarch64.neon.fminnm.v4f32"
-        )]
-        fn _vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t;
-    }
-    unsafe { _vminnmq_f32(a, b) }
 }
 #[doc = "Floating-point multiply-add to accumulator"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_f32)"]
 @@ -39566,17 +39338,7 @@ pub fn vqrshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftns.v8i8")]
         fn _vqrshrn_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t;
     }
-    unsafe {
+    unsafe { _vqrshrn_n_s16(a, const { int16x8_t([-N as i16; 8]) }) }
-        _vqrshrn_n_s16(
-            a,
-            const {
-                int16x8_t([
-                    -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16,
-                    -N as i16,
-                ])
-            },
-        )
-    }
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s32)"]
 @@ -39592,12 +39354,7 @@ pub fn vqrshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftns.v4i16")]
         fn _vqrshrn_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t;
     }
-    unsafe {
+    unsafe { _vqrshrn_n_s32(a, const { int32x4_t([-N; 4]) }) }
-        _vqrshrn_n_s32(
-            a,
-            const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) },
-        )
-    }
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s64)"]
 @@ -39613,7 +39370,7 @@ pub fn vqrshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftns.v2i32")]
         fn _vqrshrn_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t;
     }
-    unsafe { _vqrshrn_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) }
+    unsafe { _vqrshrn_n_s64(a, const { int64x2_t([-N as i64; 2]) }) }
 }
 #[doc = "Signed saturating rounded shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s16)"]
 @@ -39806,17 +39563,7 @@ pub fn vqrshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v8i8")]
         fn _vqrshrun_n_s16(a: int16x8_t, n: int16x8_t) -> uint8x8_t;
     }
-    unsafe {
+    unsafe { _vqrshrun_n_s16(a, const { int16x8_t([-N as i16; 8]) }) }
-        _vqrshrun_n_s16(
-            a,
-            const {
-                int16x8_t([
-                    -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16,
-                    -N as i16,
-                ])
-            },
-        )
-    }
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s32)"]
 @@ -39832,12 +39579,7 @@ pub fn vqrshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v4i16")]
         fn _vqrshrun_n_s32(a: int32x4_t, n: int32x4_t) -> uint16x4_t;
     }
-    unsafe {
+    unsafe { _vqrshrun_n_s32(a, const { int32x4_t([-N; 4]) }) }
-        _vqrshrun_n_s32(
-            a,
-            const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) },
-        )
-    }
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s64)"]
 @@ -39853,7 +39595,7 @@ pub fn vqrshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v2i32")]
         fn _vqrshrun_n_s64(a: int64x2_t, n: int64x2_t) -> uint32x2_t;
     }
-    unsafe { _vqrshrun_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) }
+    unsafe { _vqrshrun_n_s64(a, const { int64x2_t([-N as i64; 2]) }) }
 }
 #[doc = "Signed saturating rounded shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s16)"]
 @@ -41038,17 +40780,7 @@ pub fn vqshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftns.v8i8")]
         fn _vqshrn_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t;
     }
-    unsafe {
+    unsafe { _vqshrn_n_s16(a, const { int16x8_t([-N as i16; 8]) }) }
-        _vqshrn_n_s16(
-            a,
-            const {
-                int16x8_t([
-                    -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16,
-                    -N as i16,
-                ])
-            },
-        )
-    }
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s32)"]
 @@ -41064,12 +40796,7 @@ pub fn vqshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftns.v4i16")]
         fn _vqshrn_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t;
     }
-    unsafe {
+    unsafe { _vqshrn_n_s32(a, const { int32x4_t([-N; 4]) }) }
-        _vqshrn_n_s32(
-            a,
-            const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) },
-        )
-    }
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s64)"]
 @@ -41085,7 +40812,7 @@ pub fn vqshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftns.v2i32")]
         fn _vqshrn_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t;
     }
-    unsafe { _vqshrn_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) }
+    unsafe { _vqshrn_n_s64(a, const { int64x2_t([-N as i64; 2]) }) }
 }
 #[doc = "Signed saturating shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s16)"]
 @@ -41278,17 +41005,7 @@ pub fn vqshrun_n_s16<const N: i32>(a: int16x8_t) -> uint8x8_t {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v8i8")]
         fn _vqshrun_n_s16(a: int16x8_t, n: int16x8_t) -> uint8x8_t;
     }
-    unsafe {
+    unsafe { _vqshrun_n_s16(a, const { int16x8_t([-N as i16; 8]) }) }
-        _vqshrun_n_s16(
-            a,
-            const {
-                int16x8_t([
-                    -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16,
-                    -N as i16,
-                ])
-            },
-        )
-    }
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s32)"]
 @@ -41304,12 +41021,7 @@ pub fn vqshrun_n_s32<const N: i32>(a: int32x4_t) -> uint16x4_t {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v4i16")]
         fn _vqshrun_n_s32(a: int32x4_t, n: int32x4_t) -> uint16x4_t;
     }
-    unsafe {
+    unsafe { _vqshrun_n_s32(a, const { int32x4_t([-N; 4]) }) }
-        _vqshrun_n_s32(
-            a,
-            const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) },
-        )
-    }
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s64)"]
 @@ -41325,7 +41037,7 @@ pub fn vqshrun_n_s64<const N: i32>(a: int64x2_t) -> uint32x2_t {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v2i32")]
         fn _vqshrun_n_s64(a: int64x2_t, n: int64x2_t) -> uint32x2_t;
     }
-    unsafe { _vqshrun_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) }
+    unsafe { _vqshrun_n_s64(a, const { int64x2_t([-N as i64; 2]) }) }
 }
 #[doc = "Signed saturating shift right unsigned narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s16)"]
 @@ -59483,17 +59195,7 @@ pub fn vrshrn_n_s16<const N: i32>(a: int16x8_t) -> int8x8_t {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftn.v8i8")]
         fn _vrshrn_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t;
     }
-    unsafe {
+    unsafe { _vrshrn_n_s16(a, const { int16x8_t([-N as i16; 8]) }) }
-        _vrshrn_n_s16(
-            a,
-            const {
-                int16x8_t([
-                    -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16,
-                    -N as i16,
-                ])
-            },
-        )
-    }
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s32)"]
 @@ -59509,12 +59211,7 @@ pub fn vrshrn_n_s32<const N: i32>(a: int32x4_t) -> int16x4_t {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftn.v4i16")]
         fn _vrshrn_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t;
     }
-    unsafe {
+    unsafe { _vrshrn_n_s32(a, const { int32x4_t([-N; 4]) }) }
-        _vrshrn_n_s32(
-            a,
-            const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) },
-        )
-    }
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s64)"]
 @@ -59530,7 +59227,7 @@ pub fn vrshrn_n_s64<const N: i32>(a: int64x2_t) -> int32x2_t {
         #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftn.v2i32")]
         fn _vrshrn_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t;
     }
-    unsafe { _vrshrn_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) }
+    unsafe { _vrshrn_n_s64(a, const { int64x2_t([-N as i64; 2]) }) }
 }
 #[doc = "Rounding shift right narrow"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s16)"]
 @@ -63183,7 +62880,7 @@ pub fn vsli_n_u32<const N: i32>(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t {
         transmute(vshiftins_v2i32(
             transmute(a),
             transmute(b),
-            int32x2_t::splat(N as i32),
+            int32x2_t::splat(N),
         ))
     }
 }
 @@ -63201,7 +62898,7 @@ pub fn vsliq_n_u32<const N: i32>(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t {
         transmute(vshiftins_v4i32(
             transmute(a),
             transmute(b),
-            int32x4_t::splat(N as i32),
+            int32x4_t::splat(N),
         ))
     }
 }
 @@ -63739,7 +63436,7 @@ pub fn vsriq_n_s16<const N: i32>(a: int16x8_t, b: int16x8_t) -> int16x8_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsri_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
     static_assert!(1 <= N && N <= 32);
-    vshiftins_v2i32(a, b, int32x2_t::splat(-N as i32))
+    vshiftins_v2i32(a, b, int32x2_t::splat(-N))
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s32)"]
 @@ -63751,7 +63448,7 @@ pub fn vsri_n_s32<const N: i32>(a: int32x2_t, b: int32x2_t) -> int32x2_t {
 #[rustc_legacy_const_generics(2)]
 pub fn vsriq_n_s32<const N: i32>(a: int32x4_t, b: int32x4_t) -> int32x4_t {
     static_assert!(1 <= N && N <= 32);
-    vshiftins_v4i32(a, b, int32x4_t::splat(-N as i32))
+    vshiftins_v4i32(a, b, int32x4_t::splat(-N))
 }
 #[doc = "Shift Right and Insert (immediate)"]
 #[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s64)"]
 @@ -73297,7 +72994,11 @@ pub fn vtbx4_p8(a: poly8x8_t, b: poly8x8x4_t, c: uint8x8_t) -> poly8x8_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(trn)
+    assert_instr(trn1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(trn2)
 )]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 @@ -73315,7 +73016,11 @@ pub fn vtrn_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(trn)
+    assert_instr(trn1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(trn2)
 )]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 @@ -73334,7 +73039,11 @@ pub fn vtrnq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(zip)
+    assert_instr(zip1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(zip2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -73359,7 +73068,11 @@ pub fn vtrn_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(zip)
+    assert_instr(zip1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(zip2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -73384,7 +73097,11 @@ pub fn vtrn_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(zip)
+    assert_instr(zip1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(zip2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -73409,7 +73126,11 @@ pub fn vtrn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(trn)
+    assert_instr(trn1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(trn2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -73434,7 +73155,11 @@ pub fn vtrnq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(trn)
+    assert_instr(trn1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(trn2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -73459,7 +73184,11 @@ pub fn vtrn_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(trn)
+    assert_instr(trn1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(trn2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -73492,7 +73221,11 @@ pub fn vtrnq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(trn)
+    assert_instr(trn1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(trn2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -73517,7 +73250,11 @@ pub fn vtrn_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(trn)
+    assert_instr(trn1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(trn2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -73542,7 +73279,11 @@ pub fn vtrnq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(trn)
+    assert_instr(trn1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(trn2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -73567,7 +73308,11 @@ pub fn vtrnq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(trn)
+    assert_instr(trn1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(trn2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -73592,7 +73337,11 @@ pub fn vtrn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(trn)
+    assert_instr(trn1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(trn2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -73625,7 +73374,11 @@ pub fn vtrnq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(trn)
+    assert_instr(trn1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(trn2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -73650,7 +73403,11 @@ pub fn vtrn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(trn)
+    assert_instr(trn1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(trn2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -73675,7 +73432,11 @@ pub fn vtrnq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(trn)
+    assert_instr(trn1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(trn2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -73700,7 +73461,11 @@ pub fn vtrnq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(trn)
+    assert_instr(trn1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(trn2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -73725,7 +73490,11 @@ pub fn vtrn_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(trn)
+    assert_instr(trn1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(trn2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -73758,7 +73527,11 @@ pub fn vtrnq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(trn)
+    assert_instr(trn1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(trn2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -73783,7 +73556,11 @@ pub fn vtrn_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(trn)
+    assert_instr(trn1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(trn2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -74349,7 +74126,11 @@ pub fn vusmmlaq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(uzp)
+    assert_instr(uzp1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(uzp2)
 )]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 @@ -74367,7 +74148,11 @@ pub fn vuzp_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(uzp)
+    assert_instr(uzp1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(uzp2)
 )]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 @@ -74386,7 +74171,11 @@ pub fn vuzpq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(zip)
+    assert_instr(zip1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(zip2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -74411,7 +74200,11 @@ pub fn vuzp_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(zip)
+    assert_instr(zip1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(zip2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -74436,7 +74229,11 @@ pub fn vuzp_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(zip)
+    assert_instr(zip1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(zip2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -74461,7 +74258,11 @@ pub fn vuzp_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(uzp)
+    assert_instr(uzp1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(uzp2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -74486,7 +74287,11 @@ pub fn vuzpq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(uzp)
+    assert_instr(uzp1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(uzp2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -74511,7 +74316,11 @@ pub fn vuzp_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(uzp)
+    assert_instr(uzp1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(uzp2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -74544,7 +74353,11 @@ pub fn vuzpq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(uzp)
+    assert_instr(uzp1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(uzp2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -74569,7 +74382,11 @@ pub fn vuzp_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(uzp)
+    assert_instr(uzp1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(uzp2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -74594,7 +74411,11 @@ pub fn vuzpq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(uzp)
+    assert_instr(uzp1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(uzp2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -74619,7 +74440,11 @@ pub fn vuzpq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(uzp)
+    assert_instr(uzp1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(uzp2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -74644,7 +74469,11 @@ pub fn vuzp_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(uzp)
+    assert_instr(uzp1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(uzp2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -74677,7 +74506,11 @@ pub fn vuzpq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(uzp)
+    assert_instr(uzp1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(uzp2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -74702,7 +74535,11 @@ pub fn vuzp_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(uzp)
+    assert_instr(uzp1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(uzp2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -74727,7 +74564,11 @@ pub fn vuzpq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(uzp)
+    assert_instr(uzp1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(uzp2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -74752,7 +74593,11 @@ pub fn vuzpq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(uzp)
+    assert_instr(uzp1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(uzp2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -74777,7 +74622,11 @@ pub fn vuzp_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(uzp)
+    assert_instr(uzp1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(uzp2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -74810,7 +74659,11 @@ pub fn vuzpq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(uzp)
+    assert_instr(uzp1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(uzp2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -74835,7 +74688,11 @@ pub fn vuzp_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(uzp)
+    assert_instr(uzp1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(uzp2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -74859,7 +74716,11 @@ pub fn vuzpq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vzip.16"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(zip)
+    assert_instr(zip1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(zip2)
 )]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 @@ -74877,7 +74738,11 @@ pub fn vzip_f16(a: float16x4_t, b: float16x4_t) -> float16x4x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vzip.16"))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(zip)
+    assert_instr(zip1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(zip2)
 )]
 #[target_feature(enable = "neon,fp16")]
 #[unstable(feature = "stdarch_neon_f16", issue = "136306")]
 @@ -74896,7 +74761,11 @@ pub fn vzipq_f16(a: float16x8_t, b: float16x8_t) -> float16x8x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(zip)
+    assert_instr(zip1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(zip2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -74921,7 +74790,11 @@ pub fn vzip_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(zip)
+    assert_instr(zip1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(zip2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -74946,7 +74819,11 @@ pub fn vzip_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(zip)
+    assert_instr(zip1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(zip2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -74971,7 +74848,11 @@ pub fn vzip_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(zip)
+    assert_instr(zip1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(zip2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -74996,7 +74877,11 @@ pub fn vzip_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(zip)
+    assert_instr(zip1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(zip2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -75021,7 +74906,11 @@ pub fn vzip_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(zip)
+    assert_instr(zip1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(zip2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -75046,7 +74935,11 @@ pub fn vzip_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(zip)
+    assert_instr(zip1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(zip2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -75071,7 +74964,11 @@ pub fn vzip_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(zip)
+    assert_instr(zip1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(zip2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -75096,7 +74993,11 @@ pub fn vzip_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(zip)
+    assert_instr(zip1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(zip2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -75121,7 +75022,11 @@ pub fn vzip_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(zip)
+    assert_instr(zip1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(zip2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -75146,7 +75051,11 @@ pub fn vzipq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(zip)
+    assert_instr(zip1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(zip2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -75179,7 +75088,11 @@ pub fn vzipq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(zip)
+    assert_instr(zip1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(zip2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -75204,7 +75117,11 @@ pub fn vzipq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(zip)
+    assert_instr(zip1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(zip2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -75229,7 +75146,11 @@ pub fn vzipq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(zip)
+    assert_instr(zip1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(zip2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -75262,7 +75183,11 @@ pub fn vzipq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(zip)
+    assert_instr(zip1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(zip2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -75287,7 +75212,11 @@ pub fn vzipq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(zip)
+    assert_instr(zip1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(zip2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -75312,7 +75241,11 @@ pub fn vzipq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(zip)
+    assert_instr(zip1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(zip2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),
 @@ -75345,7 +75278,11 @@ pub fn vzipq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t {
 #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))]
 #[cfg_attr(
     all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
-    assert_instr(zip)
+    assert_instr(zip1)
+)]
+#[cfg_attr(
+    all(test, any(target_arch = "aarch64", target_arch = "arm64ec")),
+    assert_instr(zip2)
 )]
 #[cfg_attr(
     not(target_arch = "arm"),

library/stdarch/crates/core_arch/src/core_arch_docs.md+2

...	@@ -193,6 +193,7 @@ others at:	...	@@ -193,6 +193,7 @@ others at:
193	* [`powerpc64`]	193	* [`powerpc64`]
194	* [`nvptx`]	194	* [`nvptx`]
195	* [`wasm32`]	195	* [`wasm32`]
		196	* [`loongarch32`]
196	* [`loongarch64`]	197	* [`loongarch64`]
197	* [`s390x`]	198	* [`s390x`]
198		199
...	@@ -208,6 +209,7 @@ others at:	...	@@ -208,6 +209,7 @@ others at:
208	[`powerpc64`]: ../../core/arch/powerpc64/index.html	209	[`powerpc64`]: ../../core/arch/powerpc64/index.html
209	[`nvptx`]: ../../core/arch/nvptx/index.html	210	[`nvptx`]: ../../core/arch/nvptx/index.html
210	[`wasm32`]: ../../core/arch/wasm32/index.html	211	[`wasm32`]: ../../core/arch/wasm32/index.html
		212	[`loongarch32`]: ../../core/arch/loongarch32/index.html
211	[`loongarch64`]: ../../core/arch/loongarch64/index.html	213	[`loongarch64`]: ../../core/arch/loongarch64/index.html
212	[`s390x`]: ../../core/arch/s390x/index.html	214	[`s390x`]: ../../core/arch/s390x/index.html
213		215

library/stdarch/crates/core_arch/src/loongarch32/mod.rs created+47

...	@@ -0,0 +1,47 @@
1	//! `LoongArch32` intrinsics
2
3	use crate::arch::asm;
4
5	#[allow(improper_ctypes)]
6	unsafe extern "unadjusted" {
7	#[link_name = "llvm.loongarch.cacop.w"]
8	fn __cacop(a: i32, b: i32, c: i32);
9	#[link_name = "llvm.loongarch.csrrd.w"]
10	fn __csrrd(a: i32) -> i32;
11	#[link_name = "llvm.loongarch.csrwr.w"]
12	fn __csrwr(a: i32, b: i32) -> i32;
13	#[link_name = "llvm.loongarch.csrxchg.w"]
14	fn __csrxchg(a: i32, b: i32, c: i32) -> i32;
15	}
16
17	/// Generates the cache operation instruction
18	#[inline]
19	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
20	pub unsafe fn cacop<const IMM12: i32>(a: i32, b: i32) {
21	static_assert_simm_bits!(IMM12, 12);
22	__cacop(a, b, IMM12);
23	}
24
25	/// Reads the CSR
26	#[inline]
27	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
28	pub unsafe fn csrrd<const IMM14: i32>() -> i32 {
29	static_assert_uimm_bits!(IMM14, 14);
30	__csrrd(IMM14)
31	}
32
33	/// Writes the CSR
34	#[inline]
35	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
36	pub unsafe fn csrwr<const IMM14: i32>(a: i32) -> i32 {
37	static_assert_uimm_bits!(IMM14, 14);
38	__csrwr(a, IMM14)
39	}
40
41	/// Exchanges the CSR
42	#[inline]
43	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
44	pub unsafe fn csrxchg<const IMM14: i32>(a: i32, b: i32) -> i32 {
45	static_assert_uimm_bits!(IMM14, 14);
46	__csrxchg(a, b, IMM14)
47	}

library/stdarch/crates/core_arch/src/loongarch64/lasx/generated.rs+1456-1456

library/stdarch/crates/core_arch/src/loongarch64/lsx/generated.rs+1416-1416

library/stdarch/crates/core_arch/src/loongarch64/mod.rs+8-246

...	@@ -1,4 +1,4 @@	...	@@ -1,4 +1,4 @@
1	//! `LoongArch` intrinsics	1	//! `LoongArch64` intrinsics
2		2
3	mod lasx;	3	mod lasx;
4	mod lsx;	4	mod lsx;
...	@@ -13,89 +13,30 @@ use crate::arch::asm;	...	@@ -13,89 +13,30 @@ use crate::arch::asm;
13	/// Reads the 64-bit stable counter value and the counter ID	13	/// Reads the 64-bit stable counter value and the counter ID
14	#[inline]	14	#[inline]
15	#[unstable(feature = "stdarch_loongarch", issue = "117427")]	15	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
16	pub unsafe fn rdtime_d() -> (i64, isize) {	16	pub fn rdtime_d() -> (i64, isize) {
17	let val: i64;	17	let (val, tid): (i64, isize);
18	let tid: isize;	18	unsafe { asm!("rdtime.d {}, {}", out(reg) val, out(reg) tid, options(readonly, nostack)) };
19	asm!("rdtime.d {}, {}", out(reg) val, out(reg) tid, options(readonly, nostack));
20	(val, tid)
21	}
22
23	/// Reads the lower 32-bit stable counter value and the counter ID
24	#[inline]
25	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
26	pub unsafe fn rdtimel_w() -> (i32, isize) {
27	let val: i32;
28	let tid: isize;
29	asm!("rdtimel.w {}, {}", out(reg) val, out(reg) tid, options(readonly, nostack));
30	(val, tid)
31	}
32
33	/// Reads the upper 32-bit stable counter value and the counter ID
34	#[inline]
35	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
36	pub unsafe fn rdtimeh_w() -> (i32, isize) {
37	let val: i32;
38	let tid: isize;
39	asm!("rdtimeh.w {}, {}", out(reg) val, out(reg) tid, options(readonly, nostack));
40	(val, tid)	19	(val, tid)
41	}	20	}
42		21
43	#[allow(improper_ctypes)]	22	#[allow(improper_ctypes)]
44	unsafe extern "unadjusted" {	23	unsafe extern "unadjusted" {
45	#[link_name = "llvm.loongarch.crc.w.b.w"]
46	fn __crc_w_b_w(a: i32, b: i32) -> i32;
47	#[link_name = "llvm.loongarch.crc.w.h.w"]
48	fn __crc_w_h_w(a: i32, b: i32) -> i32;
49	#[link_name = "llvm.loongarch.crc.w.w.w"]
50	fn __crc_w_w_w(a: i32, b: i32) -> i32;
51	#[link_name = "llvm.loongarch.crc.w.d.w"]	24	#[link_name = "llvm.loongarch.crc.w.d.w"]
52	fn __crc_w_d_w(a: i64, b: i32) -> i32;	25	fn __crc_w_d_w(a: i64, b: i32) -> i32;
53	#[link_name = "llvm.loongarch.crcc.w.b.w"]
54	fn __crcc_w_b_w(a: i32, b: i32) -> i32;
55	#[link_name = "llvm.loongarch.crcc.w.h.w"]
56	fn __crcc_w_h_w(a: i32, b: i32) -> i32;
57	#[link_name = "llvm.loongarch.crcc.w.w.w"]
58	fn __crcc_w_w_w(a: i32, b: i32) -> i32;
59	#[link_name = "llvm.loongarch.crcc.w.d.w"]	26	#[link_name = "llvm.loongarch.crcc.w.d.w"]
60	fn __crcc_w_d_w(a: i64, b: i32) -> i32;	27	fn __crcc_w_d_w(a: i64, b: i32) -> i32;
61	#[link_name = "llvm.loongarch.cacop.d"]	28	#[link_name = "llvm.loongarch.cacop.d"]
62	fn __cacop(a: i64, b: i64, c: i64);	29	fn __cacop(a: i64, b: i64, c: i64);
63	#[link_name = "llvm.loongarch.dbar"]
64	fn __dbar(a: i32);
65	#[link_name = "llvm.loongarch.ibar"]
66	fn __ibar(a: i32);
67	#[link_name = "llvm.loongarch.movgr2fcsr"]
68	fn __movgr2fcsr(a: i32, b: i32);
69	#[link_name = "llvm.loongarch.movfcsr2gr"]
70	fn __movfcsr2gr(a: i32) -> i32;
71	#[link_name = "llvm.loongarch.csrrd.d"]	30	#[link_name = "llvm.loongarch.csrrd.d"]
72	fn __csrrd(a: i32) -> i64;	31	fn __csrrd(a: i32) -> i64;
73	#[link_name = "llvm.loongarch.csrwr.d"]	32	#[link_name = "llvm.loongarch.csrwr.d"]
74	fn __csrwr(a: i64, b: i32) -> i64;	33	fn __csrwr(a: i64, b: i32) -> i64;
75	#[link_name = "llvm.loongarch.csrxchg.d"]	34	#[link_name = "llvm.loongarch.csrxchg.d"]
76	fn __csrxchg(a: i64, b: i64, c: i32) -> i64;	35	fn __csrxchg(a: i64, b: i64, c: i32) -> i64;
77	#[link_name = "llvm.loongarch.iocsrrd.b"]
78	fn __iocsrrd_b(a: i32) -> i32;
79	#[link_name = "llvm.loongarch.iocsrrd.h"]
80	fn __iocsrrd_h(a: i32) -> i32;
81	#[link_name = "llvm.loongarch.iocsrrd.w"]
82	fn __iocsrrd_w(a: i32) -> i32;
83	#[link_name = "llvm.loongarch.iocsrrd.d"]	36	#[link_name = "llvm.loongarch.iocsrrd.d"]
84	fn __iocsrrd_d(a: i32) -> i64;	37	fn __iocsrrd_d(a: i32) -> i64;
85	#[link_name = "llvm.loongarch.iocsrwr.b"]
86	fn __iocsrwr_b(a: i32, b: i32);
87	#[link_name = "llvm.loongarch.iocsrwr.h"]
88	fn __iocsrwr_h(a: i32, b: i32);
89	#[link_name = "llvm.loongarch.iocsrwr.w"]
90	fn __iocsrwr_w(a: i32, b: i32);
91	#[link_name = "llvm.loongarch.iocsrwr.d"]	38	#[link_name = "llvm.loongarch.iocsrwr.d"]
92	fn __iocsrwr_d(a: i64, b: i32);	39	fn __iocsrwr_d(a: i64, b: i32);
93	#[link_name = "llvm.loongarch.break"]
94	fn __break(a: i32);
95	#[link_name = "llvm.loongarch.cpucfg"]
96	fn __cpucfg(a: i32) -> i32;
97	#[link_name = "llvm.loongarch.syscall"]
98	fn __syscall(a: i32);
99	#[link_name = "llvm.loongarch.asrtle.d"]	40	#[link_name = "llvm.loongarch.asrtle.d"]
100	fn __asrtle(a: i64, b: i64);	41	fn __asrtle(a: i64, b: i64);
101	#[link_name = "llvm.loongarch.asrtgt.d"]	42	#[link_name = "llvm.loongarch.asrtgt.d"]
...	@@ -104,70 +45,20 @@ unsafe extern "unadjusted" {	...	@@ -104,70 +45,20 @@ unsafe extern "unadjusted" {
104	fn __lddir(a: i64, b: i64) -> i64;	45	fn __lddir(a: i64, b: i64) -> i64;
105	#[link_name = "llvm.loongarch.ldpte.d"]	46	#[link_name = "llvm.loongarch.ldpte.d"]
106	fn __ldpte(a: i64, b: i64);	47	fn __ldpte(a: i64, b: i64);
107	#[link_name = "llvm.loongarch.frecipe.s"]
108	fn __frecipe_s(a: f32) -> f32;
109	#[link_name = "llvm.loongarch.frecipe.d"]
110	fn __frecipe_d(a: f64) -> f64;
111	#[link_name = "llvm.loongarch.frsqrte.s"]
112	fn __frsqrte_s(a: f32) -> f32;
113	#[link_name = "llvm.loongarch.frsqrte.d"]
114	fn __frsqrte_d(a: f64) -> f64;
115	}	48	}
116		49
117	/// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320)	50	/// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320)
118	#[inline]	51	#[inline]
119	#[unstable(feature = "stdarch_loongarch", issue = "117427")]	52	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
120	pub unsafe fn crc_w_b_w(a: i32, b: i32) -> i32 {	53	pub fn crc_w_d_w(a: i64, b: i32) -> i32 {
121	__crc_w_b_w(a, b)	54	unsafe { __crc_w_d_w(a, b) }
122	}
123
124	/// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320)
125	#[inline]
126	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
127	pub unsafe fn crc_w_h_w(a: i32, b: i32) -> i32 {
128	__crc_w_h_w(a, b)
129	}
130
131	/// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320)
132	#[inline]
133	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
134	pub unsafe fn crc_w_w_w(a: i32, b: i32) -> i32 {
135	__crc_w_w_w(a, b)
136	}
137
138	/// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320)
139	#[inline]
140	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
141	pub unsafe fn crc_w_d_w(a: i64, b: i32) -> i32 {
142	__crc_w_d_w(a, b)
143	}
144
145	/// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78)
146	#[inline]
147	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
148	pub unsafe fn crcc_w_b_w(a: i32, b: i32) -> i32 {
149	__crcc_w_b_w(a, b)
150	}
151
152	/// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78)
153	#[inline]
154	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
155	pub unsafe fn crcc_w_h_w(a: i32, b: i32) -> i32 {
156	__crcc_w_h_w(a, b)
157	}	55	}
158		56
159	/// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78)	57	/// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78)
160	#[inline]	58	#[inline]
161	#[unstable(feature = "stdarch_loongarch", issue = "117427")]	59	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
162	pub unsafe fn crcc_w_w_w(a: i32, b: i32) -> i32 {	60	pub fn crcc_w_d_w(a: i64, b: i32) -> i32 {
163	__crcc_w_w_w(a, b)	61	unsafe { __crcc_w_d_w(a, b) }
164	}
165
166	/// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78)
167	#[inline]
168	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
169	pub unsafe fn crcc_w_d_w(a: i64, b: i32) -> i32 {
170	__crcc_w_d_w(a, b)
171	}	62	}
172		63
173	/// Generates the cache operation instruction	64	/// Generates the cache operation instruction
...	@@ -178,38 +69,6 @@ pub unsafe fn cacop<const IMM12: i64>(a: i64, b: i64) {	...	@@ -178,38 +69,6 @@ pub unsafe fn cacop<const IMM12: i64>(a: i64, b: i64) {
178	__cacop(a, b, IMM12);	69	__cacop(a, b, IMM12);
179	}	70	}
180		71
181	/// Generates the memory barrier instruction
182	#[inline]
183	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
184	pub unsafe fn dbar<const IMM15: i32>() {
185	static_assert_uimm_bits!(IMM15, 15);
186	__dbar(IMM15);
187	}
188
189	/// Generates the instruction-fetch barrier instruction
190	#[inline]
191	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
192	pub unsafe fn ibar<const IMM15: i32>() {
193	static_assert_uimm_bits!(IMM15, 15);
194	__ibar(IMM15);
195	}
196
197	/// Moves data from a GPR to the FCSR
198	#[inline]
199	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
200	pub unsafe fn movgr2fcsr<const IMM5: i32>(a: i32) {
201	static_assert_uimm_bits!(IMM5, 5);
202	__movgr2fcsr(IMM5, a);
203	}
204
205	/// Moves data from a FCSR to the GPR
206	#[inline]
207	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
208	pub unsafe fn movfcsr2gr<const IMM5: i32>() -> i32 {
209	static_assert_uimm_bits!(IMM5, 5);
210	__movfcsr2gr(IMM5)
211	}
212
213	/// Reads the CSR	72	/// Reads the CSR
214	#[inline]	73	#[inline]
215	#[unstable(feature = "stdarch_loongarch", issue = "117427")]	74	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
...	@@ -234,27 +93,6 @@ pub unsafe fn csrxchg<const IMM14: i32>(a: i64, b: i64) -> i64 {	...	@@ -234,27 +93,6 @@ pub unsafe fn csrxchg<const IMM14: i32>(a: i64, b: i64) -> i64 {
234	__csrxchg(a, b, IMM14)	93	__csrxchg(a, b, IMM14)
235	}	94	}
236		95
237	/// Reads the 8-bit IO-CSR
238	#[inline]
239	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
240	pub unsafe fn iocsrrd_b(a: i32) -> i32 {
241	__iocsrrd_b(a)
242	}
243
244	/// Reads the 16-bit IO-CSR
245	#[inline]
246	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
247	pub unsafe fn iocsrrd_h(a: i32) -> i32 {
248	__iocsrrd_h(a)
249	}
250
251	/// Reads the 32-bit IO-CSR
252	#[inline]
253	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
254	pub unsafe fn iocsrrd_w(a: i32) -> i32 {
255	__iocsrrd_w(a)
256	}
257
258	/// Reads the 64-bit IO-CSR	96	/// Reads the 64-bit IO-CSR
259	#[inline]	97	#[inline]
260	#[unstable(feature = "stdarch_loongarch", issue = "117427")]	98	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
...	@@ -262,27 +100,6 @@ pub unsafe fn iocsrrd_d(a: i32) -> i64 {	...	@@ -262,27 +100,6 @@ pub unsafe fn iocsrrd_d(a: i32) -> i64 {
262	__iocsrrd_d(a)	100	__iocsrrd_d(a)
263	}	101	}
264		102
265	/// Writes the 8-bit IO-CSR
266	#[inline]
267	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
268	pub unsafe fn iocsrwr_b(a: i32, b: i32) {
269	__iocsrwr_b(a, b)
270	}
271
272	/// Writes the 16-bit IO-CSR
273	#[inline]
274	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
275	pub unsafe fn iocsrwr_h(a: i32, b: i32) {
276	__iocsrwr_h(a, b)
277	}
278
279	/// Writes the 32-bit IO-CSR
280	#[inline]
281	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
282	pub unsafe fn iocsrwr_w(a: i32, b: i32) {
283	__iocsrwr_w(a, b)
284	}
285
286	/// Writes the 64-bit IO-CSR	103	/// Writes the 64-bit IO-CSR
287	#[inline]	104	#[inline]
288	#[unstable(feature = "stdarch_loongarch", issue = "117427")]	105	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
...	@@ -290,29 +107,6 @@ pub unsafe fn iocsrwr_d(a: i64, b: i32) {	...	@@ -290,29 +107,6 @@ pub unsafe fn iocsrwr_d(a: i64, b: i32) {
290	__iocsrwr_d(a, b)	107	__iocsrwr_d(a, b)
291	}	108	}
292		109
293	/// Generates the breakpoint instruction
294	#[inline]
295	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
296	pub unsafe fn brk<const IMM15: i32>() {
297	static_assert_uimm_bits!(IMM15, 15);
298	__break(IMM15);
299	}
300
301	/// Reads the CPU configuration register
302	#[inline]
303	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
304	pub unsafe fn cpucfg(a: i32) -> i32 {
305	__cpucfg(a)
306	}
307
308	/// Generates the syscall instruction
309	#[inline]
310	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
311	pub unsafe fn syscall<const IMM15: i32>() {
312	static_assert_uimm_bits!(IMM15, 15);
313	__syscall(IMM15);
314	}
315
316	/// Generates the less-than-or-equal asseration instruction	110	/// Generates the less-than-or-equal asseration instruction
317	#[inline]	111	#[inline]
318	#[unstable(feature = "stdarch_loongarch", issue = "117427")]	112	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
...	@@ -342,35 +136,3 @@ pub unsafe fn lddir<const B: i64>(a: i64) -> i64 {	...	@@ -342,35 +136,3 @@ pub unsafe fn lddir<const B: i64>(a: i64) -> i64 {
342	pub unsafe fn ldpte<const B: i64>(a: i64) {	136	pub unsafe fn ldpte<const B: i64>(a: i64) {
343	__ldpte(a, B)	137	__ldpte(a, B)
344	}	138	}
345
346	/// Calculate the approximate single-precision result of 1.0 divided
347	#[inline]
348	#[target_feature(enable = "frecipe")]
349	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
350	pub unsafe fn frecipe_s(a: f32) -> f32 {
351	__frecipe_s(a)
352	}
353
354	/// Calculate the approximate double-precision result of 1.0 divided
355	#[inline]
356	#[target_feature(enable = "frecipe")]
357	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
358	pub unsafe fn frecipe_d(a: f64) -> f64 {
359	__frecipe_d(a)
360	}
361
362	/// Calculate the approximate single-precision result of dividing 1.0 by the square root
363	#[inline]
364	#[target_feature(enable = "frecipe")]
365	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
366	pub unsafe fn frsqrte_s(a: f32) -> f32 {
367	__frsqrte_s(a)
368	}
369
370	/// Calculate the approximate double-precision result of dividing 1.0 by the square root
371	#[inline]
372	#[target_feature(enable = "frecipe")]
373	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
374	pub unsafe fn frsqrte_d(a: f64) -> f64 {
375	__frsqrte_d(a)
376	}

library/stdarch/crates/core_arch/src/loongarch_shared/mod.rs created+242

...	@@ -0,0 +1,242 @@
1	//! `Shared LoongArch` intrinsics
2
3	use crate::arch::asm;
4
5	/// Reads the lower 32-bit stable counter value and the counter ID
6	#[inline]
7	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
8	pub fn rdtimel_w() -> (i32, isize) {
9	let (val, tid): (i32, isize);
10	unsafe { asm!("rdtimel.w {}, {}", out(reg) val, out(reg) tid, options(readonly, nostack)) };
11	(val, tid)
12	}
13
14	/// Reads the upper 32-bit stable counter value and the counter ID
15	#[inline]
16	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
17	pub fn rdtimeh_w() -> (i32, isize) {
18	let (val, tid): (i32, isize);
19	unsafe { asm!("rdtimeh.w {}, {}", out(reg) val, out(reg) tid, options(readonly, nostack)) };
20	(val, tid)
21	}
22
23	#[allow(improper_ctypes)]
24	unsafe extern "unadjusted" {
25	#[link_name = "llvm.loongarch.crc.w.b.w"]
26	fn __crc_w_b_w(a: i32, b: i32) -> i32;
27	#[link_name = "llvm.loongarch.crc.w.h.w"]
28	fn __crc_w_h_w(a: i32, b: i32) -> i32;
29	#[link_name = "llvm.loongarch.crc.w.w.w"]
30	fn __crc_w_w_w(a: i32, b: i32) -> i32;
31	#[link_name = "llvm.loongarch.crcc.w.b.w"]
32	fn __crcc_w_b_w(a: i32, b: i32) -> i32;
33	#[link_name = "llvm.loongarch.crcc.w.h.w"]
34	fn __crcc_w_h_w(a: i32, b: i32) -> i32;
35	#[link_name = "llvm.loongarch.crcc.w.w.w"]
36	fn __crcc_w_w_w(a: i32, b: i32) -> i32;
37	#[link_name = "llvm.loongarch.dbar"]
38	fn __dbar(a: i32);
39	#[link_name = "llvm.loongarch.ibar"]
40	fn __ibar(a: i32);
41	#[link_name = "llvm.loongarch.movgr2fcsr"]
42	fn __movgr2fcsr(a: i32, b: i32);
43	#[link_name = "llvm.loongarch.movfcsr2gr"]
44	fn __movfcsr2gr(a: i32) -> i32;
45	#[link_name = "llvm.loongarch.iocsrrd.b"]
46	fn __iocsrrd_b(a: i32) -> i32;
47	#[link_name = "llvm.loongarch.iocsrrd.h"]
48	fn __iocsrrd_h(a: i32) -> i32;
49	#[link_name = "llvm.loongarch.iocsrrd.w"]
50	fn __iocsrrd_w(a: i32) -> i32;
51	#[link_name = "llvm.loongarch.iocsrwr.b"]
52	fn __iocsrwr_b(a: i32, b: i32);
53	#[link_name = "llvm.loongarch.iocsrwr.h"]
54	fn __iocsrwr_h(a: i32, b: i32);
55	#[link_name = "llvm.loongarch.iocsrwr.w"]
56	fn __iocsrwr_w(a: i32, b: i32);
57	#[link_name = "llvm.loongarch.break"]
58	fn __break(a: i32);
59	#[link_name = "llvm.loongarch.cpucfg"]
60	fn __cpucfg(a: i32) -> i32;
61	#[link_name = "llvm.loongarch.syscall"]
62	fn __syscall(a: i32);
63	#[link_name = "llvm.loongarch.frecipe.s"]
64	fn __frecipe_s(a: f32) -> f32;
65	#[link_name = "llvm.loongarch.frecipe.d"]
66	fn __frecipe_d(a: f64) -> f64;
67	#[link_name = "llvm.loongarch.frsqrte.s"]
68	fn __frsqrte_s(a: f32) -> f32;
69	#[link_name = "llvm.loongarch.frsqrte.d"]
70	fn __frsqrte_d(a: f64) -> f64;
71	}
72
73	/// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320)
74	#[inline]
75	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
76	pub fn crc_w_b_w(a: i32, b: i32) -> i32 {
77	unsafe { __crc_w_b_w(a, b) }
78	}
79
80	/// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320)
81	#[inline]
82	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
83	pub fn crc_w_h_w(a: i32, b: i32) -> i32 {
84	unsafe { __crc_w_h_w(a, b) }
85	}
86
87	/// Calculate the CRC value using the IEEE 802.3 polynomial (0xEDB88320)
88	#[inline]
89	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
90	pub fn crc_w_w_w(a: i32, b: i32) -> i32 {
91	unsafe { __crc_w_w_w(a, b) }
92	}
93
94	/// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78)
95	#[inline]
96	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
97	pub fn crcc_w_b_w(a: i32, b: i32) -> i32 {
98	unsafe { __crcc_w_b_w(a, b) }
99	}
100
101	/// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78)
102	#[inline]
103	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
104	pub fn crcc_w_h_w(a: i32, b: i32) -> i32 {
105	unsafe { __crcc_w_h_w(a, b) }
106	}
107
108	/// Calculate the CRC value using the Castagnoli polynomial (0x82F63B78)
109	#[inline]
110	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
111	pub fn crcc_w_w_w(a: i32, b: i32) -> i32 {
112	unsafe { __crcc_w_w_w(a, b) }
113	}
114
115	/// Generates the memory barrier instruction
116	#[inline]
117	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
118	pub fn dbar<const IMM15: i32>() {
119	static_assert_uimm_bits!(IMM15, 15);
120	unsafe { __dbar(IMM15) };
121	}
122
123	/// Generates the instruction-fetch barrier instruction
124	#[inline]
125	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
126	pub fn ibar<const IMM15: i32>() {
127	static_assert_uimm_bits!(IMM15, 15);
128	unsafe { __ibar(IMM15) };
129	}
130
131	/// Moves data from a GPR to the FCSR
132	#[inline]
133	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
134	pub unsafe fn movgr2fcsr<const IMM5: i32>(a: i32) {
135	static_assert_uimm_bits!(IMM5, 5);
136	__movgr2fcsr(IMM5, a);
137	}
138
139	/// Moves data from a FCSR to the GPR
140	#[inline]
141	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
142	pub fn movfcsr2gr<const IMM5: i32>() -> i32 {
143	static_assert_uimm_bits!(IMM5, 5);
144	unsafe { __movfcsr2gr(IMM5) }
145	}
146
147	/// Reads the 8-bit IO-CSR
148	#[inline]
149	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
150	pub unsafe fn iocsrrd_b(a: i32) -> i32 {
151	__iocsrrd_b(a)
152	}
153
154	/// Reads the 16-bit IO-CSR
155	#[inline]
156	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
157	pub unsafe fn iocsrrd_h(a: i32) -> i32 {
158	__iocsrrd_h(a)
159	}
160
161	/// Reads the 32-bit IO-CSR
162	#[inline]
163	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
164	pub unsafe fn iocsrrd_w(a: i32) -> i32 {
165	__iocsrrd_w(a)
166	}
167
168	/// Writes the 8-bit IO-CSR
169	#[inline]
170	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
171	pub unsafe fn iocsrwr_b(a: i32, b: i32) {
172	__iocsrwr_b(a, b)
173	}
174
175	/// Writes the 16-bit IO-CSR
176	#[inline]
177	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
178	pub unsafe fn iocsrwr_h(a: i32, b: i32) {
179	__iocsrwr_h(a, b)
180	}
181
182	/// Writes the 32-bit IO-CSR
183	#[inline]
184	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
185	pub unsafe fn iocsrwr_w(a: i32, b: i32) {
186	__iocsrwr_w(a, b)
187	}
188
189	/// Generates the breakpoint instruction
190	#[inline]
191	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
192	pub unsafe fn brk<const IMM15: i32>() {
193	static_assert_uimm_bits!(IMM15, 15);
194	__break(IMM15);
195	}
196
197	/// Reads the CPU configuration register
198	#[inline]
199	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
200	pub fn cpucfg(a: i32) -> i32 {
201	unsafe { __cpucfg(a) }
202	}
203
204	/// Generates the syscall instruction
205	#[inline]
206	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
207	pub unsafe fn syscall<const IMM15: i32>() {
208	static_assert_uimm_bits!(IMM15, 15);
209	__syscall(IMM15);
210	}
211
212	/// Calculate the approximate single-precision result of 1.0 divided
213	#[inline]
214	#[target_feature(enable = "frecipe")]
215	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
216	pub fn frecipe_s(a: f32) -> f32 {
217	unsafe { __frecipe_s(a) }
218	}
219
220	/// Calculate the approximate double-precision result of 1.0 divided
221	#[inline]
222	#[target_feature(enable = "frecipe")]
223	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
224	pub fn frecipe_d(a: f64) -> f64 {
225	unsafe { __frecipe_d(a) }
226	}
227
228	/// Calculate the approximate single-precision result of dividing 1.0 by the square root
229	#[inline]
230	#[target_feature(enable = "frecipe")]
231	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
232	pub fn frsqrte_s(a: f32) -> f32 {
233	unsafe { __frsqrte_s(a) }
234	}
235
236	/// Calculate the approximate double-precision result of dividing 1.0 by the square root
237	#[inline]
238	#[target_feature(enable = "frecipe")]
239	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
240	pub fn frsqrte_d(a: f64) -> f64 {
241	unsafe { __frsqrte_d(a) }
242	}

library/stdarch/crates/core_arch/src/mod.rs+20-1

 @@ -16,6 +16,9 @@ mod riscv_shared;
 ))]
 mod arm_shared;
+#[cfg(any(target_arch = "loongarch32", target_arch = "loongarch64", doc))]
+mod loongarch_shared;
 mod simd;
 #[doc = include_str!("core_arch_docs.md")]
 @@ -271,13 +274,25 @@ pub mod arch {
         pub use crate::core_arch::nvptx::*;
     }
-    /// Platform-specific intrinsics for the `loongarch` platform.
+    /// Platform-specific intrinsics for the `loongarch32` platform.
+    ///
+    /// See the [module documentation](../index.html) for more details.
+    #[cfg(any(target_arch = "loongarch32", doc))]
+    #[doc(cfg(target_arch = "loongarch32"))]
+    #[unstable(feature = "stdarch_loongarch", issue = "117427")]
+    pub mod loongarch32 {
+        pub use crate::core_arch::loongarch_shared::*;
+        pub use crate::core_arch::loongarch32::*;
+    }
+    /// Platform-specific intrinsics for the `loongarch64` platform.
     ///
     /// See the [module documentation](../index.html) for more details.
     #[cfg(any(target_arch = "loongarch64", doc))]
     #[doc(cfg(target_arch = "loongarch64"))]
     #[unstable(feature = "stdarch_loongarch", issue = "117427")]
     pub mod loongarch64 {
+        pub use crate::core_arch::loongarch_shared::*;
         pub use crate::core_arch::loongarch64::*;
     }
 @@ -334,6 +349,10 @@ mod powerpc64;
 #[doc(cfg(target_arch = "nvptx64"))]
 mod nvptx;
+#[cfg(any(target_arch = "loongarch32", doc))]
+#[doc(cfg(target_arch = "loongarch32"))]
+mod loongarch32;
 #[cfg(any(target_arch = "loongarch64", doc))]
 #[doc(cfg(target_arch = "loongarch64"))]
 mod loongarch64;

library/stdarch/crates/core_arch/src/s390x/vector.rs+18-7

 @@ -1181,6 +1181,20 @@ mod sealed {
     impl_vec_trait! { [VectorOrc vec_orc]+ 2c (orc) }
+    // Z vector intrinsic      C23 math.h  LLVM IR         ISO/IEC 60559 operation        inexact  vfidb parameters
+    //
+    // vec_rint                rint        llvm.rint       roundToIntegralExact           yes      0, 0
+    // vec_roundc              nearbyint   llvm.nearbyint  n/a                            no       4, 0
+    // vec_floor / vec_roundm  floor       llvm.floor      roundToIntegralTowardNegative  no       4, 7
+    // vec_ceil / vec_roundp   ceil        llvm.ceil       roundToIntegralTowardPositive  no       4, 6
+    // vec_trunc / vec_roundz  trunc       llvm.trunc      roundToIntegralTowardZero      no       4, 5
+    // vec_round               roundeven   llvm.roundeven  roundToIntegralTiesToEven      no       4, 4
+    // n/a                     round       llvm.round      roundToIntegralTiesAway        no       4, 1
+    // `simd_round_ties_even` is implemented as `llvm.rint`.
+    test_impl! { vec_rint_f32 (a: vector_float) -> vector_float [simd_round_ties_even, "vector-enhancements-1" vfisb] }
+    test_impl! { vec_rint_f64 (a: vector_double) -> vector_double [simd_round_ties_even, vfidb] }
     test_impl! { vec_roundc_f32 (a: vector_float) -> vector_float [nearbyint_v4f32,  "vector-enhancements-1" vfisb] }
     test_impl! { vec_roundc_f64 (a: vector_double) -> vector_double [nearbyint_v2f64, vfidb] }
 @@ -1189,9 +1203,6 @@ mod sealed {
     test_impl! { vec_round_f32 (a: vector_float) -> vector_float [roundeven_v4f32, _] }
     test_impl! { vec_round_f64 (a: vector_double) -> vector_double [roundeven_v2f64, _] }
-    test_impl! { vec_rint_f32 (a: vector_float) -> vector_float [simd_round_ties_even, "vector-enhancements-1" vfisb] }
-    test_impl! { vec_rint_f64 (a: vector_double) -> vector_double [simd_round_ties_even, vfidb] }
     #[unstable(feature = "stdarch_s390x", issue = "135681")]
     pub trait VectorRoundc {
         unsafe fn vec_roundc(self) -> Self;
 @@ -2254,14 +2265,14 @@ mod sealed {
     #[inline]
     #[target_feature(enable = "vector")]
-    #[cfg_attr(test, assert_instr("vlbb"))]
+    #[cfg_attr(test, assert_instr(vlbb))]
     unsafe fn test_vec_load_bndry(ptr: *const i32) -> MaybeUninit<vector_signed_int> {
         vector_signed_int::vec_load_bndry::<512>(ptr)
     }
     #[inline]
     #[target_feature(enable = "vector")]
-    #[cfg_attr(test, assert_instr(vst))]
+    #[cfg_attr(test, assert_instr(vstl))]
     unsafe fn test_vec_store_len(vector: vector_signed_int, ptr: *mut i32, byte_count: u32) {
         vector.vec_store_len(ptr, byte_count)
     }
 @@ -2787,11 +2798,11 @@ mod sealed {
     }
     test_impl! { vec_vmal_ib(a: vector_signed_char, b: vector_signed_char, c: vector_signed_char) -> vector_signed_char [simd_mladd, vmalb ] }
-    test_impl! { vec_vmal_ih(a: vector_signed_short, b: vector_signed_short, c: vector_signed_short) -> vector_signed_short[simd_mladd, vmalh ] }
+    test_impl! { vec_vmal_ih(a: vector_signed_short, b: vector_signed_short, c: vector_signed_short) -> vector_signed_short[simd_mladd, vmalhw ] }
     test_impl! { vec_vmal_if(a: vector_signed_int, b: vector_signed_int, c: vector_signed_int) -> vector_signed_int [simd_mladd, vmalf ] }
     test_impl! { vec_vmal_ub(a: vector_unsigned_char, b: vector_unsigned_char, c: vector_unsigned_char) -> vector_unsigned_char [simd_mladd, vmalb ] }
-    test_impl! { vec_vmal_uh(a: vector_unsigned_short, b: vector_unsigned_short, c: vector_unsigned_short) -> vector_unsigned_short[simd_mladd, vmalh ] }
+    test_impl! { vec_vmal_uh(a: vector_unsigned_short, b: vector_unsigned_short, c: vector_unsigned_short) -> vector_unsigned_short[simd_mladd, vmalhw ] }
     test_impl! { vec_vmal_uf(a: vector_unsigned_int, b: vector_unsigned_int, c: vector_unsigned_int) -> vector_unsigned_int [simd_mladd, vmalf ] }
     impl_mul!([VectorMladd vec_mladd] vec_vmal_ib (vector_signed_char, vector_signed_char, vector_signed_char) -> vector_signed_char );

library/stdarch/crates/intrinsic-test/src/arm/compile.rs+35-48

...	@@ -1,64 +1,51 @@	...	@@ -1,64 +1,51 @@
1	use crate::common::compile_c::CompilationCommandBuilder;	1	use crate::common::cli::ProcessedCli;
2	use crate::common::gen_c::compile_c_programs;	2	use crate::common::compile_c::{CompilationCommandBuilder, CppCompilation};
		3
		4	pub fn build_cpp_compilation(config: &ProcessedCli) -> Option<CppCompilation> {
		5	let cpp_compiler = config.cpp_compiler.as_ref()?;
3		6
4	pub fn compile_c_arm(
5	intrinsics_name_list: &[String],
6	compiler: &str,
7	target: &str,
8	cxx_toolchain_dir: Option<&str>,
9	) -> bool {
10	// -ffp-contract=off emulates Rust's approach of not fusing separate mul-add operations	7	// -ffp-contract=off emulates Rust's approach of not fusing separate mul-add operations
11	let mut command = CompilationCommandBuilder::new()	8	let mut command = CompilationCommandBuilder::new()
12	.add_arch_flags(vec!["armv8.6-a", "crypto", "crc", "dotprod", "fp16"])	9	.add_arch_flags(vec!["armv8.6-a", "crypto", "crc", "dotprod", "fp16"])
13	.set_compiler(compiler)	10	.set_compiler(cpp_compiler)
14	.set_target(target)	11	.set_target(&config.target)
15	.set_opt_level("2")	12	.set_opt_level("2")
16	.set_cxx_toolchain_dir(cxx_toolchain_dir)	13	.set_cxx_toolchain_dir(config.cxx_toolchain_dir.as_deref())
17	.set_project_root("c_programs")	14	.set_project_root("c_programs")
18	.add_extra_flags(vec!["-ffp-contract=off", "-Wno-narrowing"]);	15	.add_extra_flags(vec!["-ffp-contract=off", "-Wno-narrowing"]);
19		16
20	if !target.contains("v7") {	17	if !config.target.contains("v7") {
21	command = command.add_arch_flags(vec!["faminmax", "lut", "sha3"]);	18	command = command.add_arch_flags(vec!["faminmax", "lut", "sha3"]);
22	}	19	}
23		20
24	/*	21	if !cpp_compiler.contains("clang") {
25	* clang++ cannot link an aarch64_be object file, so we invoke
26	* aarch64_be-unknown-linux-gnu's C++ linker. This ensures that we
27	* are testing the intrinsics against LLVM.
28	*
29	* Note: setting `--sysroot=<...>` which is the obvious thing to do
30	* does not work as it gets caught up with `#include_next <stdlib.h>`
31	* not existing...
32	*/
33	if target.contains("aarch64_be") {
34	command = command
35	.set_linker(
36	cxx_toolchain_dir.unwrap_or("").to_string() + "/bin/aarch64_be-none-linux-gnu-g++",
37	)
38	.set_include_paths(vec![
39	"/include",
40	"/aarch64_be-none-linux-gnu/include",
41	"/aarch64_be-none-linux-gnu/include/c++/14.2.1",
42	"/aarch64_be-none-linux-gnu/include/c++/14.2.1/aarch64_be-none-linux-gnu",
43	"/aarch64_be-none-linux-gnu/include/c++/14.2.1/backward",
44	"/aarch64_be-none-linux-gnu/libc/usr/include",
45	]);
46	}
47
48	if !compiler.contains("clang") {
49	command = command.add_extra_flag("-flax-vector-conversions");	22	command = command.add_extra_flag("-flax-vector-conversions");
50	}	23	}
51		24
52	let compiler_commands = intrinsics_name_list	25	let mut cpp_compiler = command.into_cpp_compilation();
53	.iter()	26
54	.map(\|intrinsic_name\| {	27	if config.target.contains("aarch64_be") {
55	command	28	let Some(ref cxx_toolchain_dir) = config.cxx_toolchain_dir else {
56	.clone()	29	panic!(
57	.set_input_name(intrinsic_name)	30	"target `{}` must specify `cxx_toolchain_dir`",
58	.set_output_name(intrinsic_name)	31	config.target
59	.make_string()	32	)
60	})	33	};
61	.collect::<Vec<_>>();	34
		35	cpp_compiler.command_mut().args([
		36	&format!("--sysroot={cxx_toolchain_dir}/aarch64_be-none-linux-gnu/libc"),
		37	"--include-directory",
		38	&format!("{cxx_toolchain_dir}/aarch64_be-none-linux-gnu/include/c++/14.3.1"),
		39	"--include-directory",
		40	&format!("{cxx_toolchain_dir}/aarch64_be-none-linux-gnu/include/c++/14.3.1/aarch64_be-none-linux-gnu"),
		41	"-L",
		42	&format!("{cxx_toolchain_dir}/lib/gcc/aarch64_be-none-linux-gnu/14.3.1"),
		43	"-L",
		44	&format!("{cxx_toolchain_dir}/aarch64_be-none-linux-gnu/libc/usr/lib"),
		45	"-B",
		46	&format!("{cxx_toolchain_dir}/lib/gcc/aarch64_be-none-linux-gnu/14.3.1"),
		47	]);
		48	}
62		49
63	compile_c_programs(&compiler_commands)	50	Some(cpp_compiler)
64	}	51	}

library/stdarch/crates/intrinsic-test/src/arm/config.rs-1

...	@@ -114,7 +114,6 @@ pub const AARCH_CONFIGURATIONS: &str = r#"	...	@@ -114,7 +114,6 @@ pub const AARCH_CONFIGURATIONS: &str = r#"
114	#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_fcma))]	114	#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_fcma))]
115	#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_dotprod))]	115	#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_dotprod))]
116	#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_i8mm))]	116	#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_i8mm))]
117	#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_sha3))]
118	#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_sm4))]	117	#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_sm4))]
119	#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_ftts))]	118	#![cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), feature(stdarch_neon_ftts))]
120	#![feature(fmt_helpers_for_derive)]	119	#![feature(fmt_helpers_for_derive)]

library/stdarch/crates/intrinsic-test/src/arm/intrinsic.rs+11-4

 @@ -1,8 +1,8 @@
 use crate::common::argument::ArgumentList;
 use crate::common::indentation::Indentation;
 use crate::common::intrinsic::{Intrinsic, IntrinsicDefinition};
-use crate::common::intrinsic_helpers::{IntrinsicType, IntrinsicTypeDefinition, TypeKind};
+use crate::common::intrinsic_helpers::{IntrinsicType, IntrinsicTypeDefinition, Sign, TypeKind};
-use std::ops::Deref;
+use std::ops::{Deref, DerefMut};
 #[derive(Debug, Clone, PartialEq)]
 pub struct ArmIntrinsicType(pub IntrinsicType);
 @@ -15,6 +15,12 @@ impl Deref for ArmIntrinsicType {
     }
 }
+impl DerefMut for ArmIntrinsicType {
+    fn deref_mut(&mut self) -> &mut Self::Target {
+        &mut self.0
+    }
+}
 impl IntrinsicDefinition<ArmIntrinsicType> for Intrinsic<ArmIntrinsicType> {
     fn arguments(&self) -> ArgumentList<ArmIntrinsicType> {
         self.arguments.clone()
 @@ -73,8 +79,9 @@ impl IntrinsicDefinition<ArmIntrinsicType> for Intrinsic<ArmIntrinsicType> {
                     TypeKind::Float if self.results().inner_size() == 16 => "float16_t".to_string(),
                     TypeKind::Float if self.results().inner_size() == 32 => "float".to_string(),
                     TypeKind::Float if self.results().inner_size() == 64 => "double".to_string(),
-                    TypeKind::Int => format!("int{}_t", self.results().inner_size()),
+                    TypeKind::Int(Sign::Signed) => format!("int{}_t", self.results().inner_size()),
-                    TypeKind::UInt => format!("uint{}_t", self.results().inner_size()),
+                    TypeKind::Int(Sign::Unsigned) =>
+                        format!("uint{}_t", self.results().inner_size()),
                     TypeKind::Poly => format!("poly{}_t", self.results().inner_size()),
                     ty => todo!("print_result_c - Unknown type: {:#?}", ty),
                 },

library/stdarch/crates/intrinsic-test/src/arm/json_parser.rs+1-1

...	@@ -110,7 +110,7 @@ fn json_to_intrinsic(	...	@@ -110,7 +110,7 @@ fn json_to_intrinsic(
110	Ok(Intrinsic {	110	Ok(Intrinsic {
111	name,	111	name,
112	arguments,	112	arguments,
113	results: *results,	113	results: results,
114	arch_tags: intr.architectures,	114	arch_tags: intr.architectures,
115	})	115	})
116	}	116	}

library/stdarch/crates/intrinsic-test/src/arm/mod.rs+65-29

...	@@ -4,15 +4,20 @@ mod intrinsic;	...	@@ -4,15 +4,20 @@ mod intrinsic;
4	mod json_parser;	4	mod json_parser;
5	mod types;	5	mod types;
6		6
		7	use std::fs::File;
		8
		9	use rayon::prelude::*;
		10
		11	use crate::arm::config::POLY128_OSTREAM_DEF;
7	use crate::common::SupportedArchitectureTest;	12	use crate::common::SupportedArchitectureTest;
8	use crate::common::cli::ProcessedCli;	13	use crate::common::cli::ProcessedCli;
9	use crate::common::compare::compare_outputs;	14	use crate::common::compare::compare_outputs;
		15	use crate::common::gen_c::{write_main_cpp, write_mod_cpp};
10	use crate::common::gen_rust::compile_rust_programs;	16	use crate::common::gen_rust::compile_rust_programs;
11	use crate::common::intrinsic::{Intrinsic, IntrinsicDefinition};	17	use crate::common::intrinsic::{Intrinsic, IntrinsicDefinition};
12	use crate::common::intrinsic_helpers::TypeKind;	18	use crate::common::intrinsic_helpers::TypeKind;
13	use crate::common::write_file::{write_c_testfiles, write_rust_testfiles};	19	use crate::common::write_file::write_rust_testfiles;
14	use compile::compile_c_arm;	20	use config::{AARCH_CONFIGURATIONS, F16_FORMATTING_DEF, build_notices};
15	use config::{AARCH_CONFIGURATIONS, F16_FORMATTING_DEF, POLY128_OSTREAM_DEF, build_notices};
16	use intrinsic::ArmIntrinsicType;	21	use intrinsic::ArmIntrinsicType;
17	use json_parser::get_neon_intrinsics;	22	use json_parser::get_neon_intrinsics;
18		23
...	@@ -21,6 +26,13 @@ pub struct ArmArchitectureTest {	...	@@ -21,6 +26,13 @@ pub struct ArmArchitectureTest {
21	cli_options: ProcessedCli,	26	cli_options: ProcessedCli,
22	}	27	}
23		28
		29	fn chunk_info(intrinsic_count: usize) -> (usize, usize) {
		30	let available_parallelism = std::thread::available_parallelism().unwrap().get();
		31	let chunk_size = intrinsic_count.div_ceil(Ord::min(available_parallelism, intrinsic_count));
		32
		33	(chunk_size, intrinsic_count.div_ceil(chunk_size))
		34	}
		35
24	impl SupportedArchitectureTest for ArmArchitectureTest {	36	impl SupportedArchitectureTest for ArmArchitectureTest {
25	fn create(cli_options: ProcessedCli) -> Box<Self> {	37	fn create(cli_options: ProcessedCli) -> Box<Self> {
26	let a32 = cli_options.target.contains("v7");	38	let a32 = cli_options.target.contains("v7");
...	@@ -51,33 +63,58 @@ impl SupportedArchitectureTest for ArmArchitectureTest {	...	@@ -51,33 +63,58 @@ impl SupportedArchitectureTest for ArmArchitectureTest {
51	}	63	}
52		64
53	fn build_c_file(&self) -> bool {	65	fn build_c_file(&self) -> bool {
54	let compiler = self.cli_options.cpp_compiler.as_deref();
55	let target = &self.cli_options.target;
56	let cxx_toolchain_dir = self.cli_options.cxx_toolchain_dir.as_deref();
57	let c_target = "aarch64";	66	let c_target = "aarch64";
		67	let platform_headers = &["arm_neon.h", "arm_acle.h", "arm_fp16.h"];
58		68
59	let intrinsics_name_list = write_c_testfiles(	69	let (chunk_size, chunk_count) = chunk_info(self.intrinsics.len());
60	&self	70
61	.intrinsics	71	let cpp_compiler = compile::build_cpp_compilation(&self.cli_options).unwrap();
62	.iter()	72
63	.map(\|i\| i as &dyn IntrinsicDefinition<_>)	73	let notice = &build_notices("// ");
64	.collect::<Vec<_>>(),	74	self.intrinsics
65	target,	75	.par_chunks(chunk_size)
		76	.enumerate()
		77	.map(\|(i, chunk)\| {
		78	let c_filename = format!("c_programs/mod_{i}.cpp");
		79	let mut file = File::create(&c_filename).unwrap();
		80	write_mod_cpp(&mut file, notice, c_target, platform_headers, chunk).unwrap();
		81
		82	// compile this cpp file into a .o file
		83	let output = cpp_compiler
		84	.compile_object_file(&format!("mod_{i}.cpp"), &format!("mod_{i}.o"))?;
		85	assert!(output.status.success(), "{output:?}");
		86
		87	Ok(())
		88	})
		89	.collect::<Result<(), std::io::Error>>()
		90	.unwrap();
		91
		92	let mut file = File::create("c_programs/main.cpp").unwrap();
		93	write_main_cpp(
		94	&mut file,
66	c_target,	95	c_target,
67	&["arm_neon.h", "arm_acle.h", "arm_fp16.h"],	96	POLY128_OSTREAM_DEF,
68	&build_notices("// "),	97	self.intrinsics.iter().map(\|i\| i.name.as_str()),
69	&[POLY128_OSTREAM_DEF],	98	)
70	);	99	.unwrap();
71		100
72	match compiler {	101	// compile this cpp file into a .o file
73	None => true,	102	info!("compiling main.cpp");
74	Some(compiler) => compile_c_arm(	103	let output = cpp_compiler
75	intrinsics_name_list.as_slice(),	104	.compile_object_file("main.cpp", "intrinsic-test-programs.o")
76	compiler,	105	.unwrap();
77	target,	106	assert!(output.status.success(), "{output:?}");
78	cxx_toolchain_dir,	107
79	),	108	let object_files = (0..chunk_count)
80	}	109	.map(\|i\| format!("mod_{i}.o"))
		110	.chain(["intrinsic-test-programs.o".to_owned()]);
		111
		112	let output = cpp_compiler
		113	.link_executable(object_files, "intrinsic-test-programs")
		114	.unwrap();
		115	assert!(output.status.success(), "{output:?}");
		116
		117	true
81	}	118	}
82		119
83	fn build_rust_file(&self) -> bool {	120	fn build_rust_file(&self) -> bool {
...	@@ -104,7 +141,7 @@ impl SupportedArchitectureTest for ArmArchitectureTest {	...	@@ -104,7 +141,7 @@ impl SupportedArchitectureTest for ArmArchitectureTest {
104	}	141	}
105		142
106	fn compare_outputs(&self) -> bool {	143	fn compare_outputs(&self) -> bool {
107	if let Some(ref toolchain) = self.cli_options.toolchain {	144	if self.cli_options.toolchain.is_some() {
108	let intrinsics_name_list = self	145	let intrinsics_name_list = self
109	.intrinsics	146	.intrinsics
110	.iter()	147	.iter()
...	@@ -113,8 +150,7 @@ impl SupportedArchitectureTest for ArmArchitectureTest {	...	@@ -113,8 +150,7 @@ impl SupportedArchitectureTest for ArmArchitectureTest {
113		150
114	compare_outputs(	151	compare_outputs(
115	&intrinsics_name_list,	152	&intrinsics_name_list,
116	toolchain,	153	&self.cli_options.runner,
117	&self.cli_options.c_runner,
118	&self.cli_options.target,	154	&self.cli_options.target,
119	)	155	)
120	} else {	156	} else {

library/stdarch/crates/intrinsic-test/src/arm/types.rs+13-14

...	@@ -1,6 +1,6 @@	...	@@ -1,6 +1,6 @@
1	use super::intrinsic::ArmIntrinsicType;	1	use super::intrinsic::ArmIntrinsicType;
2	use crate::common::cli::Language;	2	use crate::common::cli::Language;
3	use crate::common::intrinsic_helpers::{IntrinsicType, IntrinsicTypeDefinition, TypeKind};	3	use crate::common::intrinsic_helpers::{IntrinsicType, IntrinsicTypeDefinition, Sign, TypeKind};
4		4
5	impl IntrinsicTypeDefinition for ArmIntrinsicType {	5	impl IntrinsicTypeDefinition for ArmIntrinsicType {
6	/// Gets a string containing the typename for this type in C format.	6	/// Gets a string containing the typename for this type in C format.
...	@@ -73,8 +73,8 @@ impl IntrinsicTypeDefinition for ArmIntrinsicType {	...	@@ -73,8 +73,8 @@ impl IntrinsicTypeDefinition for ArmIntrinsicType {
73	format!(	73	format!(
74	"vld{len}{quad}_{type}{size}",	74	"vld{len}{quad}_{type}{size}",
75	type = match k {	75	type = match k {
76	TypeKind::UInt => "u",	76	TypeKind::Int(Sign::Unsigned) => "u",
77	TypeKind::Int => "s",	77	TypeKind::Int(Sign::Signed) => "s",
78	TypeKind::Float => "f",	78	TypeKind::Float => "f",
79	// The ACLE doesn't support 64-bit polynomial loads on Armv7	79	// The ACLE doesn't support 64-bit polynomial loads on Armv7
80	// if armv7 and bl == 64, use "s", else "p"	80	// if armv7 and bl == 64, use "s", else "p"
...	@@ -107,8 +107,8 @@ impl IntrinsicTypeDefinition for ArmIntrinsicType {	...	@@ -107,8 +107,8 @@ impl IntrinsicTypeDefinition for ArmIntrinsicType {
107	format!(	107	format!(
108	"vget{quad}_lane_{type}{size}",	108	"vget{quad}_lane_{type}{size}",
109	type = match k {	109	type = match k {
110	TypeKind::UInt => "u",	110	TypeKind::Int(Sign::Unsigned) => "u",
111	TypeKind::Int => "s",	111	TypeKind::Int(Sign::Signed) => "s",
112	TypeKind::Float => "f",	112	TypeKind::Float => "f",
113	TypeKind::Poly => "p",	113	TypeKind::Poly => "p",
114	x => todo!("get_load_function TypeKind: {:#?}", x),	114	x => todo!("get_load_function TypeKind: {:#?}", x),
...	@@ -121,7 +121,7 @@ impl IntrinsicTypeDefinition for ArmIntrinsicType {	...	@@ -121,7 +121,7 @@ impl IntrinsicTypeDefinition for ArmIntrinsicType {
121	}	121	}
122	}	122	}
123		123
124	fn from_c(s: &str, target: &str) -> Result<Box<Self>, String> {	124	fn from_c(s: &str, target: &str) -> Result<Self, String> {
125	const CONST_STR: &str = "const";	125	const CONST_STR: &str = "const";
126	if let Some(s) = s.strip_suffix('*') {	126	if let Some(s) = s.strip_suffix('*') {
127	let (s, constant) = match s.trim().strip_suffix(CONST_STR) {	127	let (s, constant) = match s.trim().strip_suffix(CONST_STR) {
...	@@ -131,9 +131,8 @@ impl IntrinsicTypeDefinition for ArmIntrinsicType {	...	@@ -131,9 +131,8 @@ impl IntrinsicTypeDefinition for ArmIntrinsicType {
131	let s = s.trim_end();	131	let s = s.trim_end();
132	let temp_return = ArmIntrinsicType::from_c(s, target);	132	let temp_return = ArmIntrinsicType::from_c(s, target);
133	temp_return.map(\|mut op\| {	133	temp_return.map(\|mut op\| {
134	let edited = op.as_mut();	134	op.ptr = true;
135	edited.0.ptr = true;	135	op.ptr_constant = constant;
136	edited.0.ptr_constant = constant;
137	op	136	op
138	})	137	})
139	} else {	138	} else {
...	@@ -163,7 +162,7 @@ impl IntrinsicTypeDefinition for ArmIntrinsicType {	...	@@ -163,7 +162,7 @@ impl IntrinsicTypeDefinition for ArmIntrinsicType {
163	),	162	),
164	None => None,	163	None => None,
165	};	164	};
166	Ok(Box::new(ArmIntrinsicType(IntrinsicType {	165	Ok(ArmIntrinsicType(IntrinsicType {
167	ptr: false,	166	ptr: false,
168	ptr_constant: false,	167	ptr_constant: false,
169	constant,	168	constant,
...	@@ -172,14 +171,14 @@ impl IntrinsicTypeDefinition for ArmIntrinsicType {	...	@@ -172,14 +171,14 @@ impl IntrinsicTypeDefinition for ArmIntrinsicType {
172	simd_len,	171	simd_len,
173	vec_len,	172	vec_len,
174	target: target.to_string(),	173	target: target.to_string(),
175	})))	174	}))
176	} else {	175	} else {
177	let kind = start.parse::<TypeKind>()?;	176	let kind = start.parse::<TypeKind>()?;
178	let bit_len = match kind {	177	let bit_len = match kind {
179	TypeKind::Int => Some(32),	178	TypeKind::Int(_) => Some(32),
180	_ => None,	179	_ => None,
181	};	180	};
182	Ok(Box::new(ArmIntrinsicType(IntrinsicType {	181	Ok(ArmIntrinsicType(IntrinsicType {
183	ptr: false,	182	ptr: false,
184	ptr_constant: false,	183	ptr_constant: false,
185	constant,	184	constant,
...	@@ -188,7 +187,7 @@ impl IntrinsicTypeDefinition for ArmIntrinsicType {	...	@@ -188,7 +187,7 @@ impl IntrinsicTypeDefinition for ArmIntrinsicType {
188	simd_len: None,	187	simd_len: None,
189	vec_len: None,	188	vec_len: None,
190	target: target.to_string(),	189	target: target.to_string(),
191	})))	190	}))
192	}	191	}
193	}	192	}
194	}	193	}

library/stdarch/crates/intrinsic-test/src/common/argument.rs+18-14

...	@@ -76,7 +76,7 @@ where	...	@@ -76,7 +76,7 @@ where
76	Argument {	76	Argument {
77	pos,	77	pos,
78	name: String::from(var_name),	78	name: String::from(var_name),
79	ty: *ty,	79	ty: ty,
80	constraint,	80	constraint,
81	}	81	}
82	}	82	}
...	@@ -125,19 +125,23 @@ where	...	@@ -125,19 +125,23 @@ where
125	/// Creates a line for each argument that initializes an array for C from which `loads` argument	125	/// Creates a line for each argument that initializes an array for C from which `loads` argument
126	/// values can be loaded as a sliding window.	126	/// values can be loaded as a sliding window.
127	/// e.g `const int32x2_t a_vals = {0x3effffff, 0x3effffff, 0x3f7fffff}`, if loads=2.	127	/// e.g `const int32x2_t a_vals = {0x3effffff, 0x3effffff, 0x3f7fffff}`, if loads=2.
128	pub fn gen_arglists_c(&self, indentation: Indentation, loads: u32) -> String {	128	pub fn gen_arglists_c(
129	self.iter()	129	&self,
130	.filter(\|&arg\| !arg.has_constraint())	130	w: &mut impl std::io::Write,
131	.map(\|arg\| {	131	indentation: Indentation,
132	format!(	132	loads: u32,
133	"{indentation}const {ty} {name}_vals[] = {values};",	133	) -> std::io::Result<()> {
134	ty = arg.ty.c_scalar_type(),	134	for arg in self.iter().filter(\|&arg\| !arg.has_constraint()) {
135	name = arg.name,	135	writeln!(
136	values = arg.ty.populate_random(indentation, loads, &Language::C)	136	w,
137	)	137	"{indentation}const {ty} {name}_vals[] = {values};",
138	})	138	ty = arg.ty.c_scalar_type(),
139	.collect::<Vec<_>>()	139	name = arg.name,
140	.join("\n")	140	values = arg.ty.populate_random(indentation, loads, &Language::C)
		141	)?
		142	}
		143
		144	Ok(())
141	}	145	}
142		146
143	/// Creates a line for each argument that initializes an array for Rust from which `loads` argument	147	/// Creates a line for each argument that initializes an array for Rust from which `loads` argument

library/stdarch/crates/intrinsic-test/src/common/cli.rs+3-3

...	@@ -60,7 +60,7 @@ pub struct ProcessedCli {	...	@@ -60,7 +60,7 @@ pub struct ProcessedCli {
60	pub filename: PathBuf,	60	pub filename: PathBuf,
61	pub toolchain: Option<String>,	61	pub toolchain: Option<String>,
62	pub cpp_compiler: Option<String>,	62	pub cpp_compiler: Option<String>,
63	pub c_runner: String,	63	pub runner: String,
64	pub target: String,	64	pub target: String,
65	pub linker: Option<String>,	65	pub linker: Option<String>,
66	pub cxx_toolchain_dir: Option<String>,	66	pub cxx_toolchain_dir: Option<String>,
...	@@ -70,7 +70,7 @@ pub struct ProcessedCli {	...	@@ -70,7 +70,7 @@ pub struct ProcessedCli {
70	impl ProcessedCli {	70	impl ProcessedCli {
71	pub fn new(cli_options: Cli) -> Self {	71	pub fn new(cli_options: Cli) -> Self {
72	let filename = cli_options.input;	72	let filename = cli_options.input;
73	let c_runner = cli_options.runner.unwrap_or_default();	73	let runner = cli_options.runner.unwrap_or_default();
74	let target = cli_options.target;	74	let target = cli_options.target;
75	let linker = cli_options.linker;	75	let linker = cli_options.linker;
76	let cxx_toolchain_dir = cli_options.cxx_toolchain_dir;	76	let cxx_toolchain_dir = cli_options.cxx_toolchain_dir;
...	@@ -102,7 +102,7 @@ impl ProcessedCli {	...	@@ -102,7 +102,7 @@ impl ProcessedCli {
102	Self {	102	Self {
103	toolchain,	103	toolchain,
104	cpp_compiler,	104	cpp_compiler,
105	c_runner,	105	runner,
106	target,	106	target,
107	linker,	107	linker,
108	cxx_toolchain_dir,	108	cxx_toolchain_dir,

library/stdarch/crates/intrinsic-test/src/common/compare.rs+16-18

...	@@ -2,27 +2,25 @@ use super::cli::FailureReason;	...	@@ -2,27 +2,25 @@ use super::cli::FailureReason;
2	use rayon::prelude::*;	2	use rayon::prelude::*;
3	use std::process::Command;	3	use std::process::Command;
4		4
5	pub fn compare_outputs(	5	pub fn compare_outputs(intrinsic_name_list: &Vec<String>, runner: &str, target: &str) -> bool {
6	intrinsic_name_list: &Vec<String>,	6	fn runner_command(runner: &str) -> Command {
7	toolchain: &str,	7	let mut it = runner.split_whitespace();
8	runner: &str,	8	let mut cmd = Command::new(it.next().unwrap());
9	target: &str,	9	cmd.args(it);
10	) -> bool {	10
		11	cmd
		12	}
		13
11	let intrinsics = intrinsic_name_list	14	let intrinsics = intrinsic_name_list
12	.par_iter()	15	.par_iter()
13	.filter_map(\|intrinsic_name\| {	16	.filter_map(\|intrinsic_name\| {
14	let c = Command::new("sh")	17	let c = runner_command(runner)
15	.arg("-c")	18	.arg("./c_programs/intrinsic-test-programs")
16	.arg(format!("{runner} ./c_programs/{intrinsic_name}"))	19	.arg(intrinsic_name)
17	.output();	20	.output();
18		21
19	let rust = Command::new("sh")	22	let rust = runner_command(runner)
20	.current_dir("rust_programs")	23	.arg(format!("target/{target}/release/{intrinsic_name}"))
21	.arg("-c")
22	.arg(format!(
23	"cargo {toolchain} run --target {target} --bin {intrinsic_name} --release",
24	))
25	.env("RUSTFLAGS", "-Cdebuginfo=0")
26	.output();	24	.output();
27		25
28	let (c, rust) = match (c, rust) {	26	let (c, rust) = match (c, rust) {
...	@@ -42,8 +40,8 @@ pub fn compare_outputs(	...	@@ -42,8 +40,8 @@ pub fn compare_outputs(
42	if !rust.status.success() {	40	if !rust.status.success() {
43	error!(	41	error!(
44	"Failed to run Rust program for intrinsic {intrinsic_name}\nstdout: {stdout}\nstderr: {stderr}",	42	"Failed to run Rust program for intrinsic {intrinsic_name}\nstdout: {stdout}\nstderr: {stderr}",
45	stdout = std::str::from_utf8(&rust.stdout).unwrap_or(""),	43	stdout = String::from_utf8_lossy(&rust.stdout),
46	stderr = std::str::from_utf8(&rust.stderr).unwrap_or(""),	44	stderr = String::from_utf8_lossy(&rust.stderr),
47	);	45	);
48	return Some(FailureReason::RunRust(intrinsic_name.clone()));	46	return Some(FailureReason::RunRust(intrinsic_name.clone()));
49	}	47	}

library/stdarch/crates/intrinsic-test/src/common/compile_c.rs+59-78

...	@@ -5,11 +5,7 @@ pub struct CompilationCommandBuilder {	...	@@ -5,11 +5,7 @@ pub struct CompilationCommandBuilder {
5	cxx_toolchain_dir: Option<String>,	5	cxx_toolchain_dir: Option<String>,
6	arch_flags: Vec<String>,	6	arch_flags: Vec<String>,
7	optimization: String,	7	optimization: String,
8	include_paths: Vec<String>,
9	project_root: Option<String>,	8	project_root: Option<String>,
10	output: String,
11	input: String,
12	linker: Option<String>,
13	extra_flags: Vec<String>,	9	extra_flags: Vec<String>,
14	}	10	}
15		11
...	@@ -21,11 +17,7 @@ impl CompilationCommandBuilder {	...	@@ -21,11 +17,7 @@ impl CompilationCommandBuilder {
21	cxx_toolchain_dir: None,	17	cxx_toolchain_dir: None,
22	arch_flags: Vec::new(),	18	arch_flags: Vec::new(),
23	optimization: "2".to_string(),	19	optimization: "2".to_string(),
24	include_paths: Vec::new(),
25	project_root: None,	20	project_root: None,
26	output: String::new(),
27	input: String::new(),
28	linker: None,
29	extra_flags: Vec::new(),	21	extra_flags: Vec::new(),
30	}	22	}
31	}	23	}
...	@@ -57,37 +49,12 @@ impl CompilationCommandBuilder {	...	@@ -57,37 +49,12 @@ impl CompilationCommandBuilder {
57	self	49	self
58	}	50	}
59		51
60	/// Sets a list of include paths for compilation.
61	/// The paths that are passed must be relative to the
62	/// "cxx_toolchain_dir" directory path.
63	pub fn set_include_paths(mut self, paths: Vec<&str>) -> Self {
64	self.include_paths = paths.into_iter().map(\|path\| path.to_string()).collect();
65	self
66	}
67
68	/// Sets the root path of all the generated test files.	52	/// Sets the root path of all the generated test files.
69	pub fn set_project_root(mut self, path: &str) -> Self {	53	pub fn set_project_root(mut self, path: &str) -> Self {
70	self.project_root = Some(path.to_string());	54	self.project_root = Some(path.to_string());
71	self	55	self
72	}	56	}
73		57
74	/// The name of the output executable, without any suffixes
75	pub fn set_output_name(mut self, path: &str) -> Self {
76	self.output = path.to_string();
77	self
78	}
79
80	/// The name of the input C file, without any suffixes
81	pub fn set_input_name(mut self, path: &str) -> Self {
82	self.input = path.to_string();
83	self
84	}
85
86	pub fn set_linker(mut self, linker: String) -> Self {
87	self.linker = Some(linker);
88	self
89	}
90
91	pub fn add_extra_flags(mut self, flags: Vec<&str>) -> Self {	58	pub fn add_extra_flags(mut self, flags: Vec<&str>) -> Self {
92	let mut flags: Vec<String> = flags.into_iter().map(\|f\| f.to_string()).collect();	59	let mut flags: Vec<String> = flags.into_iter().map(\|f\| f.to_string()).collect();
93	self.extra_flags.append(&mut flags);	60	self.extra_flags.append(&mut flags);
...	@@ -100,55 +67,69 @@ impl CompilationCommandBuilder {	...	@@ -100,55 +67,69 @@ impl CompilationCommandBuilder {
100	}	67	}
101		68
102	impl CompilationCommandBuilder {	69	impl CompilationCommandBuilder {
103	pub fn make_string(self) -> String {	70	pub fn into_cpp_compilation(self) -> CppCompilation {
104	let arch_flags = self.arch_flags.join("+");	71	let mut cpp_compiler = std::process::Command::new(self.compiler);
		72
		73	if let Some(project_root) = self.project_root {
		74	cpp_compiler.current_dir(project_root);
		75	}
		76
105	let flags = std::env::var("CPPFLAGS").unwrap_or("".into());	77	let flags = std::env::var("CPPFLAGS").unwrap_or("".into());
106	let project_root = self.project_root.unwrap_or_default();	78	cpp_compiler.args(flags.split_whitespace());
107	let project_root_str = project_root.as_str();	79
108	let mut output = self.output.clone();	80	cpp_compiler.arg(format!("-march={}", self.arch_flags.join("+")));
109	if self.linker.is_some() {	81
110	output += ".o"	82	cpp_compiler.arg(format!("-O{}", self.optimization));
111	};	83
112	let mut command = format!(	84	cpp_compiler.args(self.extra_flags);
113	"{} {flags} -march={arch_flags} \
114	-O{} \
115	-o {project_root}/{} \
116	{project_root}/{}.cpp",
117	self.compiler, self.optimization, output, self.input,
118	);
119
120	command = command + " " + self.extra_flags.join(" ").as_str();
121		85
122	if let Some(target) = &self.target {	86	if let Some(target) = &self.target {
123	command = command + " --target=" + target;	87	cpp_compiler.arg(format!("--target={target}"));
124	}	88	}
125		89
126	if let (Some(linker), Some(cxx_toolchain_dir)) = (&self.linker, &self.cxx_toolchain_dir) {	90	CppCompilation(cpp_compiler)
127	let include_args = self	91	}
128	.include_paths	92	}
129	.iter()	93
130	.map(\|path\| "--include-directory=".to_string() + cxx_toolchain_dir + path)	94	pub struct CppCompilation(std::process::Command);
131	.collect::<Vec<_>>()	95
132	.join(" ");	96	fn clone_command(command: &std::process::Command) -> std::process::Command {
133		97	let mut cmd = std::process::Command::new(command.get_program());
134	command = command	98	if let Some(current_dir) = command.get_current_dir() {
135	+ " -c "	99	cmd.current_dir(current_dir);
136	+ include_args.as_str()	100	}
137	+ " && "	101	cmd.args(command.get_args());
138	+ linker	102
139	+ " "	103	for (key, val) in command.get_envs() {
140	+ project_root_str	104	cmd.env(key, val.unwrap_or_default());
141	+ "/"	105	}
142	+ &output	106
143	+ " -o "	107	cmd
144	+ project_root_str	108	}
145	+ "/"	109
146	+ &self.output	110	impl CppCompilation {
147	+ " && rm "	111	pub fn command_mut(&mut self) -> &mut std::process::Command {
148	+ project_root_str	112	&mut self.0
149	+ "/"	113	}
150	+ &output;	114
151	}	115	pub fn compile_object_file(
152	command	116	&self,
		117	input: &str,
		118	output: &str,
		119	) -> std::io::Result<std::process::Output> {
		120	let mut cmd = clone_command(&self.0);
		121	cmd.args([input, "-c", "-o", output]);
		122	cmd.output()
		123	}
		124
		125	pub fn link_executable(
		126	&self,
		127	inputs: impl Iterator<Item = String>,
		128	output: &str,
		129	) -> std::io::Result<std::process::Output> {
		130	let mut cmd = clone_command(&self.0);
		131	cmd.args(inputs);
		132	cmd.args(["-o", output]);
		133	cmd.output()
153	}	134	}
154	}	135	}

library/stdarch/crates/intrinsic-test/src/common/gen_c.rs+162-161

...	@@ -1,8 +1,3 @@	...	@@ -1,8 +1,3 @@
1	use itertools::Itertools;
2	use rayon::prelude::*;
3	use std::collections::BTreeMap;
4	use std::process::Command;
5
6	use super::argument::Argument;	1	use super::argument::Argument;
7	use super::indentation::Indentation;	2	use super::indentation::Indentation;
8	use super::intrinsic::IntrinsicDefinition;	3	use super::intrinsic::IntrinsicDefinition;
...	@@ -11,104 +6,16 @@ use super::intrinsic_helpers::IntrinsicTypeDefinition;	...	@@ -11,104 +6,16 @@ use super::intrinsic_helpers::IntrinsicTypeDefinition;
11	// The number of times each intrinsic will be called.	6	// The number of times each intrinsic will be called.
12	const PASSES: u32 = 20;	7	const PASSES: u32 = 20;
13		8
14	// Formats the main C program template with placeholders
15	pub fn format_c_main_template(
16	notices: &str,
17	header_files: &[&str],
18	arch_identifier: &str,
19	arch_specific_definitions: &[&str],
20	arglists: &str,
21	passes: &str,
22	) -> String {
23	format!(
24	r#"{notices}{header_files}
25	#include <iostream>
26	#include <cstring>
27	#include <iomanip>
28	#include <sstream>
29
30	template<typename T1, typename T2> T1 cast(T2 x) {{
31	static_assert(sizeof(T1) == sizeof(T2), "sizeof T1 and T2 must be the same");
32	T1 ret{{}};
33	memcpy(&ret, &x, sizeof(T1));
34	return ret;
35	}}
36
37	std::ostream& operator<<(std::ostream& os, float16_t value) {{
38	uint16_t temp = 0;
39	memcpy(&temp, &value, sizeof(float16_t));
40	std::stringstream ss;
41	ss << "0x" << std::setfill('0') << std::setw(4) << std::hex << temp;
42	os << ss.str();
43	return os;
44	}}
45
46	#ifdef __{arch_identifier}__
47	{arch_specific_definitions}
48	#endif
49
50	{arglists}
51
52	int main(int argc, char **argv) {{
53	{passes}
54	return 0;
55	}}"#,
56	header_files = header_files
57	.iter()
58	.map(\|header\| format!("#include <{header}>"))
59	.collect::<Vec<_>>()
60	.join("\n"),
61	arch_specific_definitions = arch_specific_definitions.join("\n"),
62	)
63	}
64
65	pub fn compile_c_programs(compiler_commands: &[String]) -> bool {
66	compiler_commands
67	.par_iter()
68	.map(\|compiler_command\| {
69	let output = Command::new("sh").arg("-c").arg(compiler_command).output();
70	if let Ok(output) = output {
71	if output.status.success() {
72	true
73	} else {
74	error!(
75	"Failed to compile code for intrinsics: \n\nstdout:\n{}\n\nstderr:\n{}",
76	std::str::from_utf8(&output.stdout).unwrap_or(""),
77	std::str::from_utf8(&output.stderr).unwrap_or("")
78	);
79	false
80	}
81	} else {
82	error!("Command failed: {output:#?}");
83	false
84	}
85	})
86	.find_any(\|x\| !x)
87	.is_none()
88	}
89
90	// Creates directory structure and file path mappings
91	pub fn setup_c_file_paths(identifiers: &Vec<String>) -> BTreeMap<&String, String> {
92	let _ = std::fs::create_dir("c_programs");
93	identifiers
94	.par_iter()
95	.map(\|identifier\| {
96	let c_filename = format!(r#"c_programs/{identifier}.cpp"#);
97
98	(identifier, c_filename)
99	})
100	.collect::<BTreeMap<&String, String>>()
101	}
102
103	pub fn generate_c_test_loop<T: IntrinsicTypeDefinition + Sized>(	9	pub fn generate_c_test_loop<T: IntrinsicTypeDefinition + Sized>(
		10	w: &mut impl std::io::Write,
104	intrinsic: &dyn IntrinsicDefinition<T>,	11	intrinsic: &dyn IntrinsicDefinition<T>,
105	indentation: Indentation,	12	indentation: Indentation,
106	additional: &str,	13	additional: &str,
107	passes: u32,	14	passes: u32,
108	_target: &str,	15	) -> std::io::Result<()> {
109	) -> String {
110	let body_indentation = indentation.nested();	16	let body_indentation = indentation.nested();
111	format!(	17	writeln!(
		18	w,
112	"{indentation}for (int i=0; i<{passes}; i++) {{\n\	19	"{indentation}for (int i=0; i<{passes}; i++) {{\n\
113	{loaded_args}\	20	{loaded_args}\
114	{body_indentation}auto __return_value = {intrinsic_call}({args});\n\	21	{body_indentation}auto __return_value = {intrinsic_call}({args});\n\
...	@@ -121,78 +28,172 @@ pub fn generate_c_test_loop<T: IntrinsicTypeDefinition + Sized>(	...	@@ -121,78 +28,172 @@ pub fn generate_c_test_loop<T: IntrinsicTypeDefinition + Sized>(
121	)	28	)
122	}	29	}
123		30
124	pub fn generate_c_constraint_blocks<T: IntrinsicTypeDefinition>(	31	pub fn generate_c_constraint_blocks<'a, T: IntrinsicTypeDefinition + 'a>(
		32	w: &mut impl std::io::Write,
125	intrinsic: &dyn IntrinsicDefinition<T>,	33	intrinsic: &dyn IntrinsicDefinition<T>,
126	indentation: Indentation,	34	indentation: Indentation,
127	constraints: &[&Argument<T>],	35	constraints: &mut (impl Iterator<Item = &'a Argument<T>> + Clone),
128	name: String,	36	name: String,
129	target: &str,	37	) -> std::io::Result<()> {
130	) -> String {	38	let Some(current) = constraints.next() else {
131	if let Some((current, constraints)) = constraints.split_last() {	39	return generate_c_test_loop(w, intrinsic, indentation, &name, PASSES);
132	let range = current	40	};
133	.constraint	41
134	.iter()	42	let body_indentation = indentation.nested();
135	.map(\|c\| c.to_range())	43	for i in current.constraint.iter().flat_map(\|c\| c.to_range()) {
136	.flat_map(\|r\| r.into_iter());	44	let ty = current.ty.c_type();
137		45
138	let body_indentation = indentation.nested();	46	writeln!(w, "{indentation}{{")?;
139	range	47	writeln!(w, "{body_indentation}{ty} {} = {i};", current.name)?;
140	.map(\|i\| {	48
141	format!(	49	generate_c_constraint_blocks(
142	"{indentation}{{\n\	50	w,
143	{body_indentation}{ty} {name} = {val};\n\	51	intrinsic,
144	{pass}\n\	52	body_indentation,
145	{indentation}}}",	53	&mut constraints.clone(),
146	name = current.name,	54	format!("{name}-{i}"),
147	ty = current.ty.c_type(),	55	)?;
148	val = i,	56
149	pass = generate_c_constraint_blocks(	57	writeln!(w, "{indentation}}}")?;
150	intrinsic,
151	body_indentation,
152	constraints,
153	format!("{name}-{i}"),
154	target,
155	)
156	)
157	})
158	.join("\n")
159	} else {
160	generate_c_test_loop(intrinsic, indentation, &name, PASSES, target)
161	}	58	}
		59
		60	Ok(())
162	}	61	}
163		62
164	// Compiles C test programs using specified compiler	63	// Compiles C test programs using specified compiler
165	pub fn create_c_test_program<T: IntrinsicTypeDefinition>(	64	pub fn create_c_test_function<T: IntrinsicTypeDefinition>(
		65	w: &mut impl std::io::Write,
166	intrinsic: &dyn IntrinsicDefinition<T>,	66	intrinsic: &dyn IntrinsicDefinition<T>,
167	header_files: &[&str],	67	) -> std::io::Result<()> {
168	target: &str,	68	let indentation = Indentation::default();
169	c_target: &str,	69
170	notices: &str,	70	writeln!(w, "int run_{}() {{", intrinsic.name())?;
171	arch_specific_definitions: &[&str],	71
172	) -> String {	72	// Define the arrays of arguments.
173	let arguments = intrinsic.arguments();	73	let arguments = intrinsic.arguments();
174	let constraints = arguments	74	arguments.gen_arglists_c(w, indentation.nested(), PASSES)?;
175	.iter()
176	.filter(\|&i\| i.has_constraint())
177	.collect_vec();
178		75
179	let indentation = Indentation::default();	76	generate_c_constraint_blocks(
180	format_c_main_template(	77	w,
181	notices,	78	intrinsic,
182	header_files,	79	indentation.nested(),
183	c_target,	80	&mut arguments.iter().rev().filter(\|&i\| i.has_constraint()),
184	arch_specific_definitions,	81	Default::default(),
185	intrinsic	82	)?;
186	.arguments()	83
187	.gen_arglists_c(indentation, PASSES)	84	writeln!(w, " return 0;")?;
188	.as_str(),	85	writeln!(w, "}}")?;
189	generate_c_constraint_blocks(	86
190	intrinsic,	87	Ok(())
191	indentation.nested(),	88	}
192	constraints.as_slice(),	89
193	Default::default(),	90	pub fn write_mod_cpp<T: IntrinsicTypeDefinition>(
194	target,	91	w: &mut impl std::io::Write,
195	)	92	notice: &str,
196	.as_str(),	93	architecture: &str,
197	)	94	platform_headers: &[&str],
		95	intrinsics: &[impl IntrinsicDefinition<T>],
		96	) -> std::io::Result<()> {
		97	write!(w, "{notice}")?;
		98
		99	for header in platform_headers {
		100	writeln!(w, "#include <{header}>")?;
		101	}
		102
		103	writeln!(
		104	w,
		105	r#"
		106	#include <iostream>
		107	#include <cstring>
		108	#include <iomanip>
		109	#include <sstream>
		110
		111	template<typename T1, typename T2> T1 cast(T2 x) {{
		112	static_assert(sizeof(T1) == sizeof(T2), "sizeof T1 and T2 must be the same");
		113	T1 ret{{}};
		114	memcpy(&ret, &x, sizeof(T1));
		115	return ret;
		116	}}
		117
		118	std::ostream& operator<<(std::ostream& os, float16_t value);
		119
		120
		121
		122	"#
		123	)?;
		124
		125	writeln!(w, "#ifdef __{architecture}__")?;
		126	writeln!(
		127	w,
		128	"std::ostream& operator<<(std::ostream& os, poly128_t value);"
		129	)?;
		130	writeln!(w, "#endif")?;
		131
		132	for intrinsic in intrinsics {
		133	create_c_test_function(w, intrinsic)?;
		134	}
		135
		136	Ok(())
		137	}
		138
		139	pub fn write_main_cpp<'a>(
		140	w: &mut impl std::io::Write,
		141	architecture: &str,
		142	arch_specific_definitions: &str,
		143	intrinsics: impl Iterator<Item = &'a str> + Clone,
		144	) -> std::io::Result<()> {
		145	writeln!(w, "#include <iostream>")?;
		146	writeln!(w, "#include <string>")?;
		147
		148	for header in ["arm_neon.h", "arm_acle.h", "arm_fp16.h"] {
		149	writeln!(w, "#include <{header}>")?;
		150	}
		151
		152	writeln!(
		153	w,
		154	r#"
		155	#include <cstring>
		156	#include <iomanip>
		157	#include <sstream>
		158
		159	std::ostream& operator<<(std::ostream& os, float16_t value) {{
		160	uint16_t temp = 0;
		161	memcpy(&temp, &value, sizeof(float16_t));
		162	std::stringstream ss;
		163	ss << "0x" << std::setfill('0') << std::setw(4) << std::hex << temp;
		164	os << ss.str();
		165	return os;
		166	}}
		167	"#
		168	)?;
		169
		170	writeln!(w, "#ifdef __{architecture}__")?;
		171	writeln!(w, "{arch_specific_definitions }")?;
		172	writeln!(w, "#endif")?;
		173
		174	for intrinsic in intrinsics.clone() {
		175	writeln!(w, "extern int run_{intrinsic}(void);")?;
		176	}
		177
		178	writeln!(w, "int main(int argc, char **argv) {{")?;
		179	writeln!(w, " std::string intrinsic_name = argv[1];")?;
		180
		181	writeln!(w, " if (false) {{")?;
		182
		183	for intrinsic in intrinsics {
		184	writeln!(w, " }} else if (intrinsic_name == \"{intrinsic}\") {{")?;
		185	writeln!(w, " return run_{intrinsic}();")?;
		186	}
		187
		188	writeln!(w, " }} else {{")?;
		189	writeln!(
		190	w,
		191	" std::cerr << \"Unknown command: \" << intrinsic_name << \"\\n\";"
		192	)?;
		193	writeln!(w, " return -1;")?;
		194	writeln!(w, " }}")?;
		195
		196	writeln!(w, "}}")?;
		197
		198	Ok(())
198	}	199	}

library/stdarch/crates/intrinsic-test/src/common/gen_rust.rs+49-50

 @@ -2,7 +2,6 @@ use itertools::Itertools;
 use rayon::prelude::*;
 use std::collections::BTreeMap;
 use std::fs::File;
-use std::io::Write;
 use std::process::Command;
 use super::argument::Argument;
 @@ -23,8 +22,8 @@ pub fn format_rust_main_template(
 ) -> String {
     format!(
         r#"{notices}#![feature(simd_ffi)]
-#![feature(link_llvm_intrinsics)]
 #![feature(f16)]
+#![allow(unused)]
 {configurations}
 {definitions}
 @@ -38,6 +37,42 @@ fn main() {{
     )
 }
+fn write_cargo_toml(w: &mut impl std::io::Write, binaries: &[String]) -> std::io::Result<()> {
+    writeln!(
+        w,
+        concat!(
+            "[package]\n",
+            "name = \"intrinsic-test-programs\"\n",
+            "version = \"{version}\"\n",
+            "authors = [{authors}]\n",
+            "license = \"{license}\"\n",
+            "edition = \"2018\"\n",
+            "[workspace]\n",
+            "[dependencies]\n",
+            "core_arch = {{ path = \"../crates/core_arch\" }}",
+        ),
+        version = env!("CARGO_PKG_VERSION"),
+        authors = env!("CARGO_PKG_AUTHORS")
+            .split(":")
+            .format_with(", ", |author, fmt| fmt(&format_args!("\"{author}\""))),
+        license = env!("CARGO_PKG_LICENSE"),
+    )?;
+    for binary in binaries {
+        writeln!(
+            w,
+            concat!(
+                "[[bin]]\n",
+                "name = \"{binary}\"\n",
+                "path = \"{binary}/main.rs\"\n",
+            ),
+            binary = binary,
+        )?;
+    }
+    Ok(())
+}
 pub fn compile_rust_programs(
     binaries: Vec<String>,
     toolchain: Option<&str>,
 @@ -45,56 +80,20 @@ pub fn compile_rust_programs(
     linker: Option<&str>,
 ) -> bool {
     let mut cargo = File::create("rust_programs/Cargo.toml").unwrap();
-    cargo
+    write_cargo_toml(&mut cargo, &binaries).unwrap();
-        .write_all(
-            format!(
-                r#"[package]
-name = "intrinsic-test-programs"
-version = "{version}"
-authors = [{authors}]
-license = "{license}"
-edition = "2018"
-[workspace]
-[dependencies]
-core_arch = {{ path = "../crates/core_arch" }}
-{binaries}"#,
-                version = env!("CARGO_PKG_VERSION"),
-                authors = env!("CARGO_PKG_AUTHORS")
-                    .split(":")
-                    .format_with(", ", |author, fmt| fmt(&format_args!("\"{author}\""))),
-                license = env!("CARGO_PKG_LICENSE"),
-                binaries = binaries
-                    .iter()
-                    .map(|binary| {
-                        format!(
-                            r#"[[bin]]
-name = "{binary}"
-path = "{binary}/main.rs""#,
-                        )
-                    })
-                    .collect::<Vec<_>>()
-                    .join("\n")
-            )
-            .into_bytes()
-            .as_slice(),
-        )
-        .unwrap();
-    let toolchain = match toolchain {
-        None => return true,
-        Some(t) => t,
-    };
     /* If there has been a linker explicitly set from the command line then
      * we want to set it via setting it in the RUSTFLAGS*/
-    let cargo_command = format!("cargo {toolchain} build --target {target} --release");
+    let mut cargo_command = Command::new("cargo");
+    cargo_command.current_dir("rust_programs");
-    let mut command = Command::new("sh");
+    if let Some(toolchain) = toolchain {
-    command
+        if !toolchain.is_empty() {
-        .current_dir("rust_programs")
+            cargo_command.arg(toolchain);
-        .arg("-c")
+        }
-        .arg(cargo_command);
+    }
+    cargo_command.args(["build", "--target", target, "--release"]);
     let mut rust_flags = "-Cdebuginfo=0".to_string();
     if let Some(linker) = linker {
 @@ -102,11 +101,11 @@ path = "{binary}/main.rs""#,
         rust_flags.push_str(linker);
         rust_flags.push_str(" -C link-args=-static");
-        command.env("CPPFLAGS", "-fuse-ld=lld");
+        cargo_command.env("CPPFLAGS", "-fuse-ld=lld");
     }
-    command.env("RUSTFLAGS", rust_flags);
+    cargo_command.env("RUSTFLAGS", rust_flags);
-    let output = command.output();
+    let output = cargo_command.output();
     if let Ok(output) = output {
         if output.status.success() {

library/stdarch/crates/intrinsic-test/src/common/intrinsic_helpers.rs+65-23

 @@ -8,14 +8,22 @@ use super::cli::Language;
 use super::indentation::Indentation;
 use super::values::value_for_array;
+#[derive(Debug, PartialEq, Copy, Clone)]
+pub enum Sign {
+    Signed,
+    Unsigned,
+}
 #[derive(Debug, PartialEq, Copy, Clone)]
 pub enum TypeKind {
     BFloat,
     Float,
-    Int,
+    Int(Sign),
-    UInt,
+    Char(Sign),
     Poly,
     Void,
+    Mask,
+    Vector,
 }
 impl FromStr for TypeKind {
 @@ -23,12 +31,17 @@ impl FromStr for TypeKind {
     fn from_str(s: &str) -> Result<Self, Self::Err> {
         match s {
-            "bfloat" => Ok(Self::BFloat),
+            "bfloat" | "BF16" => Ok(Self::BFloat),
-            "float" => Ok(Self::Float),
+            "float" | "double" | "FP16" | "FP32" | "FP64" => Ok(Self::Float),
-            "int" => Ok(Self::Int),
+            "int" | "long" | "short" | "SI8" | "SI16" | "SI32" | "SI64" => {
+                Ok(Self::Int(Sign::Signed))
+            }
             "poly" => Ok(Self::Poly),
-            "uint" | "unsigned" => Ok(Self::UInt),
+            "char" => Ok(Self::Char(Sign::Signed)),
+            "uint" | "unsigned" | "UI8" | "UI16" | "UI32" | "UI64" => Ok(Self::Int(Sign::Unsigned)),
             "void" => Ok(Self::Void),
+            "MASK" => Ok(Self::Mask),
+            "M64" | "M128" | "M256" | "M512" => Ok(Self::Vector),
             _ => Err(format!("Impossible to parse argument kind {s}")),
         }
     }
 @@ -42,10 +55,14 @@ impl fmt::Display for TypeKind {
             match self {
                 Self::BFloat => "bfloat",
                 Self::Float => "float",
-                Self::Int => "int",
+                Self::Int(Sign::Signed) => "int",
-                Self::UInt => "uint",
+                Self::Int(Sign::Unsigned) => "uint",
                 Self::Poly => "poly",
                 Self::Void => "void",
+                Self::Char(Sign::Signed) => "char",
+                Self::Char(Sign::Unsigned) => "unsigned char",
+                Self::Mask => "mask",
+                Self::Vector => "vector",
             }
         )
     }
 @@ -56,9 +73,10 @@ impl TypeKind {
     pub fn c_prefix(&self) -> &str {
         match self {
             Self::Float => "float",
-            Self::Int => "int",
+            Self::Int(Sign::Signed) => "int",
-            Self::UInt => "uint",
+            Self::Int(Sign::Unsigned) => "uint",
             Self::Poly => "poly",
+            Self::Char(Sign::Signed) => "char",
             _ => unreachable!("Not used: {:#?}", self),
         }
     }
 @@ -66,10 +84,13 @@ impl TypeKind {
     /// Gets the rust prefix for the type kind i.e. i, u, f.
     pub fn rust_prefix(&self) -> &str {
         match self {
+            Self::BFloat => "bf",
             Self::Float => "f",
-            Self::Int => "i",
+            Self::Int(Sign::Signed) => "i",
-            Self::UInt => "u",
+            Self::Int(Sign::Unsigned) => "u",
             Self::Poly => "u",
+            Self::Char(Sign::Unsigned) => "u",
+            Self::Char(Sign::Signed) => "i",
             _ => unreachable!("Unused type kind: {:#?}", self),
         }
     }
 @@ -133,11 +154,14 @@ impl IntrinsicType {
     }
     pub fn c_scalar_type(&self) -> String {
-        format!(
+        match self.kind() {
-            "{prefix}{bits}_t",
+            TypeKind::Char(_) => String::from("char"),
-            prefix = self.kind().c_prefix(),
+            _ => format!(
-            bits = self.inner_size()
+                "{prefix}{bits}_t",
-        )
+                prefix = self.kind().c_prefix(),
+                bits = self.inner_size()
+            ),
+        }
     }
     pub fn rust_scalar_type(&self) -> String {
 @@ -155,8 +179,8 @@ impl IntrinsicType {
                 bit_len: Some(8),
                 ..
             } => match kind {
-                TypeKind::Int => "(int)",
+                TypeKind::Int(Sign::Signed) => "(int)",
-                TypeKind::UInt => "(unsigned int)",
+                TypeKind::Int(Sign::Unsigned) => "(unsigned int)",
                 TypeKind::Poly => "(unsigned int)(uint8_t)",
                 _ => "",
             },
 @@ -172,6 +196,21 @@ impl IntrinsicType {
                 128 => "",
                 _ => panic!("invalid bit_len"),
             },
+            IntrinsicType {
+                kind: TypeKind::Float,
+                bit_len: Some(bit_len),
+                ..
+            } => match bit_len {
+                16 => "(float16_t)",
+                32 => "(float)",
+                64 => "(double)",
+                128 => "",
+                _ => panic!("invalid bit_len"),
+            },
+            IntrinsicType {
+                kind: TypeKind::Char(_),
+                ..
+            } => "(char)",
             _ => "",
         }
     }
 @@ -185,7 +224,7 @@ impl IntrinsicType {
         match self {
             IntrinsicType {
                 bit_len: Some(bit_len @ (8 | 16 | 32 | 64)),
-                kind: kind @ (TypeKind::Int | TypeKind::UInt | TypeKind::Poly),
+                kind: kind @ (TypeKind::Int(_) | TypeKind::Poly | TypeKind::Char(_)),
                 simd_len,
                 vec_len,
                 ..
 @@ -201,7 +240,8 @@ impl IntrinsicType {
                         .format_with(",\n", |i, fmt| {
                             let src = value_for_array(*bit_len, i);
                             assert!(src == 0 || src.ilog2() < *bit_len);
-                            if *kind == TypeKind::Int && (src >> (*bit_len - 1)) != 0 {
+                            if *kind == TypeKind::Int(Sign::Signed) && (src >> (*bit_len - 1)) != 0
+                            {
                                 // `src` is a two's complement representation of a negative value.
                                 let mask = !0u64 >> (64 - *bit_len);
                                 let ones_compl = src ^ mask;
 @@ -257,7 +297,7 @@ impl IntrinsicType {
                 ..
             } => false,
             IntrinsicType {
-                kind: TypeKind::Int | TypeKind::UInt | TypeKind::Poly,
+                kind: TypeKind::Int(_) | TypeKind::Poly,
                 ..
             } => true,
             _ => unimplemented!(),
 @@ -282,7 +322,9 @@ pub trait IntrinsicTypeDefinition: Deref<Target = IntrinsicType> {
     fn get_lane_function(&self) -> String;
     /// can be implemented in an `impl` block
-    fn from_c(_s: &str, _target: &str) -> Result<Box<Self>, String>;
+    fn from_c(_s: &str, _target: &str) -> Result<Self, String>
+    where
+        Self: Sized;
     /// Gets a string containing the typename for this type in C format.
     /// can be directly defined in `impl` blocks

library/stdarch/crates/intrinsic-test/src/common/write_file.rs-33

...	@@ -1,5 +1,3 @@	...	@@ -1,5 +1,3 @@
1	use super::gen_c::create_c_test_program;
2	use super::gen_c::setup_c_file_paths;
3	use super::gen_rust::{create_rust_test_program, setup_rust_file_paths};	1	use super::gen_rust::{create_rust_test_program, setup_rust_file_paths};
4	use super::intrinsic::IntrinsicDefinition;	2	use super::intrinsic::IntrinsicDefinition;
5	use super::intrinsic_helpers::IntrinsicTypeDefinition;	3	use super::intrinsic_helpers::IntrinsicTypeDefinition;
...	@@ -11,37 +9,6 @@ pub fn write_file(filename: &String, code: String) {	...	@@ -11,37 +9,6 @@ pub fn write_file(filename: &String, code: String) {
11	file.write_all(code.into_bytes().as_slice()).unwrap();	9	file.write_all(code.into_bytes().as_slice()).unwrap();
12	}	10	}
13		11
14	pub fn write_c_testfiles<T: IntrinsicTypeDefinition + Sized>(
15	intrinsics: &Vec<&dyn IntrinsicDefinition<T>>,
16	target: &str,
17	c_target: &str,
18	headers: &[&str],
19	notice: &str,
20	arch_specific_definitions: &[&str],
21	) -> Vec<String> {
22	let intrinsics_name_list = intrinsics
23	.iter()
24	.map(\|i\| i.name().clone())
25	.collect::<Vec<_>>();
26	let filename_mapping = setup_c_file_paths(&intrinsics_name_list);
27
28	intrinsics.iter().for_each(\|&i\| {
29	let c_code = create_c_test_program(
30	i,
31	headers,
32	target,
33	c_target,
34	notice,
35	arch_specific_definitions,
36	);
37	if let Some(filename) = filename_mapping.get(&i.name()) {
38	write_file(filename, c_code)
39	};
40	});
41
42	intrinsics_name_list
43	}
44
45	pub fn write_rust_testfiles<T: IntrinsicTypeDefinition>(	12	pub fn write_rust_testfiles<T: IntrinsicTypeDefinition>(
46	intrinsics: Vec<&dyn IntrinsicDefinition<T>>,	13	intrinsics: Vec<&dyn IntrinsicDefinition<T>>,
47	rust_target: &str,	14	rust_target: &str,

library/stdarch/crates/intrinsic-test/src/main.rs+3

 @@ -30,12 +30,15 @@ fn main() {
     let test_environment = test_environment_result.unwrap();
+    info!("building C binaries");
     if !test_environment.build_c_file() {
         std::process::exit(2);
     }
+    info!("building Rust binaries");
     if !test_environment.build_rust_file() {
         std::process::exit(3);
     }
+    info!("comaparing outputs");
     if !test_environment.compare_outputs() {
         std::process::exit(1);
     }

library/stdarch/crates/simd-test-macro/src/lib.rs+2-2

...	@@ -57,12 +57,12 @@ pub fn simd_test(	...	@@ -57,12 +57,12 @@ pub fn simd_test(
57	.unwrap_or_else(\|\| panic!("target triple contained no \"-\": {target}"))	57	.unwrap_or_else(\|\| panic!("target triple contained no \"-\": {target}"))
58	{	58	{
59	"i686" \| "x86_64" \| "i586" => "is_x86_feature_detected",	59	"i686" \| "x86_64" \| "i586" => "is_x86_feature_detected",
60	"arm" \| "armv7" => "is_arm_feature_detected",	60	"arm" \| "armv7" \| "thumbv7neon" => "is_arm_feature_detected",
61	"aarch64" \| "arm64ec" \| "aarch64_be" => "is_aarch64_feature_detected",	61	"aarch64" \| "arm64ec" \| "aarch64_be" => "is_aarch64_feature_detected",
62	maybe_riscv if maybe_riscv.starts_with("riscv") => "is_riscv_feature_detected",	62	maybe_riscv if maybe_riscv.starts_with("riscv") => "is_riscv_feature_detected",
63	"powerpc" \| "powerpcle" => "is_powerpc_feature_detected",	63	"powerpc" \| "powerpcle" => "is_powerpc_feature_detected",
64	"powerpc64" \| "powerpc64le" => "is_powerpc64_feature_detected",	64	"powerpc64" \| "powerpc64le" => "is_powerpc64_feature_detected",
65	"loongarch64" => "is_loongarch_feature_detected",	65	"loongarch32" \| "loongarch64" => "is_loongarch_feature_detected",
66	"s390x" => "is_s390x_feature_detected",	66	"s390x" => "is_s390x_feature_detected",
67	t => panic!("unknown target: {t}"),	67	t => panic!("unknown target: {t}"),
68	};	68	};

library/stdarch/crates/std_detect/README.md+1-1

...	@@ -55,7 +55,7 @@ crate from working on applications in which `std` is not available.	...	@@ -55,7 +55,7 @@ crate from working on applications in which `std` is not available.
55	application.	55	application.
56		56
57	* Linux/Android:	57	* Linux/Android:
58	* `arm{32, 64}`, `mips{32,64}{,el}`, `powerpc{32,64}{,le}`, `loongarch64`, `s390x`:	58	* `arm{32, 64}`, `mips{32,64}{,el}`, `powerpc{32,64}{,le}`, `loongarch{32,64}`, `s390x`:
59	`std_detect` supports these on Linux by querying ELF auxiliary vectors (using `getauxval`	59	`std_detect` supports these on Linux by querying ELF auxiliary vectors (using `getauxval`
60	when available), and if that fails, by querying `/proc/self/auxv`.	60	when available), and if that fails, by querying `/proc/self/auxv`.
61	* `arm64`: partial support for doing run-time feature detection by directly	61	* `arm64`: partial support for doing run-time feature detection by directly

library/stdarch/crates/std_detect/src/detect/arch/loongarch.rs+1-1

...	@@ -2,7 +2,7 @@	...	@@ -2,7 +2,7 @@
2		2
3	features! {	3	features! {
4	@TARGET: loongarch;	4	@TARGET: loongarch;
5	@CFG: target_arch = "loongarch64";	5	@CFG: any(target_arch = "loongarch32", target_arch = "loongarch64");
6	@MACRO_NAME: is_loongarch_feature_detected;	6	@MACRO_NAME: is_loongarch_feature_detected;
7	@MACRO_ATTRS:	7	@MACRO_ATTRS:
8	/// Checks if `loongarch` feature is enabled.	8	/// Checks if `loongarch` feature is enabled.

library/stdarch/crates/std_detect/src/detect/arch/mod.rs+1-1

...	@@ -49,7 +49,7 @@ cfg_if! {	...	@@ -49,7 +49,7 @@ cfg_if! {
49	} else if #[cfg(target_arch = "mips64")] {	49	} else if #[cfg(target_arch = "mips64")] {
50	#[unstable(feature = "stdarch_mips_feature_detection", issue = "111188")]	50	#[unstable(feature = "stdarch_mips_feature_detection", issue = "111188")]
51	pub use mips64::*;	51	pub use mips64::*;
52	} else if #[cfg(target_arch = "loongarch64")] {	52	} else if #[cfg(any(target_arch = "loongarch32", target_arch = "loongarch64"))] {
53	#[stable(feature = "stdarch_loongarch_feature", since = "1.89.0")]	53	#[stable(feature = "stdarch_loongarch_feature", since = "1.89.0")]
54	pub use loongarch::*;	54	pub use loongarch::*;
55	} else if #[cfg(target_arch = "s390x")] {	55	} else if #[cfg(target_arch = "s390x")] {

library/stdarch/crates/std_detect/src/detect/mod.rs+1

...	@@ -103,6 +103,7 @@ pub fn features() -> impl Iterator<Item = (&'static str, bool)> {	...	@@ -103,6 +103,7 @@ pub fn features() -> impl Iterator<Item = (&'static str, bool)> {
103	target_arch = "powerpc64",	103	target_arch = "powerpc64",
104	target_arch = "mips",	104	target_arch = "mips",
105	target_arch = "mips64",	105	target_arch = "mips64",
		106	target_arch = "loongarch32",
106	target_arch = "loongarch64",	107	target_arch = "loongarch64",
107	target_arch = "s390x",	108	target_arch = "s390x",
108	))] {	109	))] {

library/stdarch/crates/std_detect/src/detect/os/linux/auxvec.rs+2

...	@@ -80,6 +80,7 @@ pub(crate) fn auxv() -> Result<AuxVec, ()> {	...	@@ -80,6 +80,7 @@ pub(crate) fn auxv() -> Result<AuxVec, ()> {
80	target_arch = "riscv64",	80	target_arch = "riscv64",
81	target_arch = "mips",	81	target_arch = "mips",
82	target_arch = "mips64",	82	target_arch = "mips64",
		83	target_arch = "loongarch32",
83	target_arch = "loongarch64",	84	target_arch = "loongarch64",
84	))]	85	))]
85	{	86	{
...	@@ -182,6 +183,7 @@ fn auxv_from_buf(buf: &[usize]) -> Result<AuxVec, ()> {	...	@@ -182,6 +183,7 @@ fn auxv_from_buf(buf: &[usize]) -> Result<AuxVec, ()> {
182	target_arch = "riscv64",	183	target_arch = "riscv64",
183	target_arch = "mips",	184	target_arch = "mips",
184	target_arch = "mips64",	185	target_arch = "mips64",
		186	target_arch = "loongarch32",
185	target_arch = "loongarch64",	187	target_arch = "loongarch64",
186	))]	188	))]
187	{	189	{

library/stdarch/crates/std_detect/src/detect/os/linux/mod.rs+1-1

...	@@ -51,7 +51,7 @@ cfg_if::cfg_if! {	...	@@ -51,7 +51,7 @@ cfg_if::cfg_if! {
51	} else if #[cfg(any(target_arch = "powerpc", target_arch = "powerpc64"))] {	51	} else if #[cfg(any(target_arch = "powerpc", target_arch = "powerpc64"))] {
52	mod powerpc;	52	mod powerpc;
53	pub(crate) use self::powerpc::detect_features;	53	pub(crate) use self::powerpc::detect_features;
54	} else if #[cfg(target_arch = "loongarch64")] {	54	} else if #[cfg(any(target_arch = "loongarch32", target_arch = "loongarch64"))] {
55	mod loongarch;	55	mod loongarch;
56	pub(crate) use self::loongarch::detect_features;	56	pub(crate) use self::loongarch::detect_features;
57	} else if #[cfg(target_arch = "s390x")] {	57	} else if #[cfg(target_arch = "s390x")] {

library/stdarch/crates/std_detect/tests/macro_trailing_commas.rs+5-3

...	@@ -11,6 +11,7 @@	...	@@ -11,6 +11,7 @@
11	target_arch = "s390x",	11	target_arch = "s390x",
12	target_arch = "riscv32",	12	target_arch = "riscv32",
13	target_arch = "riscv64",	13	target_arch = "riscv64",
		14	target_arch = "loongarch32",
14	target_arch = "loongarch64"	15	target_arch = "loongarch64"
15	),	16	),
16	feature(stdarch_internal)	17	feature(stdarch_internal)
...	@@ -30,7 +31,7 @@	...	@@ -30,7 +31,7 @@
30	feature(stdarch_riscv_feature_detection)	31	feature(stdarch_riscv_feature_detection)
31	)]	32	)]
32	#![cfg_attr(	33	#![cfg_attr(
33	target_arch = "loongarch64",	34	any(target_arch = "loongarch32", target_arch = "loongarch64"),
34	feature(stdarch_loongarch_feature_detection)	35	feature(stdarch_loongarch_feature_detection)
35	)]	36	)]
36		37
...	@@ -45,6 +46,7 @@	...	@@ -45,6 +46,7 @@
45	target_arch = "s390x",	46	target_arch = "s390x",
46	target_arch = "riscv32",	47	target_arch = "riscv32",
47	target_arch = "riscv64",	48	target_arch = "riscv64",
		49	target_arch = "loongarch32",
48	target_arch = "loongarch64"	50	target_arch = "loongarch64"
49	))]	51	))]
50	#[macro_use]	52	#[macro_use]
...	@@ -65,8 +67,8 @@ fn aarch64() {	...	@@ -65,8 +67,8 @@ fn aarch64() {
65	}	67	}
66		68
67	#[test]	69	#[test]
68	#[cfg(target_arch = "loongarch64")]	70	#[cfg(any(target_arch = "loongarch32", target_arch = "loongarch64"))]
69	fn loongarch64() {	71	fn loongarch() {
70	let _ = is_loongarch_feature_detected!("lsx");	72	let _ = is_loongarch_feature_detected!("lsx");
71	let _ = is_loongarch_feature_detected!("lsx",);	73	let _ = is_loongarch_feature_detected!("lsx",);
72	}	74	}

library/stdarch/crates/stdarch-gen-arm/Cargo.toml-1

...	@@ -13,7 +13,6 @@ edition = "2024"	...	@@ -13,7 +13,6 @@ edition = "2024"
13		13
14	[dependencies]	14	[dependencies]
15	itertools = "0.14.0"	15	itertools = "0.14.0"
16	lazy_static = "1.4.0"
17	proc-macro2 = "1.0"	16	proc-macro2 = "1.0"
18	quote = "1.0"	17	quote = "1.0"
19	regex = "1.5"	18	regex = "1.5"

library/stdarch/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml+66-128

 @@ -187,7 +187,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
     return_type: "{neon_type[1]}"
     attr: [*neon-stable]
-    assert_instr: [sabdl]
+    assert_instr: [sabdl2]
     safety: safe
     types:
       - [int8x16_t, int16x8_t, int8x8_t, uint8x8_t]
 @@ -230,7 +230,7 @@ intrinsics:
           - stable
           - - 'feature = "neon_intrinsics"'
             - 'since = "1.59.0"'
-    assert_instr: [sabdl]
+    assert_instr: [sabdl2]
     safety: safe
     types:
       - [int16x8_t, int32x4_t, int16x4_t, uint16x4_t]
 @@ -273,7 +273,7 @@ intrinsics:
           - stable
           - - 'feature = "neon_intrinsics"'
             - 'since = "1.59.0"'
-    assert_instr: [sabdl]
+    assert_instr: [sabdl2]
     safety: safe
     types:
       - [int32x4_t, int64x2_t, int32x2_t, uint32x2_t]
 @@ -1462,7 +1462,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}"]
     return_type: "{neon_type[1]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtl]]}]]
+      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtl2]]}]]
       - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
     safety: safe
     types:
 @@ -1530,7 +1530,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
     return_type: "{neon_type[2]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtn]]}]]
+      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtn2]]}]]
       - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
     safety: safe
     types:
 @@ -1582,7 +1582,7 @@ intrinsics:
     arguments: ["a: {type[0]}", "b: {neon_type[1]}"]
     return_type: "{type[2]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtxn]]}]]
+      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtxn2]]}]]
       - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
     safety: safe
     types:
 @@ -5147,7 +5147,7 @@ intrinsics:
     attr:
       - *neon-stable
     safety: safe
-    assert_instr: [pmull]
+    assert_instr: [pmull2]
     types:
       - [poly8x16_t, poly8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', poly16x8_t]
     compose:
 @@ -5169,7 +5169,7 @@ intrinsics:
       - *neon-aes
       - *neon-stable
     safety: safe
-    assert_instr: [pmull]
+    assert_instr: [pmull2]
     types:
       - [poly64x2_t, "p128"]
     compose:
 @@ -5741,7 +5741,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
     return_type: "{neon_type[0]}"
     attr: [*neon-stable]
-    assert_instr: [ssubw]
+    assert_instr: [ssubw2]
     safety: safe
     types:
       - [int16x8_t, int8x16_t, int8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]']
 @@ -5762,7 +5762,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"]
     return_type: "{neon_type[0]}"
     attr: [*neon-stable]
-    assert_instr: [usubw]
+    assert_instr: [usubw2]
     safety: safe
     types:
       - [uint16x8_t, uint8x16_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]']
 @@ -5783,7 +5783,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
     return_type: "{neon_type[1]}"
     attr: [*neon-stable]
-    assert_instr: [ssubl]
+    assert_instr: [ssubl2]
     safety: safe
     types:
       - [int8x16_t, int16x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', int8x8_t]
 @@ -5813,7 +5813,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
     return_type: "{neon_type[1]}"
     attr: [*neon-stable]
-    assert_instr: [usubl]
+    assert_instr: [usubl2]
     safety: safe
     types:
       - [uint8x16_t, uint16x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', uint8x8_t]
 @@ -6580,7 +6580,6 @@ intrinsics:
               arch: aarch64,arm64ec
   - name: "vmaxnm{neon_type.no}"
     doc: Floating-point Maximum Number (vector)
     arguments: ["a: {neon_type}", "b: {neon_type}"]
 @@ -6592,11 +6591,7 @@ intrinsics:
       - float64x1_t
       - float64x2_t
     compose:
-      - LLVMLink:
+      - FnCall: [simd_fmax, [a, b]]
-          name: "fmaxnm.{neon_type}"
-          links:
-            - link: "llvm.aarch64.neon.fmaxnm.{neon_type}"
-              arch: aarch64,arm64ec
   - name: "vmaxnmh_{type}"
 @@ -6611,11 +6606,7 @@ intrinsics:
     types:
       - f16
     compose:
-      - LLVMLink:
+      - FnCall: ["f16::max", [a, b]]
-          name: "vmaxh.{neon_type}"
-          links:
-            - link: "llvm.aarch64.neon.fmaxnm.{type}"
-              arch: aarch64,arm64ec
   - name: "vminnmh_{type}"
 @@ -6630,11 +6621,7 @@ intrinsics:
     types:
       - f16
     compose:
-      - LLVMLink:
+      - FnCall: ["f16::min", [a, b]]
-          name: "vminh.{neon_type}"
-          links:
-            - link: "llvm.aarch64.neon.fminnm.{type}"
-              arch: aarch64,arm64ec
   - name: "vmaxnmv{neon_type[0].no}"
 @@ -6648,11 +6635,7 @@ intrinsics:
       - [float32x2_t, f32]
       - [float64x2_t, f64]
     compose:
-      - LLVMLink:
+      - FnCall: [simd_reduce_max, [a]]
-          name: "fmaxnmv.{neon_type[0]}"
-          links:
-            - link: "llvm.aarch64.neon.fmaxnmv.{type[1]}.{neon_type[0]}"
-              arch: aarch64,arm64ec
   - name: "vmaxnmv{neon_type[0].no}"
     doc: Floating-point maximum number across vector
 @@ -6664,11 +6647,7 @@ intrinsics:
     types:
       - [float32x4_t, f32]
     compose:
-      - LLVMLink:
+      - FnCall: [simd_reduce_max, [a]]
-          name: "fmaxnmv.{neon_type[0]}"
-          links:
-            - link: "llvm.aarch64.neon.fmaxnmv.{type[1]}.{neon_type[0]}"
-              arch: aarch64,arm64ec
   - name: "vmaxnmv{neon_type[0].no}"
 @@ -6684,11 +6663,7 @@ intrinsics:
       - [float16x4_t, f16]
       - [float16x8_t, f16]
     compose:
-      - LLVMLink:
+      - FnCall: [simd_reduce_max, [a]]
-          name: "fmaxnmv.{neon_type[0]}"
-          links:
-            - link: "llvm.aarch64.neon.fmaxnmv.{type[1]}.{neon_type[0]}"
-              arch: aarch64,arm64ec
   - name: "vminnmv{neon_type[0].no}"
 @@ -6704,11 +6679,7 @@ intrinsics:
       - [float16x4_t, f16]
       - [float16x8_t, f16]
     compose:
-      - LLVMLink:
+      - FnCall: [simd_reduce_min, [a]]
-          name: "fminnmv.{neon_type[0]}"
-          links:
-            - link: "llvm.aarch64.neon.fminnmv.{type[1]}.{neon_type[0]}"
-              arch: aarch64,arm64ec
   - name: "vmaxv{neon_type[0].no}"
 @@ -6814,11 +6785,7 @@ intrinsics:
       - float64x1_t
       - float64x2_t
     compose:
-      - LLVMLink:
+      - FnCall: [simd_fmin, [a, b]]
-          name: "fminnm.{neon_type}"
-          links:
-            - link: "llvm.aarch64.neon.fminnm.{neon_type}"
-              arch: aarch64,arm64ec
   - name: "vminnmv{neon_type[0].no}"
     doc: "Floating-point minimum number across vector"
 @@ -6832,11 +6799,7 @@ intrinsics:
       - [float32x2_t, "f32"]
       - [float64x2_t, "f64"]
     compose:
-      - LLVMLink:
+      - FnCall: [simd_reduce_min, [a]]
-          name: "vminnmv.{neon_type[0]}"
-          links:
-            - link: "llvm.aarch64.neon.fminnmv.{type[1]}.{neon_type[0]}"
-              arch: aarch64,arm64ec
   - name: "vminnmv{neon_type[0].no}"
     doc: "Floating-point minimum number across vector"
 @@ -6849,11 +6812,7 @@ intrinsics:
     types:
       - [float32x4_t, "f32"]
     compose:
-      - LLVMLink:
+      - FnCall: [simd_reduce_min, [a]]
-          name: "vminnmv.{neon_type[0]}"
-          links:
-            - link: "llvm.aarch64.neon.fminnmv.{type[1]}.{neon_type[0]}"
-              arch: aarch64,arm64ec
   - name: "vmovl_high{neon_type[0].noq}"
     doc: Vector move
 @@ -9950,7 +9909,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
-      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [uabal]]}]]
+      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [uabal2]]}]]
     safety: safe
     types:
       - [uint16x8_t, uint8x16_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', '[8, 9, 10, 11, 12, 13, 14, 15]']
 @@ -9977,7 +9936,7 @@ intrinsics:
     return_type: "{neon_type[0]}"
     attr:
       - *neon-stable
-      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [sabal]]}]]
+      - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [sabal2]]}]]
     safety: safe
     types:
       - [int16x8_t, int8x16_t, int8x16_t, '[8, 9, 10, 11, 12, 13, 14, 15]', int8x8_t, uint8x8_t]
 @@ -11386,7 +11345,7 @@ intrinsics:
     arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"]
     return_type: "{neon_type[1]}"
     attr:
-      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uabdl]]}]]
+      - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uabdl2]]}]]
       - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]
     safety: safe
     types:
 @@ -13023,6 +12982,26 @@ intrinsics:
             - link: "llvm.aarch64.crc32cx"
               arch: aarch64,arm64ec
+  - name: "vabsd_s64"
+    doc: "Absolute Value (wrapping)."
+    arguments: ["a: {type[1]}"]
+    return_type: "{type[1]}"
+    attr:
+      - *neon-stable
+    assert_instr: [abs]
+    safety: safe
+    types:
+      - [i64, i64]
+    compose:
+      # This is behaviorally equivalent to `i64::wrapping_abs`, but keeps the value in a SIMD
+      # register. That can be beneficial when combined with other instructions. This LLVM
+      # issue provides some extra context https://github.com/llvm/llvm-project/issues/148388.
+      - LLVMLink:
+          name: "vabsd_s64"
+          links:
+             - link: "llvm.aarch64.neon.abs.i64"
+               arch: aarch64,arm64ec
   - name: "{type[0]}"
     doc: "Absolute Value (wrapping)."
     arguments: ["a: {type[1]}"]
 @@ -13032,15 +13011,18 @@ intrinsics:
     assert_instr: [abs]
     safety: safe
     types:
-      - ['vabsd_s64', i64, i64]
       - ['vabs_s64', int64x1_t, v1i64]
       - ['vabsq_s64', int64x2_t, v2i64]
     compose:
-      - LLVMLink:
+      - Let:
-          name: "{type[0]}"
+          - neg
-          links:
+          - "{type[1]}"
-            - link: "llvm.aarch64.neon.abs.{type[2]}"
+          - FnCall: [simd_neg, [a]]
-              arch: aarch64,arm64ec
+      - Let:
+          - mask
+          - "{type[1]}"
+          - FnCall: [simd_ge, [a, neg]]
+      - FnCall: [simd_select, [mask, a, neg]]
   - name: "vuqadd{neon_type[0].no}"
     doc: "Signed saturating Accumulate of Unsigned value."
 @@ -13142,11 +13124,7 @@ intrinsics:
     types:
       - [int64x2_t, i64]
     compose:
-      - FnCall:
+      - FnCall: [simd_reduce_add_unordered, [a]]
-          - transmute
-          - - FnCall:
-                - "vaddvq_u64"
-                - - FnCall: [transmute, [a]]
   - name: "vpaddd_u64"
     doc: "Add pairwise"
 @@ -13159,7 +13137,7 @@ intrinsics:
     types:
       - [uint64x2_t, u64]
     compose:
-      - FnCall: [vaddvq_u64, [a]]
+      - FnCall: [simd_reduce_add_unordered, [a]]
   - name: "vaddv{neon_type[0].no}"
     doc: "Add across vector"
 @@ -13176,11 +13154,7 @@ intrinsics:
       - [int16x8_t, i16]
       - [int32x4_t, i32]
     compose:
-      - LLVMLink:
+      - FnCall: [simd_reduce_add_unordered, [a]]
-          name: "vaddv{neon_type[0].no}"
-          links:
-            - link: "llvm.aarch64.neon.saddv.{type[1]}.{neon_type[0]}"
-              arch: aarch64,arm64ec
   - name: "vaddv{neon_type[0].no}"
     doc: "Add across vector"
 @@ -13193,11 +13167,7 @@ intrinsics:
     types:
       - [int32x2_t, i32]
     compose:
-      - LLVMLink:
+      - FnCall: [simd_reduce_add_unordered, [a]]
-          name: "vaddv{neon_type[0].no}"
-          links:
-            - link: "llvm.aarch64.neon.saddv.i32.{neon_type[0]}"
-              arch: aarch64,arm64ec
   - name: "vaddv{neon_type[0].no}"
     doc: "Add across vector"
 @@ -13210,11 +13180,7 @@ intrinsics:
     types:
       - [int64x2_t, i64]
     compose:
-      - LLVMLink:
+      - FnCall: [simd_reduce_add_unordered, [a]]
-          name: "vaddv{neon_type[0].no}"
-          links:
-            - link: "llvm.aarch64.neon.saddv.i64.{neon_type[0]}"
-              arch: aarch64,arm64ec
   - name: "vaddv{neon_type[0].no}"
     doc: "Add across vector"
 @@ -13231,11 +13197,7 @@ intrinsics:
       - [uint16x8_t, u16]
       - [uint32x4_t, u32]
     compose:
-      - LLVMLink:
+      - FnCall: [simd_reduce_add_unordered, [a]]
-          name: "vaddv{neon_type[0].no}"
-          links:
-            - link: "llvm.aarch64.neon.uaddv.{type[1]}.{neon_type[0]}"
-              arch: aarch64,arm64ec
   - name: "vaddv{neon_type[0].no}"
     doc: "Add across vector"
 @@ -13248,11 +13210,7 @@ intrinsics:
     types:
       - [uint32x2_t, u32, i32]
     compose:
-      - LLVMLink:
+      - FnCall: [simd_reduce_add_unordered, [a]]
-          name: "vaddv{neon_type[0].no}"
-          links:
-            - link: "llvm.aarch64.neon.uaddv.{type[2]}.{neon_type[0]}"
-              arch: aarch64,arm64ec
   - name: "vaddv{neon_type[0].no}"
     doc: "Add across vector"
 @@ -13265,11 +13223,7 @@ intrinsics:
     types:
       - [uint64x2_t, u64, i64]
     compose:
-      - LLVMLink:
+      - FnCall: [simd_reduce_add_unordered, [a]]
-          name: "vaddv{neon_type[0].no}"
-          links:
-            - link: "llvm.aarch64.neon.uaddv.{type[2]}.{neon_type[0]}"
-              arch: aarch64,arm64ec
   - name: "vaddlv{neon_type[0].no}"
     doc: "Signed Add Long across Vector"
 @@ -13327,11 +13281,7 @@ intrinsics:
       - [int16x8_t, i16, 'smaxv']
       - [int32x4_t, i32, 'smaxv']
     compose:
-      - LLVMLink:
+      - FnCall: [simd_reduce_max, [a]]
-          name: "vmaxv{neon_type[0].no}"
-          links:
-            - link: "llvm.aarch64.neon.smaxv.{type[1]}.{neon_type[0]}"
-              arch: aarch64,arm64ec
   - name: "vmaxv{neon_type[0].no}"
     doc: "Horizontal vector max."
 @@ -13349,11 +13299,7 @@ intrinsics:
       - [uint16x8_t, u16, 'umaxv']
       - [uint32x4_t, u32, 'umaxv']
     compose:
-      - LLVMLink:
+      - FnCall: [simd_reduce_max, [a]]
-          name: "vmaxv{neon_type[0].no}"
-          links:
-            - link: "llvm.aarch64.neon.umaxv.{type[1]}.{neon_type[0]}"
-              arch: aarch64,arm64ec
   - name: "vmaxv{neon_type[0].no}"
     doc: "Horizontal vector max."
 @@ -13390,11 +13336,7 @@ intrinsics:
       - [int16x8_t, i16, 'sminv']
       - [int32x4_t, i32, 'sminv']
     compose:
-      - LLVMLink:
+      - FnCall: [simd_reduce_min, [a]]
-          name: "vminv{neon_type[0].no}"
-          links:
-            - link: "llvm.aarch64.neon.sminv.{type[1]}.{neon_type[0]}"
-              arch: aarch64,arm64ec
   - name: "vminv{neon_type[0].no}"
     doc: "Horizontal vector min."
 @@ -13412,11 +13354,7 @@ intrinsics:
       - [uint16x8_t, u16, 'uminv']
       - [uint32x4_t, u32, 'uminv']
     compose:
-      - LLVMLink:
+      - FnCall: [simd_reduce_min, [a]]
-          name: "vminv{neon_type[0].no}"
-          links:
-            - link: "llvm.aarch64.neon.uminv.{type[1]}.{neon_type[0]}"
-              arch: aarch64,arm64ec
   - name: "vminv{neon_type[0].no}"
     doc: "Horizontal vector min."

library/stdarch/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml+85-119

 @@ -7135,13 +7135,8 @@ intrinsics:
       - int32x2_t
       - int32x4_t
     compose:
-      - LLVMLink:
+      - Let: [mask, "{neon_type}", {FnCall: [simd_ge, [a, b]]}]
-          name: "smax.{neon_type}"
+      - FnCall: [simd_select, [mask, a, b]]
-          links:
-            - link: "llvm.arm.neon.vmaxs.{neon_type}"
-              arch: arm
-            - link: "llvm.aarch64.neon.smax.{neon_type}"
-              arch: aarch64,arm64ec
   - name: "vmax{neon_type.no}"
     doc: Maximum (vector)
 @@ -7162,13 +7157,8 @@ intrinsics:
       - uint32x2_t
       - uint32x4_t
     compose:
-      - LLVMLink:
+      - Let: [mask, "{neon_type}", {FnCall: [simd_ge, [a, b]]}]
-          name: "smax.{neon_type}"
+      - FnCall: [simd_select, [mask, a, b]]
-          links:
-            - link: "llvm.arm.neon.vmaxu.{neon_type}"
-              arch: arm
-            - link: "llvm.aarch64.neon.umax.{neon_type}"
-              arch: aarch64,arm64ec
   - name: "vmax{neon_type.no}"
     doc: Maximum (vector)
 @@ -7233,13 +7223,7 @@ intrinsics:
       - float32x2_t
       - float32x4_t
     compose:
-      - LLVMLink:
+      - FnCall: [simd_fmax, [a, b]]
-          name: "fmaxnm.{neon_type}"
-          links:
-            - link: "llvm.arm.neon.vmaxnm.{neon_type}"
-              arch: arm
-            - link: "llvm.aarch64.neon.fmaxnm.{neon_type}"
-              arch: aarch64,arm64ec
   - name: "vmaxnm{neon_type.no}"
 @@ -7257,13 +7241,7 @@ intrinsics:
       - float16x4_t
       - float16x8_t
     compose:
-      - LLVMLink:
+      - FnCall: [simd_fmax, [a, b]]
-          name: "fmaxnm.{neon_type}"
-          links:
-            - link: "llvm.arm.neon.vmaxnm.{neon_type}"
-              arch: arm
-            - link: "llvm.aarch64.neon.fmaxnm.{neon_type}"
-              arch: aarch64,arm64ec
   - name: "vminnm{neon_type.no}"
 @@ -7281,13 +7259,7 @@ intrinsics:
       - float16x4_t
       - float16x8_t
     compose:
-      - LLVMLink:
+      - FnCall: [simd_fmin, [a, b]]
-          name: "fminnm.{neon_type}"
-          links:
-            - link: "llvm.arm.neon.vminnm.{neon_type}"
-              arch: arm
-            - link: "llvm.aarch64.neon.fminnm.{neon_type}"
-              arch: aarch64,arm64ec
   - name: "vmin{neon_type.no}"
 @@ -7309,13 +7281,8 @@ intrinsics:
       - int32x2_t
       - int32x4_t
     compose:
-      - LLVMLink:
+      - Let: [mask, "{neon_type}", {FnCall: [simd_le, [a, b]]}]
-          name: "smin.{neon_type}"
+      - FnCall: [simd_select, [mask, a, b]]
-          links:
-            - link: "llvm.arm.neon.vmins.{neon_type}"
-              arch: arm
-            - link: "llvm.aarch64.neon.smin.{neon_type}"
-              arch: aarch64,arm64ec
   - name: "vmin{neon_type.no}"
     doc: "Minimum (vector)"
 @@ -7336,13 +7303,8 @@ intrinsics:
       - uint32x2_t
       - uint32x4_t
     compose:
-      - LLVMLink:
+      - Let: [mask, "{neon_type}", {FnCall: [simd_le, [a, b]]}]
-          name: "umin.{neon_type}"
+      - FnCall: [simd_select, [mask, a, b]]
-          links:
-            - link: "llvm.arm.neon.vminu.{neon_type}"
-              arch: arm
-            - link: "llvm.aarch64.neon.umin.{neon_type}"
-              arch: aarch64,arm64ec
   - name: "vmin{neon_type.no}"
     doc: "Minimum (vector)"
 @@ -7408,13 +7370,7 @@ intrinsics:
       - float32x2_t
       - float32x4_t
     compose:
-      - LLVMLink:
+      - FnCall: [simd_fmin, [a, b]]
-          name: "fminnm.{neon_type}"
-          links:
-            - link: "llvm.arm.neon.vminnm.{neon_type}"
-              arch: arm
-            - link: "llvm.aarch64.neon.fminnm.{neon_type}"
-              arch: aarch64,arm64ec
   - name: "vpadd{neon_type.no}"
     doc: Floating-point add pairwise
 @@ -7874,9 +7830,9 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [int16x8_t, int8x8_t, 'N >= 1 && N <= 8', 'const { int16x8_t([-N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16]) }']
+      - [int16x8_t, int8x8_t, 'N >= 1 && N <= 8', 'const { int16x8_t([-N as i16; 8]) }']
-      - [int32x4_t, int16x4_t, 'N >= 1 && N <= 16', 'const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }']
+      - [int32x4_t, int16x4_t, 'N >= 1 && N <= 16', 'const { int32x4_t([-N; 4]) }']
-      - [int64x2_t, int32x2_t, 'N >= 1 && N <= 32', 'const { int64x2_t([-N as i64, -N as i64]) }']
+      - [int64x2_t, int32x2_t, 'N >= 1 && N <= 32', 'const { int64x2_t([-N as i64; 2]) }']
     compose:
       - FnCall: [static_assert!, ["{type[2]}"]]
       - LLVMLink:
 @@ -7929,9 +7885,9 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [int16x8_t, uint8x8_t, 'N >= 1 && N <= 8', 'const { int16x8_t([-N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16]) }']
+      - [int16x8_t, uint8x8_t, 'N >= 1 && N <= 8', 'const { int16x8_t([-N as i16; 8]) }']
-      - [int32x4_t, uint16x4_t, 'N >= 1 && N <= 16', 'const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }']
+      - [int32x4_t, uint16x4_t, 'N >= 1 && N <= 16', 'const { int32x4_t([-N; 4]) }']
-      - [int64x2_t, uint32x2_t, 'N >= 1 && N <= 32', 'const { int64x2_t([-N as i64, -N as i64]) }']
+      - [int64x2_t, uint32x2_t, 'N >= 1 && N <= 32', 'const { int64x2_t([-N as i64; 2]) }']
     compose:
       - FnCall: [static_assert!, ["{type[2]}"]]
       - LLVMLink:
 @@ -8105,9 +8061,9 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [int16x8_t, int8x8_t, 'N >= 1 && N <= 8', 'const { int16x8_t([-N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16]) }']
+      - [int16x8_t, int8x8_t, 'N >= 1 && N <= 8', 'const { int16x8_t([-N as i16; 8]) }']
-      - [int32x4_t, int16x4_t, 'N >= 1 && N <= 16', 'const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }']
+      - [int32x4_t, int16x4_t, 'N >= 1 && N <= 16', 'const { int32x4_t([-N; 4]) }']
-      - [int64x2_t, int32x2_t, 'N >= 1 && N <= 32', 'const { int64x2_t([-N as i64, -N as i64]) }']
+      - [int64x2_t, int32x2_t, 'N >= 1 && N <= 32', 'const { int64x2_t([-N as i64; 2]) }']
     compose:
       - FnCall: [static_assert!, ["{type[2]}"]]
       - LLVMLink:
 @@ -8215,9 +8171,9 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [int16x8_t, uint8x8_t, 'N >= 1 && N <= 8', 'const { int16x8_t([-N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16]) }']
+      - [int16x8_t, uint8x8_t, 'N >= 1 && N <= 8', 'const { int16x8_t([-N as i16; 8]) }']
-      - [int32x4_t, uint16x4_t, 'N >= 1 && N <= 16', 'const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }']
+      - [int32x4_t, uint16x4_t, 'N >= 1 && N <= 16', 'const { int32x4_t([-N; 4]) }']
-      - [int64x2_t, uint32x2_t, 'N >= 1 && N <= 32', 'const { int64x2_t([-N as i64, -N as i64]) }']
+      - [int64x2_t, uint32x2_t, 'N >= 1 && N <= 32', 'const { int64x2_t([-N as i64; 2]) }']
     compose:
       - FnCall: [static_assert!, ["{type[2]}"]]
       - LLVMLink:
 @@ -8939,9 +8895,9 @@ intrinsics:
     static_defs: ['const N: i32']
     safety: safe
     types:
-      - [int16x8_t, int8x8_t, 'N >= 1 && N <= 8', 'const { int16x8_t([-N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16]) }']
+      - [int16x8_t, int8x8_t, 'N >= 1 && N <= 8', 'const { int16x8_t([-N as i16; 8]) }']
-      - [int32x4_t, int16x4_t, 'N >= 1 && N <= 16', 'const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }']
+      - [int32x4_t, int16x4_t, 'N >= 1 && N <= 16', 'const { int32x4_t([-N; 4]) }']
-      - [int64x2_t, int32x2_t, 'N >= 1 && N <= 32', 'const { int64x2_t([-N as i64, -N as i64]) }']
+      - [int64x2_t, int32x2_t, 'N >= 1 && N <= 32', 'const { int64x2_t([-N as i64; 2]) }']
     compose:
       - FnCall: [static_assert!, ["{type[2]}"]]
       - LLVMLink:
 @@ -9576,7 +9532,8 @@ intrinsics:
     attr:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vtrn]]}]]
-      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [trn]]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [trn1]]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [trn2]]}]]
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
     safety: safe
 @@ -9617,7 +9574,8 @@ intrinsics:
     attr:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vtrn]]}]]
-      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [trn]]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [trn1]]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [trn2]]}]]
       - *neon-fp16
       - *neon-unstable-f16
     safety: safe
 @@ -9645,7 +9603,8 @@ intrinsics:
     attr:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vtrn]]}]]
-      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [zip]]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [zip1]]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [zip2]]}]]
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
     safety: safe
 @@ -9673,7 +9632,8 @@ intrinsics:
     attr:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vorr]]}]]
-      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [zip]]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [zip1]]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [zip2]]}]]
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
     safety: safe
 @@ -9707,7 +9667,8 @@ intrinsics:
     attr:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vtrn]]}]]
-      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [zip]]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [zip1]]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [zip2]]}]]
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
     safety: safe
 @@ -9735,7 +9696,8 @@ intrinsics:
     attr:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vzip]]}]]
-      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [zip]]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [zip1]]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [zip2]]}]]
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
     safety: safe
 @@ -9767,7 +9729,8 @@ intrinsics:
     attr:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vzip.16"']]}]]
-      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [zip]]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [zip1]]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [zip2]]}]]
       - *neon-fp16
       - *neon-unstable-f16
     safety: safe
 @@ -9794,7 +9757,8 @@ intrinsics:
     attr:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vuzp]]}]]
-      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [uzp]]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [uzp1]]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [uzp2]]}]]
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
     safety: safe
 @@ -9835,7 +9799,8 @@ intrinsics:
     attr:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vuzp]]}]]
-      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [uzp]]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [uzp1]]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [uzp2]]}]]
       - *neon-fp16
       - *neon-unstable-f16
     safety: safe
 @@ -9863,7 +9828,8 @@ intrinsics:
     attr:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vtrn]]}]]
-      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [zip]]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [zip1]]}]]
+      - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [zip2]]}]]
       - *neon-not-arm-stable
       - *neon-cfg-arm-unstable
     safety: safe
 @@ -12881,13 +12847,16 @@ intrinsics:
       - int16x8_t
       - int32x4_t
     compose:
-      - LLVMLink:
+      - Let:
-          name: "vabs{neon_type.no}"
+          - neg
-          links:
+          - "{neon_type}"
-            - link: "llvm.aarch64.neon.abs.{neon_type}"
+          - FnCall: [simd_neg, [a]]
-              arch: aarch64,arm64ec
+      - Let:
-            - link: "llvm.arm.neon.vabs.{neon_type}"
+          - mask
-              arch: arm
+          - "{neon_type}"
+          - FnCall: [simd_ge, [a, neg]]
+      - FnCall: [simd_select, [mask, a, neg]]
   - name: "vpmin{neon_type.no}"
     doc: "Folding minimum of adjacent pairs"
 @@ -13862,8 +13831,8 @@ intrinsics:
       - [int8x16_t, '8',  '1 <= N && N <= 8',  'v16i8', 'int8x16_t::splat', '-N as i8']
       - [int16x4_t, '16', '1 <= N && N <= 16', 'v4i16', 'int16x4_t::splat', '-N as i16']
       - [int16x8_t, '16', '1 <= N && N <= 16', 'v8i16', 'int16x8_t::splat', '-N as i16']
-      - [int32x2_t, '32', '1 <= N && N <= 32', 'v2i32', 'int32x2_t::splat', '-N as i32']
+      - [int32x2_t, '32', '1 <= N && N <= 32', 'v2i32', 'int32x2_t::splat', '-N']
-      - [int32x4_t, '32', '1 <= N && N <= 32', 'v4i32', 'int32x4_t::splat', '-N as i32']
+      - [int32x4_t, '32', '1 <= N && N <= 32', 'v4i32', 'int32x4_t::splat', '-N']
       - [int64x1_t, '64', '1 <= N && N <= 64', 'v1i64', 'int64x1_t::splat', '-N as i64']
       - [int64x2_t, '64', '1 <= N && N <= 64', 'v2i64', 'int64x2_t::splat', '-N as i64']
     compose:
 @@ -13891,8 +13860,8 @@ intrinsics:
       - [uint8x16_t, "neon,v7", '8',  'static_assert_uimm_bits!', 'N, 3',    'v16i8', 'int8x16_t::splat', 'N as i8']
       - [uint16x4_t, "neon,v7", '16', 'static_assert_uimm_bits!', 'N, 4',    'v4i16', 'int16x4_t::splat', 'N as i16']
       - [uint16x8_t, "neon,v7", '16', 'static_assert_uimm_bits!', 'N, 4',    'v8i16', 'int16x8_t::splat', 'N as i16']
-      - [uint32x2_t, "neon,v7", '32', 'static_assert!', 'N >= 0 && N <= 31', 'v2i32', 'int32x2_t::splat', 'N as i32']
+      - [uint32x2_t, "neon,v7", '32', 'static_assert!', 'N >= 0 && N <= 31', 'v2i32', 'int32x2_t::splat', 'N']
-      - [uint32x4_t, "neon,v7", '32', 'static_assert!', 'N >= 0 && N <= 31', 'v4i32', 'int32x4_t::splat', 'N as i32']
+      - [uint32x4_t, "neon,v7", '32', 'static_assert!', 'N >= 0 && N <= 31', 'v4i32', 'int32x4_t::splat', 'N']
       - [uint64x1_t, "neon,v7", '64', 'static_assert!', 'N >= 0 && N <= 63', 'v1i64', 'int64x1_t::splat', 'N as i64']
       - [uint64x2_t, "neon,v7", '64', 'static_assert!', 'N >= 0 && N <= 63', 'v2i64', 'int64x2_t::splat', 'N as i64']
       - [poly8x8_t,  "neon,v7", '8',  'static_assert_uimm_bits!', 'N, 3',     'v8i8', 'int8x8_t::splat',  'N as i8']
 @@ -14138,6 +14107,7 @@ intrinsics:
     doc: "Load one single-element structure and Replicate to all lanes (of one register)."
     arguments: ["ptr: {type[1]}"]
     return_type: "{neon_type[2]}"
+    big_endian_inverse: false
     attr:
       - *neon-v7
       - FnCall: [cfg_attr, [*test-is-arm, { FnCall: [assert_instr, ['"{type[3]}"']] }  ]]
 @@ -14147,40 +14117,36 @@ intrinsics:
     safety:
       unsafe: [neon]
     types:
-      - ['vld1_dup_s8', '*const i8', 'int8x8_t', 'vld1.8', 'ld1r', 'vld1_lane_s8::<0>', 'i8x8::splat(0)', '[0, 0, 0, 0, 0, 0, 0, 0]']
+      - ['vld1_dup_s8', '*const i8', 'int8x8_t', 'vld1.8', 'ld1r', 'i8x8::splat']
-      - ['vld1_dup_u8', '*const u8', 'uint8x8_t', 'vld1.8', 'ld1r', 'vld1_lane_u8::<0>', 'u8x8::splat(0)', '[0, 0, 0, 0, 0, 0, 0, 0]']
+      - ['vld1_dup_u8', '*const u8', 'uint8x8_t', 'vld1.8', 'ld1r', 'u8x8::splat']
-      - ['vld1_dup_p8', '*const p8', 'poly8x8_t', 'vld1.8', 'ld1r', 'vld1_lane_p8::<0>', 'u8x8::splat(0)', '[0, 0, 0, 0, 0, 0, 0, 0]']
+      - ['vld1_dup_p8', '*const p8', 'poly8x8_t', 'vld1.8', 'ld1r', 'u8x8::splat']
-      - ['vld1q_dup_s8', '*const i8', 'int8x16_t', 'vld1.8', 'ld1r', 'vld1q_lane_s8::<0>', 'i8x16::splat(0)', '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]']
+      - ['vld1q_dup_s8', '*const i8', 'int8x16_t', 'vld1.8', 'ld1r', 'i8x16::splat']
-      - ['vld1q_dup_u8', '*const u8', 'uint8x16_t', 'vld1.8', 'ld1r', 'vld1q_lane_u8::<0>', 'u8x16::splat(0)', '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]']
+      - ['vld1q_dup_u8', '*const u8', 'uint8x16_t', 'vld1.8', 'ld1r', 'u8x16::splat']
-      - ['vld1q_dup_p8', '*const p8', 'poly8x16_t', 'vld1.8', 'ld1r', 'vld1q_lane_p8::<0>', 'u8x16::splat(0)', '[0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]']
+      - ['vld1q_dup_p8', '*const p8', 'poly8x16_t', 'vld1.8', 'ld1r', 'u8x16::splat']
-      - ['vld1_dup_s16', '*const i16', 'int16x4_t', 'vld1.16', 'ld1r', 'vld1_lane_s16::<0>', 'i16x4::splat(0)', '[0, 0, 0, 0]']
+      - ['vld1_dup_s16', '*const i16', 'int16x4_t', 'vld1.16', 'ld1r', 'i16x4::splat']
-      - ['vld1_dup_u16', '*const u16', 'uint16x4_t', 'vld1.16', 'ld1r', 'vld1_lane_u16::<0>', 'u16x4::splat(0)', '[0, 0, 0, 0]']
+      - ['vld1_dup_u16', '*const u16', 'uint16x4_t', 'vld1.16', 'ld1r', 'u16x4::splat']
-      - ['vld1_dup_p16', '*const p16', 'poly16x4_t', 'vld1.16', 'ld1r', 'vld1_lane_p16::<0>', 'u16x4::splat(0)', '[0, 0, 0, 0]']
+      - ['vld1_dup_p16', '*const p16', 'poly16x4_t', 'vld1.16', 'ld1r', 'u16x4::splat']
-      - ['vld1q_dup_s16', '*const i16', 'int16x8_t', 'vld1.16', 'ld1r', 'vld1q_lane_s16::<0>', 'i16x8::splat(0)', '[0, 0, 0, 0, 0, 0, 0, 0]']
+      - ['vld1q_dup_s16', '*const i16', 'int16x8_t', 'vld1.16', 'ld1r', 'i16x8::splat']
-      - ['vld1q_dup_u16', '*const u16', 'uint16x8_t', 'vld1.16', 'ld1r', 'vld1q_lane_u16::<0>', 'u16x8::splat(0)', '[0, 0, 0, 0, 0, 0, 0, 0]']
+      - ['vld1q_dup_u16', '*const u16', 'uint16x8_t', 'vld1.16', 'ld1r', 'u16x8::splat']
-      - ['vld1q_dup_p16', '*const p16', 'poly16x8_t', 'vld1.16', 'ld1r', 'vld1q_lane_p16::<0>', 'u16x8::splat(0)', '[0, 0, 0, 0, 0, 0, 0, 0]']
+      - ['vld1q_dup_p16', '*const p16', 'poly16x8_t', 'vld1.16', 'ld1r', 'u16x8::splat']
-      - ['vld1_dup_s32', '*const i32', 'int32x2_t', 'vld1.32', 'ld1r', 'vld1_lane_s32::<0>', 'i32x2::splat(0)', '[0, 0]']
+      - ['vld1_dup_s32', '*const i32', 'int32x2_t', 'vld1.32', 'ld1r', 'i32x2::splat']
-      - ['vld1_dup_u32', '*const u32', 'uint32x2_t', 'vld1.32', 'ld1r', 'vld1_lane_u32::<0>', 'u32x2::splat(0)', '[0, 0]']
+      - ['vld1_dup_u32', '*const u32', 'uint32x2_t', 'vld1.32', 'ld1r', 'u32x2::splat']
-      - ['vld1_dup_f32', '*const f32', 'float32x2_t', 'vld1.32', 'ld1r', 'vld1_lane_f32::<0>', 'f32x2::splat(0.0)', '[0, 0]']
+      - ['vld1_dup_f32', '*const f32', 'float32x2_t', 'vld1.32', 'ld1r', 'f32x2::splat']
-      - ['vld1q_dup_s32', '*const i32', 'int32x4_t', 'vld1.32', 'ld1r', 'vld1q_lane_s32::<0>', 'i32x4::splat(0)', '[0, 0, 0, 0]']
+      - ['vld1q_dup_s32', '*const i32', 'int32x4_t', 'vld1.32', 'ld1r', 'i32x4::splat']
-      - ['vld1q_dup_u32', '*const u32', 'uint32x4_t', 'vld1.32', 'ld1r', 'vld1q_lane_u32::<0>', 'u32x4::splat(0)', '[0, 0, 0, 0]']
+      - ['vld1q_dup_u32', '*const u32', 'uint32x4_t', 'vld1.32', 'ld1r', 'u32x4::splat']
-      - ['vld1q_dup_f32', '*const f32', 'float32x4_t', 'vld1.32', 'ld1r', 'vld1q_lane_f32::<0>', 'f32x4::splat(0.0)', '[0, 0, 0, 0]']
+      - ['vld1q_dup_f32', '*const f32', 'float32x4_t', 'vld1.32', 'ld1r', 'f32x4::splat']
-      - ['vld1q_dup_s64', '*const i64', 'int64x2_t', 'vldr', 'ld1', 'vld1q_lane_s64::<0>', 'i64x2::splat(0)', '[0, 0]']
+      - ['vld1q_dup_s64', '*const i64', 'int64x2_t', 'vldr', 'ld1r', 'i64x2::splat']
-      - ['vld1q_dup_u64', '*const u64', 'uint64x2_t', 'vldr', 'ld1', 'vld1q_lane_u64::<0>', 'u64x2::splat(0)', '[0, 0]']
+      - ['vld1q_dup_u64', '*const u64', 'uint64x2_t', 'vldr', 'ld1r', 'u64x2::splat']
     compose:
-      - Let:
+      - FnCall:
-          - x
+          - transmute
-          - FnCall:
+          - - FnCall: ['{type[5]}', ["*ptr"]]
-              - '{type[5]}'
-              - - ptr
-                - FnCall: [transmute, ['{type[6]}']]
-      - FnCall: ['simd_shuffle!', [x, x, '{type[7]}']]
   - name: "{type[0]}"
     doc: "Absolute difference and accumulate (64-bit)"

library/stdarch/crates/stdarch-gen-arm/src/expression.rs+3-5

...	@@ -1,5 +1,4 @@	...	@@ -1,5 +1,4 @@
1	use itertools::Itertools;	1	use itertools::Itertools;
2	use lazy_static::lazy_static;
3	use proc_macro2::{Literal, Punct, Spacing, TokenStream};	2	use proc_macro2::{Literal, Punct, Spacing, TokenStream};
4	use quote::{ToTokens, TokenStreamExt, format_ident, quote};	3	use quote::{ToTokens, TokenStreamExt, format_ident, quote};
5	use regex::Regex;	4	use regex::Regex;
...	@@ -7,6 +6,7 @@ use serde::de::{self, MapAccess, Visitor};	...	@@ -7,6 +6,7 @@ use serde::de::{self, MapAccess, Visitor};
7	use serde::{Deserialize, Deserializer, Serialize};	6	use serde::{Deserialize, Deserializer, Serialize};
8	use std::fmt;	7	use std::fmt;
9	use std::str::FromStr;	8	use std::str::FromStr;
		9	use std::sync::LazyLock;
10		10
11	use crate::intrinsic::Intrinsic;	11	use crate::intrinsic::Intrinsic;
12	use crate::wildstring::WildStringPart;	12	use crate::wildstring::WildStringPart;
...	@@ -374,10 +374,8 @@ impl FromStr for Expression {	...	@@ -374,10 +374,8 @@ impl FromStr for Expression {
374	type Err = String;	374	type Err = String;
375		375
376	fn from_str(s: &str) -> Result<Self, Self::Err> {	376	fn from_str(s: &str) -> Result<Self, Self::Err> {
377	lazy_static! {	377	static MACRO_RE: LazyLock<Regex> =
378	static ref MACRO_RE: Regex =	378	LazyLock::new(\|\| Regex::new(r"^(?P<name>[\w\d_]+)!$(?P<ex>.*?)$;?$").unwrap());
379	Regex::new(r"^(?P<name>[\w\d_]+)!$(?P<ex>.*?)$;?$").unwrap();
380	}
381		379
382	if s == "SvUndef" {	380	if s == "SvUndef" {
383	Ok(Expression::SvUndef)	381	Ok(Expression::SvUndef)

library/stdarch/crates/stdarch-gen-arm/src/load_store_tests.rs+8-12

...	@@ -2,6 +2,7 @@ use std::fs::File;	...	@@ -2,6 +2,7 @@ use std::fs::File;
2	use std::io::Write;	2	use std::io::Write;
3	use std::path::PathBuf;	3	use std::path::PathBuf;
4	use std::str::FromStr;	4	use std::str::FromStr;
		5	use std::sync::LazyLock;
5		6
6	use crate::format_code;	7	use crate::format_code;
7	use crate::input::InputType;	8	use crate::input::InputType;
...	@@ -10,7 +11,6 @@ use crate::typekinds::BaseType;	...	@@ -10,7 +11,6 @@ use crate::typekinds::BaseType;
10	use crate::typekinds::{ToRepr, TypeKind};	11	use crate::typekinds::{ToRepr, TypeKind};
11		12
12	use itertools::Itertools;	13	use itertools::Itertools;
13	use lazy_static::lazy_static;
14	use proc_macro2::TokenStream;	14	use proc_macro2::TokenStream;
15	use quote::{format_ident, quote};	15	use quote::{format_ident, quote};
16		16
...	@@ -639,8 +639,8 @@ impl LdIntrCharacteristics {	...	@@ -639,8 +639,8 @@ impl LdIntrCharacteristics {
639	}	639	}
640	}	640	}
641		641
642	lazy_static! {	642	static PREAMBLE: LazyLock<String> = LazyLock::new(\|\| {
643	static ref PREAMBLE: String = format!(	643	format!(
644	r#"#![allow(unused)]	644	r#"#![allow(unused)]
645		645
646	use super::*;	646	use super::*;
...	@@ -801,13 +801,11 @@ fn assert_vector_matches_u64(vector: svuint64_t, expected: svuint64_t) {{	...	@@ -801,13 +801,11 @@ fn assert_vector_matches_u64(vector: svuint64_t, expected: svuint64_t) {{
801	assert!(!svptest_any(defined, cmp))	801	assert!(!svptest_any(defined, cmp))
802	}}	802	}}
803	"#	803	"#
804	);	804	)
805	}	805	});
806		806
807	lazy_static! {	807	const MANUAL_TESTS: &str = "#[simd_test(enable = \"sve\")]
808	static ref MANUAL_TESTS: String = format!(	808	unsafe fn test_ffr() {
809	"#[simd_test(enable = \"sve\")]
810	unsafe fn test_ffr() {{
811	svsetffr();	809	svsetffr();
812	let ffr = svrdffr();	810	let ffr = svrdffr();
813	assert_vector_matches_u8(svdup_n_u8_z(ffr, 1), svindex_u8(1, 0));	811	assert_vector_matches_u8(svdup_n_u8_z(ffr, 1), svindex_u8(1, 0));
...	@@ -816,7 +814,5 @@ unsafe fn test_ffr() {{	...	@@ -816,7 +814,5 @@ unsafe fn test_ffr() {{
816	svwrffr(pred);	814	svwrffr(pred);
817	let ffr = svrdffr_z(svptrue_b8());	815	let ffr = svrdffr_z(svptrue_b8());
818	assert_vector_matches_u8(svdup_n_u8_z(ffr, 1), svdup_n_u8_z(pred, 1));	816	assert_vector_matches_u8(svdup_n_u8_z(ffr, 1), svdup_n_u8_z(pred, 1));
819	}}
820	"
821	);
822	}	817	}
		818	";

library/stdarch/crates/stdarch-gen-arm/src/typekinds.rs+6-7

 @@ -1,10 +1,10 @@
-use lazy_static::lazy_static;
 use proc_macro2::TokenStream;
 use quote::{ToTokens, TokenStreamExt, quote};
 use regex::Regex;
 use serde_with::{DeserializeFromStr, SerializeDisplay};
 use std::fmt;
 use std::str::FromStr;
+use std::sync::LazyLock;
 use crate::context;
 use crate::expression::{Expression, FnCall};
 @@ -496,9 +496,9 @@ impl FromStr for VectorType {
     type Err = String;
     fn from_str(s: &str) -> Result<Self, Self::Err> {
-        lazy_static! {
+        static RE: LazyLock<Regex> = LazyLock::new(|| {
-            static ref RE: Regex = Regex::new(r"^(?:(?:sv(?P<sv_ty>(?:uint|int|bool|float)(?:\d+)?))|(?:(?P<ty>(?:uint|int|bool|poly|float)(?:\d+)?)x(?P<lanes>(?:\d+)?)))(?:x(?P<tuple_size>2|3|4))?_t$").unwrap();
+            Regex::new(r"^(?:(?:sv(?P<sv_ty>(?:uint|int|bool|float)(?:\d+)?))|(?:(?P<ty>(?:uint|int|bool|poly|float)(?:\d+)?)x(?P<lanes>(?:\d+)?)))(?:x(?P<tuple_size>2|3|4))?_t$").unwrap()
-        }
+        });
         if let Some(c) = RE.captures(s) {
             let (base_type, lanes) = Self::sanitise_lanes(
 @@ -698,9 +698,8 @@ impl FromStr for BaseType {
     type Err = String;
     fn from_str(s: &str) -> Result<Self, Self::Err> {
-        lazy_static! {
+        static RE: LazyLock<Regex> =
-            static ref RE: Regex = Regex::new(r"^(?P<kind>[a-zA-Z]+)(?P<size>\d+)?(_t)?$").unwrap();
+            LazyLock::new(|| Regex::new(r"^(?P<kind>[a-zA-Z]+)(?P<size>\d+)?(_t)?$").unwrap());
-        }
         if let Some(c) = RE.captures(s) {
             let kind = c["kind"].parse()?;

library/stdarch/crates/stdarch-gen-arm/src/wildcards.rs+4-5

 @@ -1,8 +1,7 @@
-use lazy_static::lazy_static;
 use regex::Regex;
 use serde_with::{DeserializeFromStr, SerializeDisplay};
-use std::fmt;
 use std::str::FromStr;
+use std::{fmt, sync::LazyLock};
 use crate::{
     fn_suffix::SuffixKind,
 @@ -66,9 +65,9 @@ impl FromStr for Wildcard {
     type Err = String;
     fn from_str(s: &str) -> Result<Self, Self::Err> {
-        lazy_static! {
+        static RE: LazyLock<Regex> = LazyLock::new(|| {
-            static ref RE: Regex = Regex::new(r"^(?P<wildcard>\w+?)(?:_x(?P<tuple_size>[2-4]))?(?:\[(?P<index>\d+)\])?(?:\.(?P<modifiers>\w+))?(?:\s+as\s+(?P<scale_to>.*?))?$").unwrap();
+            Regex::new(r"^(?P<wildcard>\w+?)(?:_x(?P<tuple_size>[2-4]))?(?:\[(?P<index>\d+)\])?(?:\.(?P<modifiers>\w+))?(?:\s+as\s+(?P<scale_to>.*?))?$").unwrap()
-        }
+        });
         if let Some(c) = RE.captures(s) {
             let wildcard_name = &c["wildcard"];

library/stdarch/crates/stdarch-gen-loongarch/README.md-2

...	@@ -11,7 +11,6 @@ LSX:	...	@@ -11,7 +11,6 @@ LSX:
11	# Generate bindings	11	# Generate bindings
12	OUT_DIR=`pwd`/crates/stdarch-gen-loongarch cargo run -p stdarch-gen-loongarch -- crates/stdarch-gen-loongarch/lsxintrin.h	12	OUT_DIR=`pwd`/crates/stdarch-gen-loongarch cargo run -p stdarch-gen-loongarch -- crates/stdarch-gen-loongarch/lsxintrin.h
13	OUT_DIR=`pwd`/crates/core_arch cargo run -p stdarch-gen-loongarch -- crates/stdarch-gen-loongarch/lsx.spec	13	OUT_DIR=`pwd`/crates/core_arch cargo run -p stdarch-gen-loongarch -- crates/stdarch-gen-loongarch/lsx.spec
14	rustfmt crates/core_arch/src/loongarch64/lsx/generated.rs
15		14
16	# Generate tests	15	# Generate tests
17	OUT_DIR=`pwd`/crates/stdarch-gen-loongarch cargo run -p stdarch-gen-loongarch -- crates/stdarch-gen-loongarch/lsx.spec test	16	OUT_DIR=`pwd`/crates/stdarch-gen-loongarch cargo run -p stdarch-gen-loongarch -- crates/stdarch-gen-loongarch/lsx.spec test
...	@@ -25,7 +24,6 @@ LASX:	...	@@ -25,7 +24,6 @@ LASX:
25	# Generate bindings	24	# Generate bindings
26	OUT_DIR=`pwd`/crates/stdarch-gen-loongarch cargo run -p stdarch-gen-loongarch -- crates/stdarch-gen-loongarch/lasxintrin.h	25	OUT_DIR=`pwd`/crates/stdarch-gen-loongarch cargo run -p stdarch-gen-loongarch -- crates/stdarch-gen-loongarch/lasxintrin.h
27	OUT_DIR=`pwd`/crates/core_arch cargo run -p stdarch-gen-loongarch -- crates/stdarch-gen-loongarch/lasx.spec	26	OUT_DIR=`pwd`/crates/core_arch cargo run -p stdarch-gen-loongarch -- crates/stdarch-gen-loongarch/lasx.spec
28	rustfmt crates/core_arch/src/loongarch64/lasx/generated.rs
29		27
30	# Generate tests	28	# Generate tests
31	OUT_DIR=`pwd`/crates/stdarch-gen-loongarch cargo run -p stdarch-gen-loongarch -- crates/stdarch-gen-loongarch/lasx.spec test	29	OUT_DIR=`pwd`/crates/stdarch-gen-loongarch cargo run -p stdarch-gen-loongarch -- crates/stdarch-gen-loongarch/lasx.spec test

library/stdarch/crates/stdarch-gen-loongarch/src/main.rs+29-17

 @@ -274,13 +274,14 @@ fn gen_bind_body(
         }
     };
+    let is_mem = in_t.iter().any(|s| s.contains("POINTER"));
     let is_store = current_name.to_string().contains("vst");
     let link_function = {
         let fn_decl = {
             let fn_output = if out_t.to_lowercase() == "void" {
                 String::new()
             } else {
-                format!("-> {}", type_to_rst(out_t, is_store))
+                format!(" -> {}", type_to_rst(out_t, is_store))
             };
             let fn_inputs = match para_num {
                 1 => format!("(a: {})", type_to_rst(in_t[0], is_store)),
 @@ -304,7 +305,7 @@ fn gen_bind_body(
                 ),
                 _ => panic!("unsupported parameter number"),
             };
-            format!("fn __{current_name}{fn_inputs} {fn_output};")
+            format!("fn __{current_name}{fn_inputs}{fn_output};")
         };
         let function = format!(
             r#"    #[link_name = "llvm.loongarch.{}"]
 @@ -456,31 +457,40 @@ fn gen_bind_body(
             };
             rustc_legacy_const_generics = "rustc_legacy_const_generics(2, 3)";
         }
-        format!("pub unsafe fn {current_name}{fn_inputs} {fn_output}")
+        format!(
+            "pub {}fn {current_name}{fn_inputs} {fn_output}",
+            if is_mem { "unsafe " } else { "" }
+        )
     };
+    let unsafe_start = if !is_mem { "unsafe { " } else { "" };
+    let unsafe_end = if !is_mem { " }" } else { "" };
     let mut call_params = {
         match para_num {
-            1 => format!("__{current_name}(a)"),
+            1 => format!("{unsafe_start}__{current_name}(a){unsafe_end}"),
-            2 => format!("__{current_name}(a, b)"),
+            2 => format!("{unsafe_start}__{current_name}(a, b){unsafe_end}"),
-            3 => format!("__{current_name}(a, b, c)"),
+            3 => format!("{unsafe_start}__{current_name}(a, b, c){unsafe_end}"),
-            4 => format!("__{current_name}(a, b, c, d)"),
+            4 => format!("{unsafe_start}__{current_name}(a, b, c, d){unsafe_end}"),
             _ => panic!("unsupported parameter number"),
         }
     };
     if para_num == 1 && in_t[0] == "HI" {
         call_params = match asm_fmts[1].as_str() {
             "si10" => {
-                format!("static_assert_simm_bits!(IMM_S10, 10);\n    __{current_name}(IMM_S10)")
+                format!(
+                    "static_assert_simm_bits!(IMM_S10, 10);\n    {unsafe_start}__{current_name}(IMM_S10){unsafe_end}"
+                )
             }
             "i13" => {
-                format!("static_assert_simm_bits!(IMM_S13, 13);\n    __{current_name}(IMM_S13)")
+                format!(
+                    "static_assert_simm_bits!(IMM_S13, 13);\n    {unsafe_start}__{current_name}(IMM_S13){unsafe_end}"
+                )
             }
             _ => panic!("unsupported assembly format: {}", asm_fmts[2]),
         }
     } else if para_num == 2 && (in_t[1] == "UQI" || in_t[1] == "USI") {
         call_params = if asm_fmts[2].starts_with("ui") {
             format!(
-                "static_assert_uimm_bits!(IMM{0}, {0});\n    __{current_name}(a, IMM{0})",
+                "static_assert_uimm_bits!(IMM{0}, {0});\n    {unsafe_start}__{current_name}(a, IMM{0}){unsafe_end}",
                 asm_fmts[2].get(2..).unwrap()
             )
         } else {
 @@ -489,14 +499,16 @@ fn gen_bind_body(
     } else if para_num == 2 && in_t[1] == "QI" {
         call_params = match asm_fmts[2].as_str() {
             "si5" => {
-                format!("static_assert_simm_bits!(IMM_S5, 5);\n    __{current_name}(a, IMM_S5)")
+                format!(
+                    "static_assert_simm_bits!(IMM_S5, 5);\n    {unsafe_start}__{current_name}(a, IMM_S5){unsafe_end}"
+                )
             }
             _ => panic!("unsupported assembly format: {}", asm_fmts[2]),
         };
     } else if para_num == 2 && in_t[0] == "CVPOINTER" && in_t[1] == "SI" {
         call_params = if asm_fmts[2].starts_with("si") {
             format!(
-                "static_assert_simm_bits!(IMM_S{0}, {0});\n    __{current_name}(mem_addr, IMM_S{0})",
+                "static_assert_simm_bits!(IMM_S{0}, {0});\n    {unsafe_start}__{current_name}(mem_addr, IMM_S{0}){unsafe_end}",
                 asm_fmts[2].get(2..).unwrap()
             )
         } else {
 @@ -504,13 +516,13 @@ fn gen_bind_body(
         }
     } else if para_num == 2 && in_t[0] == "CVPOINTER" && in_t[1] == "DI" {
         call_params = match asm_fmts[2].as_str() {
-            "rk" => format!("__{current_name}(mem_addr, b)"),
+            "rk" => format!("{unsafe_start}__{current_name}(mem_addr, b){unsafe_end}"),
             _ => panic!("unsupported assembly format: {}", asm_fmts[2]),
         };
     } else if para_num == 3 && (in_t[2] == "USI" || in_t[2] == "UQI") {
         call_params = if asm_fmts[2].starts_with("ui") {
             format!(
-                "static_assert_uimm_bits!(IMM{0}, {0});\n    __{current_name}(a, b, IMM{0})",
+                "static_assert_uimm_bits!(IMM{0}, {0});\n    {unsafe_start}__{current_name}(a, b, IMM{0}){unsafe_end}",
                 asm_fmts[2].get(2..).unwrap()
             )
         } else {
 @@ -519,19 +531,19 @@ fn gen_bind_body(
     } else if para_num == 3 && in_t[1] == "CVPOINTER" && in_t[2] == "SI" {
         call_params = match asm_fmts[2].as_str() {
             "si12" => format!(
-                "static_assert_simm_bits!(IMM_S12, 12);\n    __{current_name}(a, mem_addr, IMM_S12)"
+                "static_assert_simm_bits!(IMM_S12, 12);\n    {unsafe_start}__{current_name}(a, mem_addr, IMM_S12){unsafe_end}"
             ),
             _ => panic!("unsupported assembly format: {}", asm_fmts[2]),
         };
     } else if para_num == 3 && in_t[1] == "CVPOINTER" && in_t[2] == "DI" {
         call_params = match asm_fmts[2].as_str() {
-            "rk" => format!("__{current_name}(a, mem_addr, b)"),
+            "rk" => format!("{unsafe_start}__{current_name}(a, mem_addr, b){unsafe_end}"),
             _ => panic!("unsupported assembly format: {}", asm_fmts[2]),
         };
     } else if para_num == 4 {
         call_params = match (asm_fmts[2].as_str(), current_name.chars().last().unwrap()) {
             ("si8", t) => format!(
-                "static_assert_simm_bits!(IMM_S8, 8);\n    static_assert_uimm_bits!(IMM{0}, {0});\n    __{current_name}(a, mem_addr, IMM_S8, IMM{0})",
+                "static_assert_simm_bits!(IMM_S8, 8);\n    static_assert_uimm_bits!(IMM{0}, {0});\n    {unsafe_start}__{current_name}(a, mem_addr, IMM_S8, IMM{0}){unsafe_end}",
                 type_to_imm(t)
             ),
             (_, _) => panic!(

library/stdarch/crates/stdarch-test/Cargo.toml+1-2

...	@@ -7,7 +7,6 @@ edition = "2024"	...	@@ -7,7 +7,6 @@ edition = "2024"
7	[dependencies]	7	[dependencies]
8	assert-instr-macro = { path = "../assert-instr-macro" }	8	assert-instr-macro = { path = "../assert-instr-macro" }
9	simd-test-macro = { path = "../simd-test-macro" }	9	simd-test-macro = { path = "../simd-test-macro" }
10	lazy_static = "1.0"
11	rustc-demangle = "0.1.8"	10	rustc-demangle = "0.1.8"
12	cfg-if = "1.0"	11	cfg-if = "1.0"
13		12
...	@@ -20,7 +19,7 @@ cc = "1.0"	...	@@ -20,7 +19,7 @@ cc = "1.0"
20	# time, and we want to make updates to this explicit rather than automatically	19	# time, and we want to make updates to this explicit rather than automatically
21	# picking up updates which might break CI with new instruction names.	20	# picking up updates which might break CI with new instruction names.
22	[target.'cfg(target_arch = "wasm32")'.dependencies]	21	[target.'cfg(target_arch = "wasm32")'.dependencies]
23	wasmprinter = "=0.2.67"	22	wasmprinter = "=0.235"
24		23
25	[features]	24	[features]
26	default = []	25	default = []

library/stdarch/crates/stdarch-test/src/lib.rs+25-14

...	@@ -6,14 +6,12 @@	...	@@ -6,14 +6,12 @@
6	#![deny(rust_2018_idioms)]	6	#![deny(rust_2018_idioms)]
7	#![allow(clippy::missing_docs_in_private_items, clippy::print_stdout)]	7	#![allow(clippy::missing_docs_in_private_items, clippy::print_stdout)]
8		8
9	#[macro_use]
10	extern crate lazy_static;
11	#[macro_use]	9	#[macro_use]
12	extern crate cfg_if;	10	extern crate cfg_if;
13		11
14	pub use assert_instr_macro::*;	12	pub use assert_instr_macro::*;
15	pub use simd_test_macro::*;	13	pub use simd_test_macro::*;
16	use std::{cmp, collections::HashSet, env, hash, hint::black_box, str};	14	use std::{cmp, collections::HashSet, env, hash, hint::black_box, str, sync::LazyLock};
17		15
18	cfg_if! {	16	cfg_if! {
19	if #[cfg(target_arch = "wasm32")] {	17	if #[cfg(target_arch = "wasm32")] {
...	@@ -25,9 +23,7 @@ cfg_if! {	...	@@ -25,9 +23,7 @@ cfg_if! {
25	}	23	}
26	}	24	}
27		25
28	lazy_static! {	26	static DISASSEMBLY: LazyLock<HashSet<Function>> = LazyLock::new(disassemble_myself);
29	static ref DISASSEMBLY: HashSet<Function> = disassemble_myself();
30	}
31		27
32	#[derive(Debug)]	28	#[derive(Debug)]
33	struct Function {	29	struct Function {
...	@@ -65,11 +61,12 @@ pub fn assert(shim_addr: usize, fnname: &str, expected: &str) {	...	@@ -65,11 +61,12 @@ pub fn assert(shim_addr: usize, fnname: &str, expected: &str) {
65	black_box(shim_addr);	61	black_box(shim_addr);
66		62
67	//eprintln!("shim name: {fnname}");	63	//eprintln!("shim name: {fnname}");
68	let function = &DISASSEMBLY	64	let Some(function) = &DISASSEMBLY.get(&Function::new(fnname)) else {
69	.get(&Function::new(fnname))	65	panic!("function `{fnname}` not found in the disassembly")
70	.unwrap_or_else(\|\| panic!("function \"{fnname}\" not found in the disassembly"));	66	};
71	//eprintln!(" function: {:?}", function);	67	//eprintln!(" function: {:?}", function);
72		68
		69	// Trim any filler instructions.
73	let mut instrs = &function.instrs[..];	70	let mut instrs = &function.instrs[..];
74	while instrs.last().is_some_and(\|s\| s == "nop" \|\| s == "int3") {	71	while instrs.last().is_some_and(\|s\| s == "nop" \|\| s == "int3") {
75	instrs = &instrs[..instrs.len() - 1];	72	instrs = &instrs[..instrs.len() - 1];
...	@@ -84,12 +81,26 @@ pub fn assert(shim_addr: usize, fnname: &str, expected: &str) {	...	@@ -84,12 +81,26 @@ pub fn assert(shim_addr: usize, fnname: &str, expected: &str) {
84	// 2. It is a mark, indicating that the instruction will be	81	// 2. It is a mark, indicating that the instruction will be
85	// compiled into other instructions - mainly because of llvm	82	// compiled into other instructions - mainly because of llvm
86	// optimization.	83	// optimization.
87	let expected = if expected == "unknown" {	84	let expected = match expected {
88	"<unknown>" // Workaround for rust-lang/stdarch#1674, todo: remove when the issue is fixed	85	// `<unknown>` is what LLVM will generate for unknown instructions. We use this to fail
89	} else {	86	// loudly when LLVM does start supporting these instructions.
90	expected	87	//
		88	// This was introduced in https://github.com/rust-lang/stdarch/pull/1674 to work around the
		89	// RISC-V P extension not yet being supported.
		90	"unknown" => "<unknown>",
		91	_ => expected,
91	};	92	};
92	let found = expected == "nop" \|\| instrs.iter().any(\|s\| s.starts_with(expected));	93
		94	// Check whether the given instruction is part of the disassemblied body.
		95	let found = expected == "nop"
		96	\|\| instrs.iter().any(\|instruction\| {
		97	instruction.starts_with(expected)
		98	// Check that the next character is non-alphanumeric. This prevents false negatives
		99	// when e.g. `fminnm` was used but `fmin` was expected.
		100	//
		101	// TODO: resolve the conflicts (x86_64 and aarch64 have a bunch, probably others)
		102	// && !instruction[expected.len()..].starts_with(\|c: char\| c.is_ascii_alphanumeric())
		103	});
93		104
94	// Look for subroutine call instructions in the disassembly to detect whether	105	// Look for subroutine call instructions in the disassembly to detect whether
95	// inlining failed: all intrinsics are `#[inline(always)]`, so calling one	106	// inlining failed: all intrinsics are `#[inline(always)]`, so calling one

library/stdarch/examples/connect5.rs+12-25

 @@ -558,7 +558,8 @@ fn search(pos: &Pos, alpha: i32, beta: i32, depth: i32, _ply: i32) -> i32 {
     assert_ne!(bm, MOVE_NONE);
     assert!(bs >= -EVAL_INF && bs <= EVAL_INF);
-    if _ply == 0 { bm } else { bs } //best move at the root node, best score elsewhere
+    // best move at the root node, best score elsewhere
+    if _ply == 0 { bm } else { bs }
 }
 /// Evaluation function: give different scores to different patterns after a fixed depth.
 @@ -570,15 +571,11 @@ fn eval(pos: &Pos, _ply: i32) -> i32 {
     #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
     {
         if check_x86_avx512_features() {
-            unsafe {
+            if unsafe { check_patternlive4_avx512(pos, def) } {
-                if check_patternlive4_avx512(pos, def) {
-                    return -4096;
-                }
-            }
-        } else {
-            if check_patternlive4(pos, def) {
                 return -4096;
             }
+        } else if check_patternlive4(pos, def) {
+            return -4096;
         }
     }
 @@ -593,15 +590,11 @@ fn eval(pos: &Pos, _ply: i32) -> i32 {
     #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
     {
         if check_x86_avx512_features() {
-            unsafe {
+            if unsafe { check_patternlive4_avx512(pos, atk) } {
-                if check_patternlive4_avx512(pos, atk) {
-                    return 2560;
-                }
-            }
-        } else {
-            if check_patternlive4(pos, atk) {
                 return 2560;
             }
+        } else if check_patternlive4(pos, atk) {
+            return 2560;
         }
     }
 @@ -616,15 +609,11 @@ fn eval(pos: &Pos, _ply: i32) -> i32 {
     #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
     {
         if check_x86_avx512_features() {
-            unsafe {
+            if unsafe { check_patterndead4_avx512(pos, atk) > 0 } {
-                if check_patterndead4_avx512(pos, atk) > 0 {
-                    return 2560;
-                }
-            }
-        } else {
-            if check_patterndead4(pos, atk) > 0 {
                 return 2560;
             }
+        } else if check_patterndead4(pos, atk) > 0 {
+            return 2560;
         }
     }
 @@ -909,9 +898,7 @@ fn pos_is_winner_avx512(pos: &Pos) -> bool {
                                         0b00_10_10_10_10_11_10_10_10_10_11_11_11_11_11_10];
     let mut count_match: i32 = 0;
-    for dir in 0..2 {
+    for mut board0 in board0org {
-        // direction 0 and 1
-        let mut board0 = board0org[dir];
         let boardf = _mm512_and_si512(answer, board0);
         let temp_mask = _mm512_mask_cmpeq_epi16_mask(answer_mask[0], answer, boardf);
         count_match += _popcnt32(temp_mask as i32);

library/stdarch/triagebot.toml+1-1

...	@@ -1,7 +1,7 @@	...	@@ -1,7 +1,7 @@
1	[assign]	1	[assign]
2		2
3	[assign.owners]	3	[assign.owners]
4	"*" = ["@Amanieu"]	4	"*" = ["@Amanieu", "@folkertdev", "@sayantn"]
5		5
6	[ping.windows]	6	[ping.windows]
7	message = """\	7	message = """\

...	@@ -144,21 +144,21 @@ case ${TARGET} in	...	@@ -144,21 +144,21 @@ case ${TARGET} in
144	aarch64-unknown-linux-gnu*)	144	aarch64-unknown-linux-gnu*)
145	TEST_CPPFLAGS="-fuse-ld=lld -I/usr/aarch64-linux-gnu/include/ -I/usr/aarch64-linux-gnu/include/c++/9/aarch64-linux-gnu/"	145	TEST_CPPFLAGS="-fuse-ld=lld -I/usr/aarch64-linux-gnu/include/ -I/usr/aarch64-linux-gnu/include/c++/9/aarch64-linux-gnu/"
146	TEST_SKIP_INTRINSICS=crates/intrinsic-test/missing_aarch64.txt	146	TEST_SKIP_INTRINSICS=crates/intrinsic-test/missing_aarch64.txt
147	TEST_CXX_COMPILER="clang++-19"	147	TEST_CXX_COMPILER="clang++"
148	TEST_RUNNER="${CARGO_TARGET_AARCH64_UNKNOWN_LINUX_GNU_RUNNER}"	148	TEST_RUNNER="${CARGO_TARGET_AARCH64_UNKNOWN_LINUX_GNU_RUNNER}"
149	;;	149	;;
150		150
151	aarch64_be-unknown-linux-gnu*)	151	aarch64_be-unknown-linux-gnu*)
152	TEST_CPPFLAGS="-fuse-ld=lld"	152	TEST_CPPFLAGS="-fuse-ld=lld"
153	TEST_SKIP_INTRINSICS=crates/intrinsic-test/missing_aarch64.txt	153	TEST_SKIP_INTRINSICS=crates/intrinsic-test/missing_aarch64.txt
154	TEST_CXX_COMPILER="clang++-19"	154	TEST_CXX_COMPILER="clang++"
155	TEST_RUNNER="${CARGO_TARGET_AARCH64_BE_UNKNOWN_LINUX_GNU_RUNNER}"	155	TEST_RUNNER="${CARGO_TARGET_AARCH64_BE_UNKNOWN_LINUX_GNU_RUNNER}"
156	;;	156	;;
157		157
158	armv7-unknown-linux-gnueabihf*)	158	armv7-unknown-linux-gnueabihf*)
159	TEST_CPPFLAGS="-fuse-ld=lld -I/usr/arm-linux-gnueabihf/include/ -I/usr/arm-linux-gnueabihf/include/c++/9/arm-linux-gnueabihf/"	159	TEST_CPPFLAGS="-fuse-ld=lld -I/usr/arm-linux-gnueabihf/include/ -I/usr/arm-linux-gnueabihf/include/c++/9/arm-linux-gnueabihf/"
160	TEST_SKIP_INTRINSICS=crates/intrinsic-test/missing_arm.txt	160	TEST_SKIP_INTRINSICS=crates/intrinsic-test/missing_arm.txt
161	TEST_CXX_COMPILER="clang++-19"	161	TEST_CXX_COMPILER="clang++"
162	TEST_RUNNER="${CARGO_TARGET_ARMV7_UNKNOWN_LINUX_GNUEABIHF_RUNNER}"	162	TEST_RUNNER="${CARGO_TARGET_ARMV7_UNKNOWN_LINUX_GNUEABIHF_RUNNER}"
163	;;	163	;;
164	*)	164	*)

...	@@ -1495,3501 +1495,3501 @@ unsafe extern "unadjusted" {	...	@@ -1495,3501 +1495,3501 @@ unsafe extern "unadjusted" {
1495	#[inline]	1495	#[inline]
1496	#[target_feature(enable = "lasx")]	1496	#[target_feature(enable = "lasx")]
1497	#[unstable(feature = "stdarch_loongarch", issue = "117427")]	1497	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
1498	pub unsafe fn lasx_xvsll_b(a: v32i8, b: v32i8) -> v32i8 {	1498	pub fn lasx_xvsll_b(a: v32i8, b: v32i8) -> v32i8 {
1499	__lasx_xvsll_b(a, b)	1499	unsafe { __lasx_xvsll_b(a, b) }
1500	}	1500	}
1501		1501
1502	#[inline]	1502	#[inline]
1503	#[target_feature(enable = "lasx")]	1503	#[target_feature(enable = "lasx")]
1504	#[unstable(feature = "stdarch_loongarch", issue = "117427")]	1504	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
1505	pub unsafe fn lasx_xvsll_h(a: v16i16, b: v16i16) -> v16i16 {	1505	pub fn lasx_xvsll_h(a: v16i16, b: v16i16) -> v16i16 {
1506	__lasx_xvsll_h(a, b)	1506	unsafe { __lasx_xvsll_h(a, b) }
1507	}	1507	}
1508		1508
1509	#[inline]	1509	#[inline]
1510	#[target_feature(enable = "lasx")]	1510	#[target_feature(enable = "lasx")]
1511	#[unstable(feature = "stdarch_loongarch", issue = "117427")]	1511	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
1512	pub unsafe fn lasx_xvsll_w(a: v8i32, b: v8i32) -> v8i32 {	1512	pub fn lasx_xvsll_w(a: v8i32, b: v8i32) -> v8i32 {
1513	__lasx_xvsll_w(a, b)	1513	unsafe { __lasx_xvsll_w(a, b) }
1514	}	1514	}
1515		1515
1516	#[inline]	1516	#[inline]
1517	#[target_feature(enable = "lasx")]	1517	#[target_feature(enable = "lasx")]
1518	#[unstable(feature = "stdarch_loongarch", issue = "117427")]	1518	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
1519	pub unsafe fn lasx_xvsll_d(a: v4i64, b: v4i64) -> v4i64 {	1519	pub fn lasx_xvsll_d(a: v4i64, b: v4i64) -> v4i64 {
1520	__lasx_xvsll_d(a, b)	1520	unsafe { __lasx_xvsll_d(a, b) }
1521	}	1521	}
1522		1522
1523	#[inline]	1523	#[inline]
1524	#[target_feature(enable = "lasx")]	1524	#[target_feature(enable = "lasx")]
1525	#[rustc_legacy_const_generics(1)]	1525	#[rustc_legacy_const_generics(1)]
1526	#[unstable(feature = "stdarch_loongarch", issue = "117427")]	1526	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
1527	pub unsafe fn lasx_xvslli_b<const IMM3: u32>(a: v32i8) -> v32i8 {	1527	pub fn lasx_xvslli_b<const IMM3: u32>(a: v32i8) -> v32i8 {
1528	static_assert_uimm_bits!(IMM3, 3);	1528	static_assert_uimm_bits!(IMM3, 3);
1529	__lasx_xvslli_b(a, IMM3)	1529	unsafe { __lasx_xvslli_b(a, IMM3) }
1530	}	1530	}
1531		1531
1532	#[inline]	1532	#[inline]
1533	#[target_feature(enable = "lasx")]	1533	#[target_feature(enable = "lasx")]

...	@@ -1455,3593 +1455,3593 @@ unsafe extern "unadjusted" {	...	@@ -1455,3593 +1455,3593 @@ unsafe extern "unadjusted" {
1455	#[inline]	1455	#[inline]
1456	#[target_feature(enable = "lsx")]	1456	#[target_feature(enable = "lsx")]
1457	#[unstable(feature = "stdarch_loongarch", issue = "117427")]	1457	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
1458	pub unsafe fn lsx_vsll_b(a: v16i8, b: v16i8) -> v16i8 {	1458	pub fn lsx_vsll_b(a: v16i8, b: v16i8) -> v16i8 {
1459	__lsx_vsll_b(a, b)	1459	unsafe { __lsx_vsll_b(a, b) }
1460	}	1460	}
1461		1461
1462	#[inline]	1462	#[inline]
1463	#[target_feature(enable = "lsx")]	1463	#[target_feature(enable = "lsx")]
1464	#[unstable(feature = "stdarch_loongarch", issue = "117427")]	1464	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
1465	pub unsafe fn lsx_vsll_h(a: v8i16, b: v8i16) -> v8i16 {	1465	pub fn lsx_vsll_h(a: v8i16, b: v8i16) -> v8i16 {
1466	__lsx_vsll_h(a, b)	1466	unsafe { __lsx_vsll_h(a, b) }
1467	}	1467	}
1468		1468
1469	#[inline]	1469	#[inline]
1470	#[target_feature(enable = "lsx")]	1470	#[target_feature(enable = "lsx")]
1471	#[unstable(feature = "stdarch_loongarch", issue = "117427")]	1471	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
1472	pub unsafe fn lsx_vsll_w(a: v4i32, b: v4i32) -> v4i32 {	1472	pub fn lsx_vsll_w(a: v4i32, b: v4i32) -> v4i32 {
1473	__lsx_vsll_w(a, b)	1473	unsafe { __lsx_vsll_w(a, b) }
1474	}	1474	}
1475		1475
1476	#[inline]	1476	#[inline]
1477	#[target_feature(enable = "lsx")]	1477	#[target_feature(enable = "lsx")]
1478	#[unstable(feature = "stdarch_loongarch", issue = "117427")]	1478	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
1479	pub unsafe fn lsx_vsll_d(a: v2i64, b: v2i64) -> v2i64 {	1479	pub fn lsx_vsll_d(a: v2i64, b: v2i64) -> v2i64 {
1480	__lsx_vsll_d(a, b)	1480	unsafe { __lsx_vsll_d(a, b) }
1481	}	1481	}
1482		1482
1483	#[inline]	1483	#[inline]
1484	#[target_feature(enable = "lsx")]	1484	#[target_feature(enable = "lsx")]
1485	#[rustc_legacy_const_generics(1)]	1485	#[rustc_legacy_const_generics(1)]
1486	#[unstable(feature = "stdarch_loongarch", issue = "117427")]	1486	#[unstable(feature = "stdarch_loongarch", issue = "117427")]
1487	pub unsafe fn lsx_vslli_b<const IMM3: u32>(a: v16i8) -> v16i8 {	1487	pub fn lsx_vslli_b<const IMM3: u32>(a: v16i8) -> v16i8 {
1488	static_assert_uimm_bits!(IMM3, 3);	1488	static_assert_uimm_bits!(IMM3, 3);
1489	__lsx_vslli_b(a, IMM3)	1489	unsafe { __lsx_vslli_b(a, IMM3) }
1490	}	1490	}
1491		1491
1492	#[inline]	1492	#[inline]
1493	#[target_feature(enable = "lsx")]	1493	#[target_feature(enable = "lsx")]