Commit a18e6d9d1473d9b25581dd04bef6c7577999631c | rust

author	bors <bors@rust-lang.org> 2026-01-24 10:18:04 UTC
committer	bors <bors@rust-lang.org> 2026-01-24 10:18:04 UTC
log	a18e6d9d1473d9b25581dd04bef6c7577999631c
tree	1ffdeb3495137653fd12cfedcbba2b4e3c558d05
parent	87b272187129343c0efc8f92d253c16958aeac0b
parent	85430dfc909d9b95c1423e24f3bcc9b811b52d95

Auto merge of #151575 - JonathanBrouwer:rollup-hPBbNPJ, r=JonathanBrouwer

Rollup of 8 pull requests

Successful merges:

 - rust-lang/rust#150556 (Add Tier 3 Thumb-mode targets for Armv7-A, Armv7-R and Armv8-R)
 - rust-lang/rust#151259 (Fix is_ascii performance regression on AVX-512 CPUs when compiling with -C target-cpu=native)
 - rust-lang/rust#151500 (hexagon: Add HVX target features)
 - rust-lang/rust#151517 (Enable reproducible binary builds with debuginfo on Linux)
 - rust-lang/rust#151482 (Add "Skip to main content" link for keyboard navigation in rustdoc)
 - rust-lang/rust#151489 (constify boolean methods)
 - rust-lang/rust#151551 (Don't use default build-script fingerprinting in `test`)
 - rust-lang/rust#151555 (Fix compilation of std/src/sys/pal/uefi/tests.rs)

r? @ghost

32 files changed, 472 insertions(+), 206 deletions(-)

compiler/rustc_target/src/spec/mod.rs+5

...	...	@@ -1596,8 +1596,11 @@ supported_targets! {
1596	1596	("armebv7r-none-eabi", armebv7r_none_eabi),
1597	1597	("armebv7r-none-eabihf", armebv7r_none_eabihf),
1598	1598	("armv7r-none-eabi", armv7r_none_eabi),
	1599	("thumbv7r-none-eabi", thumbv7r_none_eabi),
1599	1600	("armv7r-none-eabihf", armv7r_none_eabihf),
	1601	("thumbv7r-none-eabihf", thumbv7r_none_eabihf),
1600	1602	("armv8r-none-eabihf", armv8r_none_eabihf),
	1603	("thumbv8r-none-eabihf", thumbv8r_none_eabihf),
1601	1604
1602	1605	("armv7-rtems-eabihf", armv7_rtems_eabihf),
1603	1606
...	...	@@ -1649,7 +1652,9 @@ supported_targets! {
1649	1652	("thumbv8m.main-none-eabihf", thumbv8m_main_none_eabihf),
1650	1653
1651	1654	("armv7a-none-eabi", armv7a_none_eabi),
	1655	("thumbv7a-none-eabi", thumbv7a_none_eabi),
1652	1656	("armv7a-none-eabihf", armv7a_none_eabihf),
	1657	("thumbv7a-none-eabihf", thumbv7a_none_eabihf),
1653	1658	("armv7a-nuttx-eabi", armv7a_nuttx_eabi),
1654	1659	("armv7a-nuttx-eabihf", armv7a_nuttx_eabihf),
1655	1660	("armv7a-vex-v5", armv7a_vex_v5),

compiler/rustc_target/src/spec/targets/armv7a_none_eabi.rs+10-35

...	...	@@ -1,40 +1,8 @@
1		// Generic ARMv7-A target for bare-metal code - floating point disabled
2		//
3		// This is basically the `armv7-unknown-linux-gnueabi` target with some changes
4		// (listed below) to bring it closer to the bare-metal `thumb` & `aarch64`
5		// targets:
6		//
7		// - `TargetOptions.features`: added `+strict-align`. rationale: unaligned
8		// memory access is disabled on boot on these cores
9		// - linker changed to LLD. rationale: C is not strictly needed to build
10		// bare-metal binaries (the `gcc` linker has the advantage that it knows where C
11		// libraries and crt*.o are but it's not much of an advantage here); LLD is also
12		// faster
13		// - `panic_strategy` set to `abort`. rationale: matches `thumb` targets
14		// - `relocation-model` set to `static`; also no PIE, no relro and no dynamic
15		// linking. rationale: matches `thumb` targets
	1	// Targets the Little-endian Cortex-A8 (and similar) processors (ARMv7-A)
16	2
17		use crate::spec::{
18		Abi, Arch, Cc, FloatAbi, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetMetadata,
19		TargetOptions,
20		};
	3	use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
21	4
22	5	pub(crate) fn target() -> Target {
23		let opts = TargetOptions {
24		abi: Abi::Eabi,
25		llvm_floatabi: Some(FloatAbi::Soft),
26		linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
27		linker: Some("rust-lld".into()),
28		features: "+v7,+thumb2,+soft-float,-neon,+strict-align".into(),
29		relocation_model: RelocModel::Static,
30		disable_redzone: true,
31		max_atomic_width: Some(64),
32		panic_strategy: PanicStrategy::Abort,
33		emit_debug_gdb_scripts: false,
34		c_enum_min_bits: Some(8),
35		has_thumb_interworking: true,
36		..Default::default()
37		};
38	6	Target {
39	7	llvm_target: "armv7a-none-eabi".into(),
40	8	metadata: TargetMetadata {
...	...	@@ -46,6 +14,13 @@ pub(crate) fn target() -> Target {
46	14	pointer_width: 32,
47	15	data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
48	16	arch: Arch::Arm,
49		options: opts,
	17	options: TargetOptions {
	18	abi: Abi::Eabi,
	19	llvm_floatabi: Some(FloatAbi::Soft),
	20	features: "+soft-float,-neon,+strict-align".into(),
	21	max_atomic_width: Some(64),
	22	has_thumb_interworking: true,
	23	..base::arm_none::opts()
	24	},
50	25	}
51	26	}

compiler/rustc_target/src/spec/targets/armv7a_none_eabihf.rs+10-27

...	...	@@ -1,32 +1,8 @@
1		// Generic ARMv7-A target for bare-metal code - floating point enabled (assumes
2		// FPU is present and emits FPU instructions)
3		//
4		// This is basically the `armv7-unknown-linux-gnueabihf` target with some
5		// changes (list in `armv7a_none_eabi.rs`) to bring it closer to the bare-metal
6		// `thumb` & `aarch64` targets.
	1	// Targets the Little-endian Cortex-A8 (and similar) processors (ARMv7-A)
7	2
8		use crate::spec::{
9		Abi, Arch, Cc, FloatAbi, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetMetadata,
10		TargetOptions,
11		};
	3	use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
12	4
13	5	pub(crate) fn target() -> Target {
14		let opts = TargetOptions {
15		abi: Abi::EabiHf,
16		llvm_floatabi: Some(FloatAbi::Hard),
17		linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
18		linker: Some("rust-lld".into()),
19		features: "+v7,+vfp3d16,+thumb2,-neon,+strict-align".into(),
20		relocation_model: RelocModel::Static,
21		disable_redzone: true,
22		max_atomic_width: Some(64),
23		panic_strategy: PanicStrategy::Abort,
24		emit_debug_gdb_scripts: false,
25		// GCC defaults to 8 for arm-none here.
26		c_enum_min_bits: Some(8),
27		has_thumb_interworking: true,
28		..Default::default()
29		};
30	6	Target {
31	7	llvm_target: "armv7a-none-eabihf".into(),
32	8	metadata: TargetMetadata {
...	...	@@ -38,6 +14,13 @@ pub(crate) fn target() -> Target {
38	14	pointer_width: 32,
39	15	data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
40	16	arch: Arch::Arm,
41		options: opts,
	17	options: TargetOptions {
	18	abi: Abi::EabiHf,
	19	llvm_floatabi: Some(FloatAbi::Hard),
	20	features: "+vfp3d16,-neon,+strict-align".into(),
	21	max_atomic_width: Some(64),
	22	has_thumb_interworking: true,
	23	..base::arm_none::opts()
	24	},
42	25	}
43	26	}

compiler/rustc_target/src/spec/targets/armv7r_none_eabi.rs+3-14

...	...	@@ -1,15 +1,12 @@
1	1	// Targets the Little-endian Cortex-R4/R5 processor (ARMv7-R)
2	2
3		use crate::spec::{
4		Abi, Arch, Cc, FloatAbi, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetMetadata,
5		TargetOptions,
6		};
	3	use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
7	4
8	5	pub(crate) fn target() -> Target {
9	6	Target {
10	7	llvm_target: "armv7r-none-eabi".into(),
11	8	metadata: TargetMetadata {
12		description: Some("Armv7-R".into()),
	9	description: Some("Bare Armv7-R".into()),
13	10	tier: Some(2),
14	11	host_tools: Some(false),
15	12	std: Some(false),
...	...	@@ -17,20 +14,12 @@ pub(crate) fn target() -> Target {
17	14	pointer_width: 32,
18	15	data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
19	16	arch: Arch::Arm,
20
21	17	options: TargetOptions {
22	18	abi: Abi::Eabi,
23	19	llvm_floatabi: Some(FloatAbi::Soft),
24		linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
25		linker: Some("rust-lld".into()),
26		relocation_model: RelocModel::Static,
27		panic_strategy: PanicStrategy::Abort,
28	20	max_atomic_width: Some(64),
29		emit_debug_gdb_scripts: false,
30		// GCC defaults to 8 for arm-none here.
31		c_enum_min_bits: Some(8),
32	21	has_thumb_interworking: true,
33		..Default::default()
	22	..base::arm_none::opts()
34	23	},
35	24	}
36	25	}

compiler/rustc_target/src/spec/targets/armv7r_none_eabihf.rs+3-14

...	...	@@ -1,15 +1,12 @@
1	1	// Targets the Little-endian Cortex-R4F/R5F processor (ARMv7-R)
2	2
3		use crate::spec::{
4		Abi, Arch, Cc, FloatAbi, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetMetadata,
5		TargetOptions,
6		};
	3	use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
7	4
8	5	pub(crate) fn target() -> Target {
9	6	Target {
10	7	llvm_target: "armv7r-none-eabihf".into(),
11	8	metadata: TargetMetadata {
12		description: Some("Armv7-R, hardfloat".into()),
	9	description: Some("Bare Armv7-R, hardfloat".into()),
13	10	tier: Some(2),
14	11	host_tools: Some(false),
15	12	std: Some(false),
...	...	@@ -17,21 +14,13 @@ pub(crate) fn target() -> Target {
17	14	pointer_width: 32,
18	15	data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
19	16	arch: Arch::Arm,
20
21	17	options: TargetOptions {
22	18	abi: Abi::EabiHf,
23	19	llvm_floatabi: Some(FloatAbi::Hard),
24		linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
25		linker: Some("rust-lld".into()),
26		relocation_model: RelocModel::Static,
27		panic_strategy: PanicStrategy::Abort,
28	20	features: "+vfp3d16".into(),
29	21	max_atomic_width: Some(64),
30		emit_debug_gdb_scripts: false,
31		// GCC defaults to 8 for arm-none here.
32		c_enum_min_bits: Some(8),
33	22	has_thumb_interworking: true,
34		..Default::default()
	23	..base::arm_none::opts()
35	24	},
36	25	}
37	26	}

compiler/rustc_target/src/spec/targets/armv8r_none_eabihf.rs+2-12

...	...	@@ -1,9 +1,6 @@
1	1	// Targets the Little-endian Cortex-R52 processor (ARMv8-R)
2	2
3		use crate::spec::{
4		Abi, Arch, Cc, FloatAbi, LinkerFlavor, Lld, PanicStrategy, RelocModel, Target, TargetMetadata,
5		TargetOptions,
6		};
	3	use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
7	4
8	5	pub(crate) fn target() -> Target {
9	6	Target {
...	...	@@ -21,10 +18,6 @@ pub(crate) fn target() -> Target {
21	18	options: TargetOptions {
22	19	abi: Abi::EabiHf,
23	20	llvm_floatabi: Some(FloatAbi::Hard),
24		linker_flavor: LinkerFlavor::Gnu(Cc::No, Lld::Yes),
25		linker: Some("rust-lld".into()),
26		relocation_model: RelocModel::Static,
27		panic_strategy: PanicStrategy::Abort,
28	21	// Armv8-R requires a minimum set of floating-point features equivalent to:
29	22	// fp-armv8, SP-only, with 16 DP (32 SP) registers
30	23	// LLVM defines Armv8-R to include these features automatically.
...	...	@@ -36,11 +29,8 @@ pub(crate) fn target() -> Target {
36	29	// Arm Cortex-R52 Processor Technical Reference Manual
37	30	// - Chapter 15 Advanced SIMD and floating-point support
38	31	max_atomic_width: Some(64),
39		emit_debug_gdb_scripts: false,
40		// GCC defaults to 8 for arm-none here.
41		c_enum_min_bits: Some(8),
42	32	has_thumb_interworking: true,
43		..Default::default()
	33	..base::arm_none::opts()
44	34	},
45	35	}
46	36	}

compiler/rustc_target/src/spec/targets/thumbv7a_none_eabi.rs created+26

...	...	@@ -0,0 +1,26 @@
	1	// Targets the Little-endian Cortex-A8 (and similar) processors (ARMv7-A)
	2
	3	use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
	4
	5	pub(crate) fn target() -> Target {
	6	Target {
	7	llvm_target: "thumbv7a-none-eabi".into(),
	8	metadata: TargetMetadata {
	9	description: Some("Thumb-mode Bare Armv7-A".into()),
	10	tier: Some(2),
	11	host_tools: Some(false),
	12	std: Some(false),
	13	},
	14	pointer_width: 32,
	15	data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
	16	arch: Arch::Arm,
	17	options: TargetOptions {
	18	abi: Abi::Eabi,
	19	llvm_floatabi: Some(FloatAbi::Soft),
	20	features: "+soft-float,-neon,+strict-align".into(),
	21	max_atomic_width: Some(64),
	22	has_thumb_interworking: true,
	23	..base::arm_none::opts()
	24	},
	25	}
	26	}

compiler/rustc_target/src/spec/targets/thumbv7a_none_eabihf.rs created+26

...	...	@@ -0,0 +1,26 @@
	1	// Targets the Little-endian Cortex-A8 (and similar) processors (ARMv7-A)
	2
	3	use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
	4
	5	pub(crate) fn target() -> Target {
	6	Target {
	7	llvm_target: "thumbv7a-none-eabihf".into(),
	8	metadata: TargetMetadata {
	9	description: Some("Thumb-mode Bare Armv7-A, hardfloat".into()),
	10	tier: Some(2),
	11	host_tools: Some(false),
	12	std: Some(false),
	13	},
	14	pointer_width: 32,
	15	data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
	16	arch: Arch::Arm,
	17	options: TargetOptions {
	18	abi: Abi::EabiHf,
	19	llvm_floatabi: Some(FloatAbi::Hard),
	20	features: "+vfp3d16,-neon,+strict-align".into(),
	21	max_atomic_width: Some(64),
	22	has_thumb_interworking: true,
	23	..base::arm_none::opts()
	24	},
	25	}
	26	}

compiler/rustc_target/src/spec/targets/thumbv7r_none_eabi.rs created+25

...	...	@@ -0,0 +1,25 @@
	1	// Targets the Little-endian Cortex-R4/R5 processor (ARMv7-R)
	2
	3	use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
	4
	5	pub(crate) fn target() -> Target {
	6	Target {
	7	llvm_target: "thumbv7r-none-eabi".into(),
	8	metadata: TargetMetadata {
	9	description: Some("Thumb-mode Bare Armv7-R".into()),
	10	tier: Some(2),
	11	host_tools: Some(false),
	12	std: Some(false),
	13	},
	14	pointer_width: 32,
	15	data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
	16	arch: Arch::Arm,
	17	options: TargetOptions {
	18	abi: Abi::Eabi,
	19	llvm_floatabi: Some(FloatAbi::Soft),
	20	max_atomic_width: Some(64),
	21	has_thumb_interworking: true,
	22	..base::arm_none::opts()
	23	},
	24	}
	25	}

compiler/rustc_target/src/spec/targets/thumbv7r_none_eabihf.rs created+26

...	...	@@ -0,0 +1,26 @@
	1	// Targets the Little-endian Cortex-R4F/R5F processor (ARMv7-R)
	2
	3	use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
	4
	5	pub(crate) fn target() -> Target {
	6	Target {
	7	llvm_target: "thumbv7r-none-eabihf".into(),
	8	metadata: TargetMetadata {
	9	description: Some("Thumb-mode Bare Armv7-R, hardfloat".into()),
	10	tier: Some(2),
	11	host_tools: Some(false),
	12	std: Some(false),
	13	},
	14	pointer_width: 32,
	15	data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
	16	arch: Arch::Arm,
	17	options: TargetOptions {
	18	abi: Abi::EabiHf,
	19	llvm_floatabi: Some(FloatAbi::Hard),
	20	features: "+vfp3d16".into(),
	21	max_atomic_width: Some(64),
	22	has_thumb_interworking: true,
	23	..base::arm_none::opts()
	24	},
	25	}
	26	}

compiler/rustc_target/src/spec/targets/thumbv8r_none_eabihf.rs created+36

...	...	@@ -0,0 +1,36 @@
	1	// Targets the Little-endian Cortex-R52 processor (ARMv8-R)
	2
	3	use crate::spec::{Abi, Arch, FloatAbi, Target, TargetMetadata, TargetOptions, base};
	4
	5	pub(crate) fn target() -> Target {
	6	Target {
	7	llvm_target: "thumbv8r-none-eabihf".into(),
	8	metadata: TargetMetadata {
	9	description: Some("Thumb-mode Bare Armv8-R, hardfloat".into()),
	10	tier: Some(2),
	11	host_tools: Some(false),
	12	std: Some(false),
	13	},
	14	pointer_width: 32,
	15	data_layout: "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64".into(),
	16	arch: Arch::Arm,
	17
	18	options: TargetOptions {
	19	abi: Abi::EabiHf,
	20	llvm_floatabi: Some(FloatAbi::Hard),
	21	// Armv8-R requires a minimum set of floating-point features equivalent to:
	22	// fp-armv8, SP-only, with 16 DP (32 SP) registers
	23	// LLVM defines Armv8-R to include these features automatically.
	24	//
	25	// The Cortex-R52 supports these default features and optionally includes:
	26	// neon-fp-armv8, SP+DP, with 32 DP registers
	27	//
	28	// Reference:
	29	// Arm Cortex-R52 Processor Technical Reference Manual
	30	// - Chapter 15 Advanced SIMD and floating-point support
	31	max_atomic_width: Some(64),
	32	has_thumb_interworking: true,
	33	..base::arm_none::opts()
	34	},
	35	}
	36	}

compiler/rustc_target/src/target_features.rs+16-1

...	...	@@ -492,7 +492,22 @@ static X86_FEATURES: &[(&str, Stability, ImpliedFeatures)] = &[
492	492	const HEXAGON_FEATURES: &[(&str, Stability, ImpliedFeatures)] = &[
493	493	// tidy-alphabetical-start
494	494	("hvx", Unstable(sym::hexagon_target_feature), &[]),
	495	("hvx-ieee-fp", Unstable(sym::hexagon_target_feature), &["hvx"]),
	496	("hvx-length64b", Unstable(sym::hexagon_target_feature), &["hvx"]),
495	497	("hvx-length128b", Unstable(sym::hexagon_target_feature), &["hvx"]),
	498	("hvx-qfloat", Unstable(sym::hexagon_target_feature), &["hvx"]),
	499	("hvxv60", Unstable(sym::hexagon_target_feature), &["hvx"]),
	500	("hvxv62", Unstable(sym::hexagon_target_feature), &["hvxv60"]),
	501	("hvxv65", Unstable(sym::hexagon_target_feature), &["hvxv62"]),
	502	("hvxv66", Unstable(sym::hexagon_target_feature), &["hvxv65", "zreg"]),
	503	("hvxv67", Unstable(sym::hexagon_target_feature), &["hvxv66"]),
	504	("hvxv68", Unstable(sym::hexagon_target_feature), &["hvxv67"]),
	505	("hvxv69", Unstable(sym::hexagon_target_feature), &["hvxv68"]),
	506	("hvxv71", Unstable(sym::hexagon_target_feature), &["hvxv69"]),
	507	("hvxv73", Unstable(sym::hexagon_target_feature), &["hvxv71"]),
	508	("hvxv75", Unstable(sym::hexagon_target_feature), &["hvxv73"]),
	509	("hvxv79", Unstable(sym::hexagon_target_feature), &["hvxv75"]),
	510	("zreg", Unstable(sym::hexagon_target_feature), &[]),
496	511	// tidy-alphabetical-end
497	512	];
498	513
...	...	@@ -949,7 +964,7 @@ const SPARC_FEATURES_FOR_CORRECT_FIXED_LENGTH_VECTOR_ABI: &'static [(u64, &'stat
949	964	&[/(64, "vis")/];
950	965
951	966	const HEXAGON_FEATURES_FOR_CORRECT_FIXED_LENGTH_VECTOR_ABI: &'static [(u64, &'static str)] =
952		&[/(512, "hvx-length64b"),/ (1024, "hvx-length128b")];
	967	&[(512, "hvx-length64b"), (1024, "hvx-length128b")];
953	968	const MIPS_FEATURES_FOR_CORRECT_FIXED_LENGTH_VECTOR_ABI: &'static [(u64, &'static str)] =
954	969	&[(128, "msa")];
955	970	const CSKY_FEATURES_FOR_CORRECT_FIXED_LENGTH_VECTOR_ABI: &'static [(u64, &'static str)] =

library/core/src/bool.rs+13-4

...	...	@@ -1,5 +1,7 @@
1	1	//! impl bool {}
2	2
	3	use crate::marker::Destruct;
	4
3	5	impl bool {
4	6	/// Returns `Some(t)` if the `bool` is [`true`](../std/keyword.true.html),
5	7	/// or `None` otherwise.
...	...	@@ -29,8 +31,9 @@ impl bool {
29	31	/// assert_eq!(a, 2);
30	32	/// ```
31	33	#[stable(feature = "bool_to_option", since = "1.62.0")]
	34	#[rustc_const_unstable(feature = "const_bool", issue = "151531")]
32	35	#[inline]
33		pub fn then_some<T>(self, t: T) -> Option<T> {
	36	pub const fn then_some<T: [const] Destruct>(self, t: T) -> Option<T> {
34	37	if self { Some(t) } else { None }
35	38	}
36	39
...	...	@@ -57,8 +60,9 @@ impl bool {
57	60	#[doc(alias = "then_with")]
58	61	#[stable(feature = "lazy_bool_to_option", since = "1.50.0")]
59	62	#[rustc_diagnostic_item = "bool_then"]
	63	#[rustc_const_unstable(feature = "const_bool", issue = "151531")]
60	64	#[inline]
61		pub fn then<T, F: FnOnce() -> T>(self, f: F) -> Option<T> {
	65	pub const fn then<T, F: [const] FnOnce() -> T + [const] Destruct>(self, f: F) -> Option<T> {
62	66	if self { Some(f()) } else { None }
63	67	}
64	68
...	...	@@ -94,8 +98,9 @@ impl bool {
94	98	/// assert_eq!(a, 2);
95	99	/// ```
96	100	#[unstable(feature = "bool_to_result", issue = "142748")]
	101	#[rustc_const_unstable(feature = "const_bool", issue = "151531")]
97	102	#[inline]
98		pub fn ok_or<E>(self, err: E) -> Result<(), E> {
	103	pub const fn ok_or<E: [const] Destruct>(self, err: E) -> Result<(), E> {
99	104	if self { Ok(()) } else { Err(err) }
100	105	}
101	106
...	...	@@ -124,8 +129,12 @@ impl bool {
124	129	/// assert_eq!(a, 1);
125	130	/// ```
126	131	#[unstable(feature = "bool_to_result", issue = "142748")]
	132	#[rustc_const_unstable(feature = "const_bool", issue = "151531")]
127	133	#[inline]
128		pub fn ok_or_else<E, F: FnOnce() -> E>(self, f: F) -> Result<(), E> {
	134	pub const fn ok_or_else<E, F: [const] FnOnce() -> E + [const] Destruct>(
	135	self,
	136	f: F,
	137	) -> Result<(), E> {
129	138	if self { Ok(()) } else { Err(f()) }
130	139	}
131	140	}

library/core/src/slice/ascii.rs+91-12

...	...	@@ -3,10 +3,7 @@
3	3	use core::ascii::EscapeDefault;
4	4
5	5	use crate::fmt::{self, Write};
6		#[cfg(not(any(
7		all(target_arch = "x86_64", target_feature = "sse2"),
8		all(target_arch = "loongarch64", target_feature = "lsx")
9		)))]
	6	#[cfg(not(all(target_arch = "loongarch64", target_feature = "lsx")))]
10	7	use crate::intrinsics::const_eval_select;
11	8	use crate::{ascii, iter, ops};
12	9
...	...	@@ -463,19 +460,101 @@ const fn is_ascii(s: &[u8]) -> bool {
463	460	)
464	461	}
465	462
466		/// ASCII test optimized to use the `pmovmskb` instruction on `x86-64` and the
467		/// `vmskltz.b` instruction on `loongarch64`.
	463	/// Chunk size for vectorized ASCII checking (two 16-byte SSE registers).
	464	#[cfg(all(target_arch = "x86_64", target_feature = "sse2"))]
	465	const CHUNK_SIZE: usize = 32;
	466
	467	/// SSE2 implementation using `_mm_movemask_epi8` (compiles to `pmovmskb`) to
	468	/// avoid LLVM's broken AVX-512 auto-vectorization of counting loops.
	469	///
	470	/// FIXME(llvm#176906): Remove this workaround once LLVM generates efficient code.
	471	#[cfg(all(target_arch = "x86_64", target_feature = "sse2"))]
	472	fn is_ascii_sse2(bytes: &[u8]) -> bool {
	473	use crate::arch::x86_64::{__m128i, _mm_loadu_si128, _mm_movemask_epi8, _mm_or_si128};
	474
	475	let mut i = 0;
	476
	477	while i + CHUNK_SIZE <= bytes.len() {
	478	// SAFETY: We have verified that `i + CHUNK_SIZE <= bytes.len()`.
	479	let ptr = unsafe { bytes.as_ptr().add(i) };
	480
	481	// Load two 16-byte chunks and combine them.
	482	// SAFETY: We verified `i + 32 <= len`, so ptr is valid for 32 bytes.
	483	// `_mm_loadu_si128` allows unaligned loads.
	484	let chunk1 = unsafe { _mm_loadu_si128(ptr as *const __m128i) };
	485	// SAFETY: Same as above - ptr.add(16) is within the valid 32-byte range.
	486	let chunk2 = unsafe { _mm_loadu_si128(ptr.add(16) as *const __m128i) };
	487
	488	// OR them together - if any byte has the high bit set, the result will too.
	489	// SAFETY: SSE2 is guaranteed by the cfg predicate.
	490	let combined = unsafe { _mm_or_si128(chunk1, chunk2) };
	491
	492	// Create a mask from the MSBs of each byte.
	493	// If any byte is >= 128, its MSB is 1, so the mask will be non-zero.
	494	// SAFETY: SSE2 is guaranteed by the cfg predicate.
	495	let mask = unsafe { _mm_movemask_epi8(combined) };
	496
	497	if mask != 0 {
	498	return false;
	499	}
	500
	501	i += CHUNK_SIZE;
	502	}
	503
	504	// Handle remaining bytes with simple loop
	505	while i < bytes.len() {
	506	if !bytes[i].is_ascii() {
	507	return false;
	508	}
	509	i += 1;
	510	}
	511
	512	true
	513	}
	514
	515	/// ASCII test optimized to use the `pmovmskb` instruction on `x86-64`.
	516	///
	517	/// Uses explicit SSE2 intrinsics to prevent LLVM from auto-vectorizing with
	518	/// broken AVX-512 code that extracts mask bits one-by-one.
	519	#[cfg(all(target_arch = "x86_64", target_feature = "sse2"))]
	520	#[inline]
	521	#[rustc_allow_const_fn_unstable(const_eval_select)]
	522	const fn is_ascii(bytes: &[u8]) -> bool {
	523	const USIZE_SIZE: usize = size_of::<usize>();
	524	const NONASCII_MASK: usize = usize::MAX / 255 * 0x80;
	525
	526	const_eval_select!(
	527	@capture { bytes: &[u8] } -> bool:
	528	if const {
	529	is_ascii_simple(bytes)
	530	} else {
	531	// For small inputs, use usize-at-a-time processing to avoid SSE2 call overhead.
	532	if bytes.len() < CHUNK_SIZE {
	533	let chunks = bytes.chunks_exact(USIZE_SIZE);
	534	let remainder = chunks.remainder();
	535	for chunk in chunks {
	536	let word = usize::from_ne_bytes(chunk.try_into().unwrap());
	537	if (word & NONASCII_MASK) != 0 {
	538	return false;
	539	}
	540	}
	541	return remainder.iter().all(\|b\| b.is_ascii());
	542	}
	543
	544	is_ascii_sse2(bytes)
	545	}
	546	)
	547	}
	548
	549	/// ASCII test optimized to use the `vmskltz.b` instruction on `loongarch64`.
468	550	///
469	551	/// Other platforms are not likely to benefit from this code structure, so they
470	552	/// use SWAR techniques to test for ASCII in `usize`-sized chunks.
471		#[cfg(any(
472		all(target_arch = "x86_64", target_feature = "sse2"),
473		all(target_arch = "loongarch64", target_feature = "lsx")
474		))]
	553	#[cfg(all(target_arch = "loongarch64", target_feature = "lsx"))]
475	554	#[inline]
476	555	const fn is_ascii(bytes: &[u8]) -> bool {
477	556	// Process chunks of 32 bytes at a time in the fast path to enable
478		// auto-vectorization and use of `pmovmskb`. Two 128-bit vector registers
	557	// auto-vectorization and use of `vmskltz.b`. Two 128-bit vector registers
479	558	// can be OR'd together and then the resulting vector can be tested for
480	559	// non-ASCII bytes.
481	560	const CHUNK_SIZE: usize = 32;
...	...	@@ -485,7 +564,7 @@ const fn is_ascii(bytes: &[u8]) -> bool {
485	564	while i + CHUNK_SIZE <= bytes.len() {
486	565	let chunk_end = i + CHUNK_SIZE;
487	566
488		// Get LLVM to produce a `pmovmskb` instruction on x86-64 which
	567	// Get LLVM to produce a `vmskltz.b` instruction on loongarch64 which
489	568	// creates a mask from the most significant bit of each byte.
490	569	// ASCII bytes are less than 128 (0x80), so their most significant
491	570	// bit is unset.

library/coretests/tests/bool.rs+14-6

...	...	@@ -82,6 +82,10 @@ pub fn test_bool_not() {
82	82	}
83	83	}
84	84
	85	const fn zero() -> i32 {
	86	0
	87	}
	88
85	89	#[test]
86	90	fn test_bool_to_option() {
87	91	assert_eq!(false.then_some(0), None);
...	...	@@ -89,11 +93,6 @@ fn test_bool_to_option() {
89	93	assert_eq!(false.then(\|\| 0), None);
90	94	assert_eq!(true.then(\|\| 0), Some(0));
91	95
92		/* FIXME(#110395)
93		const fn zero() -> i32 {
94		0
95		}
96
97	96	const A: Option<i32> = false.then_some(0);
98	97	const B: Option<i32> = true.then_some(0);
99	98	const C: Option<i32> = false.then(zero);
...	...	@@ -103,7 +102,6 @@ fn test_bool_to_option() {
103	102	assert_eq!(B, Some(0));
104	103	assert_eq!(C, None);
105	104	assert_eq!(D, Some(0));
106		*/
107	105	}
108	106
109	107	#[test]
...	...	@@ -112,4 +110,14 @@ fn test_bool_to_result() {
112	110	assert_eq!(true.ok_or(0), Ok(()));
113	111	assert_eq!(false.ok_or_else(\|\| 0), Err(0));
114	112	assert_eq!(true.ok_or_else(\|\| 0), Ok(()));
	113
	114	const A: Result<(), i32> = false.ok_or(0);
	115	const B: Result<(), i32> = true.ok_or(0);
	116	const C: Result<(), i32> = false.ok_or_else(zero);
	117	const D: Result<(), i32> = true.ok_or_else(zero);
	118
	119	assert_eq!(A, Err(0));
	120	assert_eq!(B, Ok(()));
	121	assert_eq!(C, Err(0));
	122	assert_eq!(D, Ok(()));
115	123	}

library/coretests/tests/lib.rs+1

...	...	@@ -17,6 +17,7 @@
17	17	#![feature(clamp_magnitude)]
18	18	#![feature(clone_to_uninit)]
19	19	#![feature(const_array)]
	20	#![feature(const_bool)]
20	21	#![feature(const_cell_traits)]
21	22	#![feature(const_clone)]
22	23	#![feature(const_cmp)]

library/std/src/sys/pal/uefi/tests.rs+17-36

...	...	@@ -1,14 +1,14 @@
1	1	//! These tests are not run automatically right now. Please run these tests manually by copying them
2	2	//! to a separate project when modifying any related code.
3	3
4		use super::alloc::*;
5	4	use super::time::system_time_internal::{from_uefi, to_uefi};
6	5	use crate::io::{IoSlice, IoSliceMut};
	6	use crate::ops::{Deref, DerefMut};
7	7	use crate::time::Duration;
8	8
9	9	const SECS_IN_MINUTE: u64 = 60;
10	10
11		const MAX_UEFI_TIME: Duration = from_uefi(r_efi::efi::Time {
	11	const MAX_UEFI_TIME: Duration = from_uefi(&r_efi::efi::Time {
12	12	year: 9999,
13	13	month: 12,
14	14	day: 31,
...	...	@@ -20,27 +20,8 @@ const MAX_UEFI_TIME: Duration = from_uefi(r_efi::efi::Time {
20	20	daylight: 0,
21	21	pad1: 0,
22	22	pad2: 0,
23		});
24
25		#[test]
26		fn align() {
27		// UEFI ABI specifies that allocation alignment minimum is always 8. So this can be
28		// statically verified.
29		assert_eq!(POOL_ALIGNMENT, 8);
30
31		// Loop over allocation-request sizes from 0-256 and alignments from 1-128, and verify
32		// that in case of overalignment there is at least space for one additional pointer to
33		// store in the allocation.
34		for i in 0..256 {
35		for j in &[1, 2, 4, 8, 16, 32, 64, 128] {
36		if *j <= 8 {
37		assert_eq!(align_size(i, *j), i);
38		} else {
39		assert!(align_size(i, j) > i + size_of::<mut ()>());
40		}
41		}
42		}
43		}
	23	})
	24	.unwrap();
44	25
45	26	// UEFI Time cannot implement Eq due to uninitilaized pad1 and pad2
46	27	fn uefi_time_cmp(t1: r_efi::efi::Time, t2: r_efi::efi::Time) -> bool {
...	...	@@ -70,9 +51,9 @@ fn systemtime_start() {
70	51	daylight: 0,
71	52	pad2: 0,
72	53	};
73		assert_eq!(from_uefi(&t), Duration::new(0, 0));
74		assert!(uefi_time_cmp(t, to_uefi(&from_uefi(&t), -1440, 0).unwrap()));
75		assert!(to_uefi(&from_uefi(&t), 0, 0).is_err());
	54	assert_eq!(from_uefi(&t).unwrap(), Duration::new(0, 0));
	55	assert!(uefi_time_cmp(t, to_uefi(&from_uefi(&t).unwrap(), -1440, 0).unwrap()));
	56	assert!(to_uefi(&from_uefi(&t).unwrap(), 0, 0).is_err());
76	57	}
77	58
78	59	#[test]
...	...	@@ -90,9 +71,9 @@ fn systemtime_utc_start() {
90	71	daylight: 0,
91	72	pad2: 0,
92	73	};
93		assert_eq!(from_uefi(&t), Duration::new(1440 * SECS_IN_MINUTE, 0));
94		assert!(uefi_time_cmp(t, to_uefi(&from_uefi(&t), 0, 0).unwrap()));
95		assert!(to_uefi(&from_uefi(&t), -1440, 0).is_ok());
	74	assert_eq!(from_uefi(&t).unwrap(), Duration::new(1440 * SECS_IN_MINUTE, 0));
	75	assert!(uefi_time_cmp(t, to_uefi(&from_uefi(&t).unwrap(), 0, 0).unwrap()));
	76	assert!(to_uefi(&from_uefi(&t).unwrap(), -1440, 0).is_ok());
96	77	}
97	78
98	79	#[test]
...	...	@@ -110,8 +91,8 @@ fn systemtime_end() {
110	91	daylight: 0,
111	92	pad2: 0,
112	93	};
113		assert!(to_uefi(&from_uefi(&t), 1440, 0).is_ok());
114		assert!(to_uefi(&from_uefi(&t), 1439, 0).is_err());
	94	assert!(to_uefi(&from_uefi(&t).unwrap(), 1440, 0).is_ok());
	95	assert!(to_uefi(&from_uefi(&t).unwrap(), 1439, 0).is_err());
115	96	}
116	97
117	98	#[test]
...	...	@@ -139,17 +120,17 @@ fn min_time() {
139	120
140	121	#[test]
141	122	fn max_time() {
142		let inp = MAX_UEFI_TIME.0;
	123	let inp = MAX_UEFI_TIME;
143	124	let new_tz = to_uefi(&inp, -1440, 0).err().unwrap();
144	125	assert_eq!(new_tz, 1440);
145	126	assert!(to_uefi(&inp, new_tz, 0).is_ok());
146	127
147		let inp = MAX_UEFI_TIME.0 - Duration::from_secs(1440 * SECS_IN_MINUTE);
	128	let inp = MAX_UEFI_TIME - Duration::from_secs(1440 * SECS_IN_MINUTE);
148	129	let new_tz = to_uefi(&inp, -1440, 0).err().unwrap();
149	130	assert_eq!(new_tz, 0);
150	131	assert!(to_uefi(&inp, new_tz, 0).is_ok());
151	132
152		let inp = MAX_UEFI_TIME.0 - Duration::from_secs(1440 * SECS_IN_MINUTE + 10);
	133	let inp = MAX_UEFI_TIME - Duration::from_secs(1440 * SECS_IN_MINUTE + 10);
153	134	let new_tz = to_uefi(&inp, -1440, 0).err().unwrap();
154	135	assert_eq!(new_tz, 0);
155	136	assert!(to_uefi(&inp, new_tz, 0).is_ok());
...	...	@@ -266,8 +247,8 @@ fn io_slice_mut_basic() {
266	247	let mut data_clone = [0, 1, 2, 3, 4];
267	248	let mut io_slice_mut = IoSliceMut::new(&mut data_clone);
268	249
269		assert_eq!(data, io_slice_mut.as_slice());
270		assert_eq!(data, io_slice_mut.as_mut_slice());
	250	assert_eq!(data, io_slice_mut.deref());
	251	assert_eq!(data, io_slice_mut.deref_mut());
271	252
272	253	io_slice_mut.advance(2);
273	254	assert_eq!(&data[2..], io_slice_mut.into_slice());

library/test/build.rs+1

...	...	@@ -1,4 +1,5 @@
1	1	fn main() {
	2	println!("cargo:rerun-if-changed=build.rs");
2	3	println!("cargo:rustc-check-cfg=cfg(enable_unstable_features)");
3	4
4	5	let rustc = std::env::var("RUSTC").unwrap_or_else(\|_\| "rustc".into());

src/bootstrap/src/core/sanity.rs+5

...	...	@@ -38,6 +38,11 @@ pub struct Finder {
38	38	const STAGE0_MISSING_TARGETS: &[&str] = &[
39	39	// just a dummy comment so the list doesn't get onelined
40	40	"x86_64-unknown-linux-gnuasan",
	41	"thumbv7a-none-eabi",
	42	"thumbv7a-none-eabihf",
	43	"thumbv7r-none-eabi",
	44	"thumbv7r-none-eabihf",
	45	"thumbv8r-none-eabihf",
41	46	];
42	47
43	48	/// Minimum version threshold for libstdc++ required when using prebuilt LLVM

src/doc/rustc/src/SUMMARY.md+4-4

...	...	@@ -56,15 +56,15 @@
56	56	- [arm-none-eabi](platform-support/arm-none-eabi.md)
57	57	- [{arm,thumb}v4t-none-eabi](platform-support/armv4t-none-eabi.md)
58	58	- [{arm,thumb}v5te-none-eabi](platform-support/armv5te-none-eabi.md)
59		- [armv7a-none-eabi{,hf}](platform-support/armv7a-none-eabi.md)
60		- [armv7r-none-eabi{,hf}](platform-support/armv7r-none-eabi.md)
61		- [armebv7r-none-eabi{,hf}](platform-support/armebv7r-none-eabi.md)
62		- [armv8r-none-eabihf](platform-support/armv8r-none-eabihf.md)
	59	- [{arm,thumb}v7a-none-eabi{,hf}](platform-support/armv7a-none-eabi.md)
	60	- [{arm,thumb}v7r-none-eabi{,hf}](platform-support/armv7r-none-eabi.md)
	61	- [{arm,thumb}v8r-none-eabihf](platform-support/armv8r-none-eabihf.md)
63	62	- [thumbv6m-none-eabi](./platform-support/thumbv6m-none-eabi.md)
64	63	- [thumbv7em-none-eabi\*](./platform-support/thumbv7em-none-eabi.md)
65	64	- [thumbv7m-none-eabi](./platform-support/thumbv7m-none-eabi.md)
66	65	- [thumbv8m.base-none-eabi](./platform-support/thumbv8m.base-none-eabi.md)
67	66	- [thumbv8m.main-none-eabi\*](./platform-support/thumbv8m.main-none-eabi.md)
	67	- [armebv7r-none-eabi{,hf}](platform-support/armebv7r-none-eabi.md)
68	68	- [arm\-unknown-linux-\](./platform-support/arm-linux.md)
69	69	- [armeb-unknown-linux-gnueabi](platform-support/armeb-unknown-linux-gnueabi.md)
70	70	- [armv5te-unknown-linux-gnueabi](platform-support/armv5te-unknown-linux-gnueabi.md)

src/doc/rustc/src/platform-support.md+7-2

...	...	@@ -411,17 +411,22 @@ target \| std \| host \| notes
411	411	[`thumbv4t-none-eabi`](platform-support/armv4t-none-eabi.md) \| * \| \| Thumb-mode Bare Armv4T
412	412	[`thumbv5te-none-eabi`](platform-support/armv5te-none-eabi.md) \| * \| \| Thumb-mode Bare Armv5TE
413	413	[`thumbv6m-nuttx-eabi`](platform-support/nuttx.md) \| ✓ \| \| ARMv6M with NuttX
414		`thumbv7a-pc-windows-msvc` \| \| \|
415		[`thumbv7a-uwp-windows-msvc`](platform-support/uwp-windows-msvc.md) \| \| \|
	414	[`thumbv7a-none-eabi`](platform-support/armv7a-none-eabi.md) \| * \| \| Thumb-mode Bare Armv7-A
	415	[`thumbv7a-none-eabihf`](platform-support/armv7a-none-eabi.md) \| * \| \| Thumb-mode Bare Armv7-A, hardfloat
416	416	[`thumbv7a-nuttx-eabi`](platform-support/nuttx.md) \| ✓ \| \| ARMv7-A with NuttX
417	417	[`thumbv7a-nuttx-eabihf`](platform-support/nuttx.md) \| ✓ \| \| ARMv7-A with NuttX, hardfloat
	418	`thumbv7a-pc-windows-msvc` \| \| \|
	419	[`thumbv7a-uwp-windows-msvc`](platform-support/uwp-windows-msvc.md) \| \| \|
418	420	[`thumbv7em-nuttx-eabi`](platform-support/nuttx.md) \| ✓ \| \| ARMv7EM with NuttX
419	421	[`thumbv7em-nuttx-eabihf`](platform-support/nuttx.md) \| ✓ \| \| ARMv7EM with NuttX, hardfloat
420	422	[`thumbv7m-nuttx-eabi`](platform-support/nuttx.md) \| ✓ \| \| ARMv7M with NuttX
421	423	`thumbv7neon-unknown-linux-musleabihf` \| ? \| \| Thumb2-mode Armv7-A Linux with NEON, musl 1.2.5
	424	[`thumbv7r-none-eabi`](platform-support/armv7r-none-eabi.md) \| * \| \| Thumb-mode Bare Armv7-R
	425	[`thumbv7r-none-eabihf`](platform-support/armv7r-none-eabi.md) \| * \| \| Thumb-mode Bare Armv7-R, hardfloat
422	426	[`thumbv8m.base-nuttx-eabi`](platform-support/nuttx.md) \| ✓ \| \| ARMv8M Baseline with NuttX
423	427	[`thumbv8m.main-nuttx-eabi`](platform-support/nuttx.md) \| ✓ \| \| ARMv8M Mainline with NuttX
424	428	[`thumbv8m.main-nuttx-eabihf`](platform-support/nuttx.md) \| ✓ \| \| ARMv8M Mainline with NuttX, hardfloat
	429	[`thumbv8r-none-eabihf`](platform-support/armv8r-none-eabihf.md) \| * \| \| Thumb-mode Bare Armv8-R, hardfloat
425	430	[`wasm64-unknown-unknown`](platform-support/wasm64-unknown-unknown.md) \| ? \| \| WebAssembly
426	431	[`wasm32-wali-linux-musl`](platform-support/wasm32-wali-linux.md) \| ? \| \| WebAssembly with [WALI](https://github.com/arjunr2/WALI)
427	432	[`wasm32-wasip3`](platform-support/wasm32-wasip3.md) \| ✓ \| \| WebAssembly with WASIp3

src/doc/rustc/src/platform-support/armv7a-none-eabi.md+8-4

...	...	@@ -1,10 +1,14 @@
1		# `armv7a-none-eabi` and `armv7a-none-eabihf`
	1	# `armv7a-none-eabi` and `thumbv7a-none-eabi`
2	2
3		* Tier: 2
	3	* Tier: 2 (`armv7a-none-eabi` and `armv7a-none-eabihf`)
	4	* Tier: 3 (`thumbv7a-none-eabi` and `thumbv7a-none-eabihf`)
4	5	* Library Support: core and alloc (bare-metal, `#![no_std]`)
5	6
6		Bare-metal target for CPUs in the Armv7-A architecture family, supporting
7		dual ARM/Thumb mode, with ARM mode as the default.
	7	Bare-metal target for CPUs in the Armv7-A architecture family, supporting dual
	8	ARM/Thumb mode. The `armv7a-none-eabi*` targets use Arm mode by default and the
	9	`thumbv7a-none-eabi` targets use Thumb mode by default. The `-eabi` targets use
	10	a soft-float ABI and do not require an FPU, while the `-eabihf` targets use a
	11	hard-float ABI and do require an FPU.
8	12
9	13	Note, this is for processors running in AArch32 mode. For the AArch64 mode
10	14	added in Armv8-A, see [`aarch64-unknown-none`](aarch64-unknown-none.md) instead.

src/doc/rustc/src/platform-support/armv7r-none-eabi.md+13-9

...	...	@@ -1,10 +1,14 @@
1		# `armv7r-none-eabi` and `armv7r-none-eabihf`
	1	# `armv7r-none-eabi` and `thumbv7r-none-eabi`
2	2
3		* Tier: 2
	3	* Tier: 2 (`armv7r-none-eabi` and `armv7r-none-eabihf`)
	4	* Tier: 3 (`thumbv7r-none-eabi` and `thumbv7r-none-eabihf`)
4	5	* Library Support: core and alloc (bare-metal, `#![no_std]`)
5	6
6		Bare-metal target for CPUs in the Armv7-R architecture family, supporting
7		dual ARM/Thumb mode, with ARM mode as the default.
	7	Bare-metal target for CPUs in the Armv7-R architecture family, supporting dual
	8	ARM/Thumb mode. The `armv7r-none-eabi*` targets use Arm mode by default and the
	9	`thumbv7r-none-eabi*` targets use Thumb mode by default. The `-eabi` targets use
	10	a soft-float ABI and do not require an FPU, while the `-eabihf` targets use a
	11	hard-float ABI and do require an FPU.
8	12
9	13	Processors in this family include the [Arm Cortex-R4, 5, 7, and 8][cortex-r].
10	14
...	...	@@ -25,11 +29,11 @@ See [`arm-none-eabi`](arm-none-eabi.md) for information applicable to all
25	29
26	30	## Requirements
27	31
28		When using the hardfloat targets, the minimum floating-point features assumed
29		are those of the `vfpv3-d16`, which includes single- and double-precision, with
30		16 double-precision registers. This floating-point unit appears in Cortex-R4F
31		and Cortex-R5F processors. See [VFP in the Cortex-R processors][vfp]
32		for more details on the possible FPU variants.
	32	When using the hardfloat (`-eabibf`) targets, the minimum floating-point
	33	features assumed are those of the `vfpv3-d16`, which includes single- and
	34	double-precision, with 16 double-precision registers. This floating-point unit
	35	appears in Cortex-R4F and Cortex-R5F processors. See [VFP in the Cortex-R
	36	processors][vfp] for more details on the possible FPU variants.
33	37
34	38	If your processor supports a different set of floating-point features than the
35	39	default expectations of `vfpv3-d16`, then these should also be enabled or

src/doc/rustc/src/platform-support/armv8r-none-eabihf.md+7-4

...	...	@@ -1,10 +1,13 @@
1		# `armv8r-none-eabihf`
	1	# `armv8r-none-eabihf` and `thumbv8r-none-eabihf`
2	2
3		* Tier: 2
	3	* Tier: 2: `armv8r-none-eabihf`
	4	* Tier: 3: `thumbv8r-none-eabihf`
4	5	* Library Support: core and alloc (bare-metal, `#![no_std]`)
5	6
6		Bare-metal target for CPUs in the Armv8-R architecture family, supporting
7		dual ARM/Thumb mode, with ARM mode as the default.
	7	Bare-metal target for CPUs in the Armv8-R architecture family, supporting dual
	8	ARM/Thumb mode. The `armv8r-none-eabihf` target uses Arm mode by default and
	9	the `thumbv8r-none-eabihf` target uses Thumb mode by default. Both targets
	10	use a hard-float ABI and require an FPU.
8	11
9	12	Processors in this family include the Arm [Cortex-R52][cortex-r52]
10	13	and [Cortex-R52+][cortex-r52-plus].

src/librustdoc/html/static/css/rustdoc.css+19

...	...	@@ -210,6 +210,24 @@ body {
210	210	color: var(--main-color);
211	211	}
212	212
	213	/* Skip navigation link for keyboard users (WCAG 2.4.1) */
	214	.skip-main-content {
	215	position: absolute;
	216	left: 0;
	217	top: -100%;
	218	z-index: 1000;
	219	padding: 0.5rem 1rem;
	220	background-color: var(--main-background-color);
	221	color: var(--main-color);
	222	text-decoration: none;
	223	font-weight: 500;
	224	border-bottom-right-radius: 4px;
	225	outline: 2px solid var(--search-input-focused-border-color);
	226	}
	227	.skip-main-content:focus {
	228	top: 0;
	229	}
	230
213	231	h1 {
214	232	font-size: 1.5rem; /* 24px */
215	233	}
...	...	@@ -1114,6 +1132,7 @@ pre, .rustdoc.src .example-wrap, .example-wrap .src-line-numbers {
1114	1132
1115	1133	#main-content {
1116	1134	position: relative;
	1135	outline: none;
1117	1136	}
1118	1137
1119	1138	.docblock table {

src/librustdoc/html/templates/page.html+2-1

...	...	@@ -66,6 +66,7 @@
66	66	{{ layout.external_html.in_header\|safe }}
67	67	</head> {# #}
68	68	<body class="rustdoc {{+page.css_class}}"> {# #}
	69	<a class="skip-main-content" href="#main-content">Skip to main content</a> {# #}
69	70	<!--[if lte IE 11]> {# #}
70	71	<div class="warning"> {# #}
71	72	This old browser is unsupported and will most likely display funky things. {# #}
...	...	@@ -109,7 +110,7 @@
109	110	<div class="sidebar-resizer" title="Drag to resize sidebar"></div> {# #}
110	111	<main>
111	112	{% if page.css_class != "src" %}<div class="width-limiter">{% endif %}
112		<section id="main-content" class="content">{{ content\|safe }}</section>
	113	<section id="main-content" class="content" tabindex="-1">{{ content\|safe }}</section>
113	114	{% if page.css_class != "src" %}</div>{% endif %}
114	115	</main>
115	116	{{ layout.external_html.after_content\|safe }}

tests/assembly-llvm/slice-is-ascii.rs created+32

...	...	@@ -0,0 +1,32 @@
	1	//@ revisions: X86_64 LA64
	2	//@ assembly-output: emit-asm
	3	//@ compile-flags: -C opt-level=3
	4	//
	5	//@ [X86_64] only-x86_64
	6	//@ [X86_64] compile-flags: -C target-cpu=znver4
	7	//@ [X86_64] compile-flags: -C llvm-args=-x86-asm-syntax=intel
	8	//
	9	//@ [LA64] only-loongarch64
	10
	11	#![crate_type = "lib"]
	12
	13	/// Verify `is_ascii` generates efficient code on different architectures:
	14	///
	15	/// - x86_64: Must NOT use `kshiftrd`/`kshiftrq` (broken AVX-512 auto-vectorization).
	16	/// The fix uses explicit SSE2 intrinsics (`pmovmskb`/`vpmovmskb`).
	17	/// See: https://github.com/llvm/llvm-project/issues/176906
	18	///
	19	/// - loongarch64: Should use `vmskltz.b` instruction for the fast-path.
	20	/// This architecture still relies on LLVM auto-vectorization.
	21
	22	// X86_64-LABEL: test_is_ascii
	23	// X86_64-NOT: kshiftrd
	24	// X86_64-NOT: kshiftrq
	25
	26	// LA64-LABEL: test_is_ascii
	27	// LA64: vmskltz.b
	28
	29	#[no_mangle]
	30	pub fn test_is_ascii(s: &[u8]) -> bool {
	31	s.is_ascii()
	32	}

tests/assembly-llvm/targets/targets-elf.rs+15

...	...	@@ -559,6 +559,21 @@
559	559	//@ revisions: thumbv5te_none_eabi
560	560	//@ [thumbv5te_none_eabi] compile-flags: --target thumbv5te-none-eabi
561	561	//@ [thumbv5te_none_eabi] needs-llvm-components: arm
	562	//@ revisions: thumbv7a_none_eabi
	563	//@ [thumbv7a_none_eabi] compile-flags: --target thumbv7a-none-eabi
	564	//@ [thumbv7a_none_eabi] needs-llvm-components: arm
	565	//@ revisions: thumbv7a_none_eabihf
	566	//@ [thumbv7a_none_eabihf] compile-flags: --target thumbv7a-none-eabihf
	567	//@ [thumbv7a_none_eabihf] needs-llvm-components: arm
	568	//@ revisions: thumbv7r_none_eabi
	569	//@ [thumbv7r_none_eabi] compile-flags: --target thumbv7r-none-eabi
	570	//@ [thumbv7r_none_eabi] needs-llvm-components: arm
	571	//@ revisions: thumbv7r_none_eabihf
	572	//@ [thumbv7r_none_eabihf] compile-flags: --target thumbv7r-none-eabihf
	573	//@ [thumbv7r_none_eabihf] needs-llvm-components: arm
	574	//@ revisions: thumbv8r_none_eabihf
	575	//@ [thumbv8r_none_eabihf] compile-flags: --target thumbv8r-none-eabihf
	576	//@ [thumbv8r_none_eabihf] needs-llvm-components: arm
562	577	//@ revisions: thumbv6m_none_eabi
563	578	//@ [thumbv6m_none_eabi] compile-flags: --target thumbv6m-none-eabi
564	579	//@ [thumbv6m_none_eabi] needs-llvm-components: arm

tests/codegen-llvm/slice-is-ascii.rs deleted-16

...	...	@@ -1,16 +0,0 @@
1		//@ only-x86_64
2		//@ compile-flags: -C opt-level=3 -C target-cpu=x86-64
3		#![crate_type = "lib"]
4
5		/// Check that the fast-path of `is_ascii` uses a `pmovmskb` instruction.
6		/// Platforms lacking an equivalent instruction use other techniques for
7		/// optimizing `is_ascii`.
8		// CHECK-LABEL: @is_ascii_autovectorized
9		#[no_mangle]
10		pub fn is_ascii_autovectorized(s: &[u8]) -> bool {
11		// CHECK: load <32 x i8>
12		// CHECK-NEXT: icmp slt <32 x i8>
13		// CHECK-NEXT: bitcast <32 x i1>
14		// CHECK-NEXT: icmp eq i32
15		s.is_ascii()
16		}

tests/run-make/reproducible-build/rmake.rs+1-5

...	...	@@ -199,13 +199,9 @@ fn diff_dir_test(crate_type: CrateType, remap_type: RemapType) {
199	199	.arg(format!("--remap-path-prefix={}=/b", base_dir.join("test").display()));
200	200	}
201	201	RemapType::Cwd { is_empty } => {
202		// FIXME(Oneirical): Building with crate type set to `bin` AND having -Cdebuginfo=2
203		// (or `-g`, the shorthand form) enabled will cause reproducibility failures
204		// for multiple platforms.
205		// See https://github.com/rust-lang/rust/issues/89911
206	202	// FIXME(#129117): Windows rlib + `-Cdebuginfo=2` + `-Z remap-cwd-prefix=.` seems
207	203	// to be unreproducible.
208		if !matches!(crate_type, CrateType::Bin) && !is_windows() {
	204	if !is_windows() {
209	205	compiler1.arg("-Cdebuginfo=2");
210	206	compiler2.arg("-Cdebuginfo=2");
211	207	}

tests/rustdoc-gui/skip-navigation.goml created+19

...	...	@@ -0,0 +1,19 @@
	1	// This test ensures that the "Skip to main content" link works correctly
	2	// for keyboard navigation (WCAG 2.4.1 compliance).
	3	go-to: "file://" + \|DOC_PATH\| + "/test_docs/index.html"
	4
	5	// The skip link should be hidden initially (positioned off-screen above viewport)
	6	store-position: (".skip-main-content", {"y": y_before})
	7	store-size: (".skip-main-content", {"height": height_before})
	8	assert: \|y_before\| + \|height_before\| < 0
	9
	10	// The skip link should be the first focusable element when pressing Tab
	11	press-key: "Tab"
	12	wait-for: ".skip-main-content:focus"
	13
	14	// When focused, the link should be visible (top: 0px)
	15	assert-css: (".skip-main-content:focus", {"top": "0px"})
	16
	17	// Pressing Enter on the skip link should move focus to main content
	18	press-key: "Enter"
	19	wait-for: "#main-content:focus"

tests/ui/check-cfg/target_feature.stderr+15

...	...	@@ -131,7 +131,21 @@ LL \| cfg!(target_feature = "_UNEXPECTED_VALUE");
131	131	`high-registers`
132	132	`high-word`
133	133	`hvx`
	134	`hvx-ieee-fp`
134	135	`hvx-length128b`
	136	`hvx-length64b`
	137	`hvx-qfloat`
	138	`hvxv60`
	139	`hvxv62`
	140	`hvxv65`
	141	`hvxv66`
	142	`hvxv67`
	143	`hvxv68`
	144	`hvxv69`
	145	`hvxv71`
	146	`hvxv73`
	147	`hvxv75`
	148	`hvxv79`
135	149	`hwdiv`
136	150	`i8mm`
137	151	`isa-68000`
...	...	@@ -431,6 +445,7 @@ LL \| cfg!(target_feature = "_UNEXPECTED_VALUE");
431	445	`zksed`
432	446	`zksh`
433	447	`zkt`
	448	`zreg`
434	449	`ztso`
435	450	`zvbb`
436	451	`zvbc`