authorgravatar for joachim.schmidt557@outlook.comJoachim Schmidt <joachim.schmidt557@outlook.com> 2022-03-12 14:59:29+01:00
committergravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2022-03-12 18:33:25+01:00
log01081ce5a59f4e2e57a9ff6e5885269ed3014279
treef2f4f9f71c1168f60d616bfb4df68466f755c21d
parente5d4a694ea7dd251e10d6434c9321b5e0a548d4b

stage2 x86_64: Fix assertion in getResolvedInstValue

1 files changed, 18 insertions(+), 19 deletions(-)

src/arch/x86_64/CodeGen.zig+18-19
...@@ -3741,8 +3741,6 @@ fn airCondBr(self: *Self, inst: Air.Inst.Index) !void {...@@ -3741,8 +3741,6 @@ fn airCondBr(self: *Self, inst: Air.Inst.Index) !void {
3741 // If the condition dies here in this condbr instruction, process3741 // If the condition dies here in this condbr instruction, process
3742 // that death now instead of later as this has an effect on3742 // that death now instead of later as this has an effect on
3743 // whether it needs to be spilled in the branches3743 // whether it needs to be spilled in the branches
3744 // TODO I need investigate how to make this work without removing
3745 // an assertion from getResolvedInstValue()
3746 if (self.liveness.operandDies(inst, 0)) {3744 if (self.liveness.operandDies(inst, 0)) {
3747 const op_int = @enumToInt(pl_op.operand);3745 const op_int = @enumToInt(pl_op.operand);
3748 if (op_int >= Air.Inst.Ref.typed_value_map.len) {3746 if (op_int >= Air.Inst.Ref.typed_value_map.len) {
...@@ -3869,7 +3867,9 @@ fn airCondBr(self: *Self, inst: Air.Inst.Index) !void {...@@ -3869,7 +3867,9 @@ fn airCondBr(self: *Self, inst: Air.Inst.Index) !void {
38693867
3870 self.branch_stack.pop().deinit(self.gpa);3868 self.branch_stack.pop().deinit(self.gpa);
38713869
3872 return self.finishAir(inst, .unreach, .{ pl_op.operand, .none, .none });3870 // We already took care of pl_op.operand earlier, so we're going
3871 // to pass .none here
3872 return self.finishAir(inst, .unreach, .{ .none, .none, .none });
3873}3873}
38743874
3875fn isNull(self: *Self, inst: Air.Inst.Index, ty: Type, operand: MCValue) !MCValue {3875fn isNull(self: *Self, inst: Air.Inst.Index, ty: Type, operand: MCValue) !MCValue {
...@@ -4194,6 +4194,17 @@ fn airSwitch(self: *Self, inst: Air.Inst.Index) !void {...@@ -4194,6 +4194,17 @@ fn airSwitch(self: *Self, inst: Air.Inst.Index) !void {
4194 );4194 );
4195 defer self.gpa.free(liveness.deaths);4195 defer self.gpa.free(liveness.deaths);
41964196
4197 // If the condition dies here in this switch instruction, process
4198 // that death now instead of later as this has an effect on
4199 // whether it needs to be spilled in the branches
4200 if (self.liveness.operandDies(inst, 0)) {
4201 const op_int = @enumToInt(pl_op.operand);
4202 if (op_int >= Air.Inst.Ref.typed_value_map.len) {
4203 const op_index = @intCast(Air.Inst.Index, op_int - Air.Inst.Ref.typed_value_map.len);
4204 self.processDeath(op_index);
4205 }
4206 }
4207
4197 while (case_i < switch_br.data.cases_len) : (case_i += 1) {4208 while (case_i < switch_br.data.cases_len) : (case_i += 1) {
4198 const case = self.air.extraData(Air.SwitchBr.Case, extra_index);4209 const case = self.air.extraData(Air.SwitchBr.Case, extra_index);
4199 const items = @bitCast([]const Air.Inst.Ref, self.air.extra[case.end..][0..case.data.items_len]);4210 const items = @bitCast([]const Air.Inst.Ref, self.air.extra[case.end..][0..case.data.items_len]);
...@@ -4208,19 +4219,6 @@ fn airSwitch(self: *Self, inst: Air.Inst.Index) !void {...@@ -4208,19 +4219,6 @@ fn airSwitch(self: *Self, inst: Air.Inst.Index) !void {
4208 relocs[item_i] = try self.genCondSwitchMir(condition_ty, condition, item_mcv);4219 relocs[item_i] = try self.genCondSwitchMir(condition_ty, condition, item_mcv);
4209 }4220 }
42104221
4211 // If the condition dies here in this condbr instruction, process
4212 // that death now instead of later as this has an effect on
4213 // whether it needs to be spilled in the branches
4214 // TODO I need investigate how to make this work without removing
4215 // an assertion from getResolvedInstValue()
4216 if (self.liveness.operandDies(inst, 0)) {
4217 const op_int = @enumToInt(pl_op.operand);
4218 if (op_int >= Air.Inst.Ref.typed_value_map.len) {
4219 const op_index = @intCast(Air.Inst.Index, op_int - Air.Inst.Ref.typed_value_map.len);
4220 self.processDeath(op_index);
4221 }
4222 }
4223
4224 // Capture the state of register and stack allocation state so that we can revert to it.4222 // Capture the state of register and stack allocation state so that we can revert to it.
4225 const parent_next_stack_offset = self.next_stack_offset;4223 const parent_next_stack_offset = self.next_stack_offset;
4226 const parent_free_registers = self.register_manager.free_registers;4224 const parent_free_registers = self.register_manager.free_registers;
...@@ -4276,7 +4274,9 @@ fn airSwitch(self: *Self, inst: Air.Inst.Index) !void {...@@ -4276,7 +4274,9 @@ fn airSwitch(self: *Self, inst: Air.Inst.Index) !void {
4276 // in airCondBr.4274 // in airCondBr.
4277 }4275 }
42784276
4279 return self.finishAir(inst, .unreach, .{ pl_op.operand, .none, .none });4277 // We already took care of pl_op.operand earlier, so we're going
4278 // to pass .none here
4279 return self.finishAir(inst, .unreach, .{ .none, .none, .none });
4280}4280}
42814281
4282fn performReloc(self: *Self, reloc: Mir.Inst.Index) !void {4282fn performReloc(self: *Self, reloc: Mir.Inst.Index) !void {
...@@ -5630,8 +5630,7 @@ fn getResolvedInstValue(self: *Self, inst: Air.Inst.Index) MCValue {...@@ -5630,8 +5630,7 @@ fn getResolvedInstValue(self: *Self, inst: Air.Inst.Index) MCValue {
5630 while (true) {5630 while (true) {
5631 i -= 1;5631 i -= 1;
5632 if (self.branch_stack.items[i].inst_table.get(inst)) |mcv| {5632 if (self.branch_stack.items[i].inst_table.get(inst)) |mcv| {
5633 // TODO see comment in `airCondBr` and `airSwitch`5633 assert(mcv != .dead);
5634 // assert(mcv != .dead);
5635 return mcv;5634 return mcv;
5636 }5635 }
5637 }5636 }