authorgravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2022-05-12 20:52:52+02:00
committergravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2022-05-19 19:36:35+02:00
log019cc94ec7291c652b3e18980194e028f8df9ec1
tree33ef6ce1fe00ea5217ffdd09cdbc7cc2e168957b
parent875a16030c2e58f9f8b9a2b66b43b565e3932cf5

x64: clean up populating VEX prefix

2 files changed, 222 insertions(+), 201 deletions(-)

src/arch/x86_64/Emit.zig+105-112
......@@ -249,7 +249,7 @@ fn mirPushPop(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
249249 switch (ops.flags) {
250250 0b00 => {
251251 // PUSH/POP reg
252 return lowerToOEnc(tag, .{ .register = ops.reg1 }, emit.code);
252 return lowerToOEnc(tag, Register.reg(ops.reg1), emit.code);
253253 },
254254 0b01 => {
255255 // PUSH/POP r/m64
......@@ -285,9 +285,9 @@ fn mirPushPopRegsFromCalleePreservedRegs(emit: *Emit, tag: Tag, inst: Mir.Inst.I
285285 try lowerToMrEnc(.mov, RegisterOrMemory.mem(.qword_ptr, .{
286286 .disp = @bitCast(u32, -@intCast(i32, disp)),
287287 .base = ops.reg1,
288 }), .{ .register = reg.to64() }, emit.code);
288 }), Register.reg(reg.to64()), emit.code);
289289 } else {
290 try lowerToRmEnc(.mov, .{ .register = reg.to64() }, RegisterOrMemory.mem(.qword_ptr, .{
290 try lowerToRmEnc(.mov, Register.reg(reg.to64()), RegisterOrMemory.mem(.qword_ptr, .{
291291 .disp = @bitCast(u32, -@intCast(i32, disp)),
292292 .base = ops.reg1,
293293 }), emit.code);
......@@ -321,7 +321,7 @@ fn mirJmpCall(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
321321 return lowerToMEnc(tag, RegisterOrMemory.mem(ptr_size, .{ .disp = imm }), emit.code);
322322 }
323323 // JMP/CALL reg
324 return lowerToMEnc(tag, RegisterOrMemory.reg(.{ .register = ops.reg1 }), emit.code);
324 return lowerToMEnc(tag, RegisterOrMemory.reg(ops.reg1), emit.code);
325325 },
326326 0b10 => {
327327 // JMP/CALL r/m64
......@@ -394,13 +394,13 @@ fn mirCondSetByte(emit: *Emit, mir_tag: Mir.Inst.Tag, inst: Mir.Inst.Index) Inne
394394 },
395395 else => unreachable,
396396 };
397 return lowerToMEnc(tag, RegisterOrMemory.reg(.{ .register = ops.reg1.to8() }), emit.code);
397 return lowerToMEnc(tag, RegisterOrMemory.reg(ops.reg1.to8()), emit.code);
398398}
399399
400400fn mirCondMov(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
401401 const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
402402 if (ops.flags == 0b00) {
403 return lowerToRmEnc(tag, .{ .register = ops.reg1 }, RegisterOrMemory.reg(.{ .register = ops.reg2 }), emit.code);
403 return lowerToRmEnc(tag, Register.reg(ops.reg1), RegisterOrMemory.reg(ops.reg2), emit.code);
404404 }
405405 const imm = emit.mir.instructions.items(.data)[inst].imm;
406406 const ptr_size: Memory.PtrSize = switch (ops.flags) {
......@@ -409,7 +409,7 @@ fn mirCondMov(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
409409 0b10 => .dword_ptr,
410410 0b11 => .qword_ptr,
411411 };
412 return lowerToRmEnc(tag, .{ .register = ops.reg1 }, RegisterOrMemory.mem(ptr_size, .{
412 return lowerToRmEnc(tag, Register.reg(ops.reg1), RegisterOrMemory.mem(ptr_size, .{
413413 .disp = imm,
414414 .base = ops.reg2,
415415 }), emit.code);
......@@ -430,13 +430,13 @@ fn mirTest(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
430430 // I
431431 return lowerToIEnc(.@"test", imm, emit.code);
432432 }
433 return lowerToMiEnc(.@"test", RegisterOrMemory.reg(.{ .register = ops.reg1 }), imm, emit.code);
433 return lowerToMiEnc(.@"test", RegisterOrMemory.reg(ops.reg1), imm, emit.code);
434434 }
435435 // TEST r/m64, r64
436436 return lowerToMrEnc(
437437 .@"test",
438 RegisterOrMemory.reg(.{ .register = ops.reg1 }),
439 .{ .register = ops.reg2 },
438 RegisterOrMemory.reg(ops.reg1),
439 Register.reg(ops.reg2),
440440 emit.code,
441441 );
442442 },
......@@ -478,18 +478,18 @@ fn mirArith(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
478478 // mov reg1, imm32
479479 // MI
480480 const imm = emit.mir.instructions.items(.data)[inst].imm;
481 return lowerToMiEnc(tag, RegisterOrMemory.reg(.{ .register = ops.reg1 }), imm, emit.code);
481 return lowerToMiEnc(tag, RegisterOrMemory.reg(ops.reg1), imm, emit.code);
482482 }
483483 // mov reg1, reg2
484484 // RM
485 return lowerToRmEnc(tag, .{ .register = ops.reg1 }, RegisterOrMemory.reg(.{ .register = ops.reg2 }), emit.code);
485 return lowerToRmEnc(tag, Register.reg(ops.reg1), RegisterOrMemory.reg(ops.reg2), emit.code);
486486 },
487487 0b01 => {
488488 // mov reg1, [reg2 + imm32]
489489 // RM
490490 const imm = emit.mir.instructions.items(.data)[inst].imm;
491491 const src_reg: ?GpRegister = if (ops.reg2 == .none) null else ops.reg2;
492 return lowerToRmEnc(tag, .{ .register = ops.reg1 }, RegisterOrMemory.mem(Memory.PtrSize.fromBits(ops.reg1.size()), .{
492 return lowerToRmEnc(tag, Register.reg(ops.reg1), RegisterOrMemory.mem(Memory.PtrSize.fromBits(ops.reg1.size()), .{
493493 .disp = imm,
494494 .base = src_reg,
495495 }), emit.code);
......@@ -504,7 +504,7 @@ fn mirArith(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
504504 return lowerToMrEnc(tag, RegisterOrMemory.mem(Memory.PtrSize.fromBits(ops.reg2.size()), .{
505505 .disp = imm,
506506 .base = ops.reg1,
507 }), .{ .register = ops.reg2 }, emit.code);
507 }), Register.reg(ops.reg2), emit.code);
508508 },
509509 0b11 => {
510510 return emit.fail("TODO unused variant: mov reg1, reg2, 0b11", .{});
......@@ -562,7 +562,7 @@ fn mirArithScaleSrc(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void
562562 .scale = scale,
563563 .index = .rcx,
564564 };
565 return lowerToRmEnc(tag, .{ .register = ops.reg1 }, RegisterOrMemory.mem(Memory.PtrSize.fromBits(ops.reg1.size()), .{
565 return lowerToRmEnc(tag, Register.reg(ops.reg1), RegisterOrMemory.mem(Memory.PtrSize.fromBits(ops.reg1.size()), .{
566566 .disp = imm,
567567 .base = ops.reg2,
568568 .scale_index = scale_index,
......@@ -590,7 +590,7 @@ fn mirArithScaleDst(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void
590590 .disp = imm,
591591 .base = ops.reg1,
592592 .scale_index = scale_index,
593 }), .{ .register = ops.reg2 }, emit.code);
593 }), Register.reg(ops.reg2), emit.code);
594594}
595595
596596fn mirArithScaleImm(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
......@@ -641,27 +641,22 @@ fn mirMovSignExtend(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
641641 switch (ops.flags) {
642642 0b00 => {
643643 const tag: Tag = if (ops.reg2.size() == 32) .movsxd else .movsx;
644 return lowerToRmEnc(
645 tag,
646 .{ .register = ops.reg1 },
647 RegisterOrMemory.reg(.{ .register = ops.reg2 }),
648 emit.code,
649 );
644 return lowerToRmEnc(tag, Register.reg(ops.reg1), RegisterOrMemory.reg(ops.reg2), emit.code);
650645 },
651646 0b01 => {
652 return lowerToRmEnc(.movsx, .{ .register = ops.reg1 }, RegisterOrMemory.mem(.byte_ptr, .{
647 return lowerToRmEnc(.movsx, Register.reg(ops.reg1), RegisterOrMemory.mem(.byte_ptr, .{
653648 .disp = imm,
654649 .base = ops.reg2,
655650 }), emit.code);
656651 },
657652 0b10 => {
658 return lowerToRmEnc(.movsx, .{ .register = ops.reg1 }, RegisterOrMemory.mem(.word_ptr, .{
653 return lowerToRmEnc(.movsx, Register.reg(ops.reg1), RegisterOrMemory.mem(.word_ptr, .{
659654 .disp = imm,
660655 .base = ops.reg2,
661656 }), emit.code);
662657 },
663658 0b11 => {
664 return lowerToRmEnc(.movsxd, .{ .register = ops.reg1 }, RegisterOrMemory.mem(.dword_ptr, .{
659 return lowerToRmEnc(.movsxd, Register.reg(ops.reg1), RegisterOrMemory.mem(.dword_ptr, .{
665660 .disp = imm,
666661 .base = ops.reg2,
667662 }), emit.code);
......@@ -676,21 +671,16 @@ fn mirMovZeroExtend(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
676671 const imm = if (ops.flags != 0b00) emit.mir.instructions.items(.data)[inst].imm else undefined;
677672 switch (ops.flags) {
678673 0b00 => {
679 return lowerToRmEnc(
680 .movzx,
681 .{ .register = ops.reg1 },
682 RegisterOrMemory.reg(.{ .register = ops.reg2 }),
683 emit.code,
684 );
674 return lowerToRmEnc(.movzx, Register.reg(ops.reg1), RegisterOrMemory.reg(ops.reg2), emit.code);
685675 },
686676 0b01 => {
687 return lowerToRmEnc(.movzx, .{ .register = ops.reg1 }, RegisterOrMemory.mem(.byte_ptr, .{
677 return lowerToRmEnc(.movzx, Register.reg(ops.reg1), RegisterOrMemory.mem(.byte_ptr, .{
688678 .disp = imm,
689679 .base = ops.reg2,
690680 }), emit.code);
691681 },
692682 0b10 => {
693 return lowerToRmEnc(.movzx, .{ .register = ops.reg1 }, RegisterOrMemory.mem(.word_ptr, .{
683 return lowerToRmEnc(.movzx, Register.reg(ops.reg1), RegisterOrMemory.mem(.word_ptr, .{
694684 .disp = imm,
695685 .base = ops.reg2,
696686 }), emit.code);
......@@ -713,16 +703,16 @@ fn mirMovabs(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
713703 if (ops.flags == 0b00) {
714704 // movabs reg, imm64
715705 // OI
716 return lowerToOiEnc(.mov, .{ .register = ops.reg1 }, imm, emit.code);
706 return lowerToOiEnc(.mov, Register.reg(ops.reg1), imm, emit.code);
717707 }
718708 if (ops.reg1 == .none) {
719709 // movabs moffs64, rax
720710 // TD
721 return lowerToTdEnc(.mov, imm, .{ .register = ops.reg2 }, emit.code);
711 return lowerToTdEnc(.mov, imm, Register.reg(ops.reg2), emit.code);
722712 }
723713 // movabs rax, moffs64
724714 // FD
725 return lowerToFdEnc(.mov, .{ .register = ops.reg1 }, imm, emit.code);
715 return lowerToFdEnc(.mov, Register.reg(ops.reg1), imm, emit.code);
726716}
727717
728718fn mirFisttp(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
......@@ -773,18 +763,18 @@ fn mirShift(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
773763 0b00 => {
774764 // sal reg1, 1
775765 // M1
776 return lowerToM1Enc(tag, RegisterOrMemory.reg(.{ .register = ops.reg1 }), emit.code);
766 return lowerToM1Enc(tag, RegisterOrMemory.reg(ops.reg1), emit.code);
777767 },
778768 0b01 => {
779769 // sal reg1, .cl
780770 // MC
781 return lowerToMcEnc(tag, RegisterOrMemory.reg(.{ .register = ops.reg1 }), emit.code);
771 return lowerToMcEnc(tag, RegisterOrMemory.reg(ops.reg1), emit.code);
782772 },
783773 0b10 => {
784774 // sal reg1, imm8
785775 // MI
786776 const imm = @truncate(u8, emit.mir.instructions.items(.data)[inst].imm);
787 return lowerToMiImm8Enc(tag, RegisterOrMemory.reg(.{ .register = ops.reg1 }), imm, emit.code);
777 return lowerToMiImm8Enc(tag, RegisterOrMemory.reg(ops.reg1), imm, emit.code);
788778 },
789779 0b11 => {
790780 return emit.fail("TODO unused variant: SHIFT reg1, 0b11", .{});
......@@ -796,7 +786,7 @@ fn mirMulDiv(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
796786 const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
797787 if (ops.reg1 != .none) {
798788 assert(ops.reg2 == .none);
799 return lowerToMEnc(tag, RegisterOrMemory.reg(.{ .register = ops.reg1 }), emit.code);
789 return lowerToMEnc(tag, RegisterOrMemory.reg(ops.reg1), emit.code);
800790 }
801791 assert(ops.reg1 == .none);
802792 assert(ops.reg2 != .none);
......@@ -819,35 +809,24 @@ fn mirIMulComplex(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
819809 const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);
820810 switch (ops.flags) {
821811 0b00 => {
822 return lowerToRmEnc(
823 .imul,
824 .{ .register = ops.reg1 },
825 RegisterOrMemory.reg(.{ .register = ops.reg2 }),
826 emit.code,
827 );
812 return lowerToRmEnc(.imul, Register.reg(ops.reg1), RegisterOrMemory.reg(ops.reg2), emit.code);
828813 },
829814 0b01 => {
830815 const imm = emit.mir.instructions.items(.data)[inst].imm;
831816 const src_reg: ?GpRegister = if (ops.reg2 == .none) null else ops.reg2;
832 return lowerToRmEnc(.imul, .{ .register = ops.reg1 }, RegisterOrMemory.mem(.qword_ptr, .{
817 return lowerToRmEnc(.imul, Register.reg(ops.reg1), RegisterOrMemory.mem(.qword_ptr, .{
833818 .disp = imm,
834819 .base = src_reg,
835820 }), emit.code);
836821 },
837822 0b10 => {
838823 const imm = emit.mir.instructions.items(.data)[inst].imm;
839 return lowerToRmiEnc(
840 .imul,
841 .{ .register = ops.reg1 },
842 RegisterOrMemory.reg(.{ .register = ops.reg2 }),
843 imm,
844 emit.code,
845 );
824 return lowerToRmiEnc(.imul, Register.reg(ops.reg1), RegisterOrMemory.reg(ops.reg2), imm, emit.code);
846825 },
847826 0b11 => {
848827 const payload = emit.mir.instructions.items(.data)[inst].payload;
849828 const imm_pair = emit.mir.extraData(Mir.ImmPair, payload).data;
850 return lowerToRmiEnc(.imul, .{ .register = ops.reg1 }, RegisterOrMemory.mem(.qword_ptr, .{
829 return lowerToRmiEnc(.imul, Register.reg(ops.reg1), RegisterOrMemory.mem(.qword_ptr, .{
851830 .disp = imm_pair.dest_off,
852831 .base = ops.reg2,
853832 }), imm_pair.operand, emit.code);
......@@ -878,7 +857,7 @@ fn mirLea(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
878857 const src_reg: ?GpRegister = if (ops.reg2 == .none) null else ops.reg2;
879858 return lowerToRmEnc(
880859 .lea,
881 .{ .register = ops.reg1 },
860 Register.reg(ops.reg1),
882861 RegisterOrMemory.mem(Memory.PtrSize.fromBits(ops.reg1.size()), .{
883862 .disp = imm,
884863 .base = src_reg,
......@@ -892,7 +871,7 @@ fn mirLea(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
892871 const start_offset = emit.code.items.len;
893872 try lowerToRmEnc(
894873 .lea,
895 .{ .register = ops.reg1 },
874 Register.reg(ops.reg1),
896875 RegisterOrMemory.rip(Memory.PtrSize.fromBits(ops.reg1.size()), 0),
897876 emit.code,
898877 );
......@@ -913,7 +892,7 @@ fn mirLea(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
913892 };
914893 return lowerToRmEnc(
915894 .lea,
916 .{ .register = ops.reg1 },
895 Register.reg(ops.reg1),
917896 RegisterOrMemory.mem(Memory.PtrSize.fromBits(ops.reg1.size()), .{
918897 .disp = imm,
919898 .base = src_reg,
......@@ -936,7 +915,7 @@ fn mirLeaPie(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
936915 // RM
937916 try lowerToRmEnc(
938917 .lea,
939 .{ .register = ops.reg1 },
918 Register.reg(ops.reg1),
940919 RegisterOrMemory.rip(Memory.PtrSize.fromBits(ops.reg1.size()), 0),
941920 emit.code,
942921 );
......@@ -1666,8 +1645,12 @@ const RegisterOrMemory = union(enum) {
16661645 register: Register,
16671646 memory: Memory,
16681647
1669 fn reg(register: Register) RegisterOrMemory {
1670 return .{ .register = register };
1648 fn reg(register: GpRegister) RegisterOrMemory {
1649 return .{ .register = Register.reg(register) };
1650 }
1651
1652 fn avxReg(register: AvxRegister) RegisterOrMemory {
1653 return .{ .register = Register.avxReg(register) };
16711654 }
16721655
16731656 fn mem(ptr_size: Memory.PtrSize, args: struct {
......@@ -1976,22 +1959,32 @@ fn lowerToMrEnc(
19761959 encoder.modRm_direct(reg.lowId(), dst_reg.lowId());
19771960 },
19781961 .memory => |dst_mem| {
1979 const encoder = try Encoder.init(code, 9);
1980 if (reg.size() == 16) {
1981 encoder.prefix16BitMode();
1982 }
1983 if (dst_mem.base) |base| {
1984 encoder.rex(.{
1985 .w = dst_mem.ptr_size == .qword_ptr or setRexWRegister(reg),
1986 .r = reg.isExtended(),
1987 .b = base.isExtended(),
1988 });
1989 } else {
1990 encoder.rex(.{
1991 .w = dst_mem.ptr_size == .qword_ptr or setRexWRegister(reg),
1992 .r = reg.isExtended(),
1993 });
1994 }
1962 const encoder = blk: {
1963 switch (reg) {
1964 .register => {
1965 const encoder = try Encoder.init(code, 9);
1966 if (reg.size() == 16) {
1967 encoder.prefix16BitMode();
1968 }
1969 if (dst_mem.base) |base| {
1970 encoder.rex(.{
1971 .w = dst_mem.ptr_size == .qword_ptr or setRexWRegister(reg),
1972 .r = reg.isExtended(),
1973 .b = base.isExtended(),
1974 });
1975 } else {
1976 encoder.rex(.{
1977 .w = dst_mem.ptr_size == .qword_ptr or setRexWRegister(reg),
1978 .r = reg.isExtended(),
1979 });
1980 }
1981 break :blk encoder;
1982 },
1983 .avx_register => {
1984 unreachable;
1985 },
1986 }
1987 };
19951988 opc.encode(encoder);
19961989 dst_mem.encode(encoder, reg.lowId());
19971990 },
......@@ -2168,23 +2161,23 @@ test "lower MI encoding" {
21682161test "lower RM encoding" {
21692162 var emit = TestEmit.init();
21702163 defer emit.deinit();
2171 try lowerToRmEnc(.mov, .rax, RegisterOrMemory.reg(.rbx), emit.code());
2164 try lowerToRmEnc(.mov, Register.reg(.rax), RegisterOrMemory.reg(.rbx), emit.code());
21722165 try expectEqualHexStrings("\x48\x8b\xc3", emit.lowered(), "mov rax, rbx");
2173 try lowerToRmEnc(.mov, .rax, RegisterOrMemory.mem(.qword_ptr, .{ .disp = 0, .base = .r11 }), emit.code());
2166 try lowerToRmEnc(.mov, Register.reg(.rax), RegisterOrMemory.mem(.qword_ptr, .{ .disp = 0, .base = .r11 }), emit.code());
21742167 try expectEqualHexStrings("\x49\x8b\x03", emit.lowered(), "mov rax, qword ptr [r11 + 0]");
2175 try lowerToRmEnc(.add, .r11, RegisterOrMemory.mem(.qword_ptr, .{ .disp = 0x10000000 }), emit.code());
2168 try lowerToRmEnc(.add, Register.reg(.r11), RegisterOrMemory.mem(.qword_ptr, .{ .disp = 0x10000000 }), emit.code());
21762169 try expectEqualHexStrings(
21772170 "\x4C\x03\x1C\x25\x00\x00\x00\x10",
21782171 emit.lowered(),
21792172 "add r11, qword ptr [ds:0x10000000]",
21802173 );
2181 try lowerToRmEnc(.add, .r12b, RegisterOrMemory.mem(.byte_ptr, .{ .disp = 0x10000000 }), emit.code());
2174 try lowerToRmEnc(.add, Register.reg(.r12b), RegisterOrMemory.mem(.byte_ptr, .{ .disp = 0x10000000 }), emit.code());
21822175 try expectEqualHexStrings(
21832176 "\x44\x02\x24\x25\x00\x00\x00\x10",
21842177 emit.lowered(),
21852178 "add r11b, byte ptr [ds:0x10000000]",
21862179 );
2187 try lowerToRmEnc(.sub, .r11, RegisterOrMemory.mem(.qword_ptr, .{
2180 try lowerToRmEnc(.sub, Register.reg(.r11), RegisterOrMemory.mem(.qword_ptr, .{
21882181 .disp = 0x10000000,
21892182 .base = .r13,
21902183 }), emit.code());
......@@ -2193,7 +2186,7 @@ test "lower RM encoding" {
21932186 emit.lowered(),
21942187 "sub r11, qword ptr [r13 + 0x10000000]",
21952188 );
2196 try lowerToRmEnc(.sub, .r11, RegisterOrMemory.mem(.qword_ptr, .{
2189 try lowerToRmEnc(.sub, Register.reg(.r11), RegisterOrMemory.mem(.qword_ptr, .{
21972190 .disp = 0x10000000,
21982191 .base = .r12,
21992192 }), emit.code());
......@@ -2202,14 +2195,14 @@ test "lower RM encoding" {
22022195 emit.lowered(),
22032196 "sub r11, qword ptr [r12 + 0x10000000]",
22042197 );
2205 try lowerToRmEnc(.mov, .rax, RegisterOrMemory.mem(.qword_ptr, .{
2198 try lowerToRmEnc(.mov, Register.reg(.rax), RegisterOrMemory.mem(.qword_ptr, .{
22062199 .disp = @bitCast(u32, @as(i32, -4)),
22072200 .base = .rbp,
22082201 }), emit.code());
22092202 try expectEqualHexStrings("\x48\x8B\x45\xFC", emit.lowered(), "mov rax, qword ptr [rbp - 4]");
2210 try lowerToRmEnc(.lea, .rax, RegisterOrMemory.rip(.qword_ptr, 0x10), emit.code());
2203 try lowerToRmEnc(.lea, Register.reg(.rax), RegisterOrMemory.rip(.qword_ptr, 0x10), emit.code());
22112204 try expectEqualHexStrings("\x48\x8D\x05\x10\x00\x00\x00", emit.lowered(), "lea rax, [rip + 0x10]");
2212 try lowerToRmEnc(.mov, .rax, RegisterOrMemory.mem(.qword_ptr, .{
2205 try lowerToRmEnc(.mov, Register.reg(.rax), RegisterOrMemory.mem(.qword_ptr, .{
22132206 .disp = @bitCast(u32, @as(i32, -8)),
22142207 .base = .rbp,
22152208 .scale_index = .{
......@@ -2218,7 +2211,7 @@ test "lower RM encoding" {
22182211 },
22192212 }), emit.code());
22202213 try expectEqualHexStrings("\x48\x8B\x44\x0D\xF8", emit.lowered(), "mov rax, qword ptr [rbp + rcx*1 - 8]");
2221 try lowerToRmEnc(.mov, .eax, RegisterOrMemory.mem(.dword_ptr, .{
2214 try lowerToRmEnc(.mov, Register.reg(.eax), RegisterOrMemory.mem(.dword_ptr, .{
22222215 .disp = @bitCast(u32, @as(i32, -4)),
22232216 .base = .rbp,
22242217 .scale_index = .{
......@@ -2227,7 +2220,7 @@ test "lower RM encoding" {
22272220 },
22282221 }), emit.code());
22292222 try expectEqualHexStrings("\x8B\x44\x95\xFC", emit.lowered(), "mov eax, dword ptr [rbp + rdx*4 - 4]");
2230 try lowerToRmEnc(.mov, .rax, RegisterOrMemory.mem(.qword_ptr, .{
2223 try lowerToRmEnc(.mov, Register.reg(.rax), RegisterOrMemory.mem(.qword_ptr, .{
22312224 .disp = @bitCast(u32, @as(i32, -8)),
22322225 .base = .rbp,
22332226 .scale_index = .{
......@@ -2236,7 +2229,7 @@ test "lower RM encoding" {
22362229 },
22372230 }), emit.code());
22382231 try expectEqualHexStrings("\x48\x8B\x44\xCD\xF8", emit.lowered(), "mov rax, qword ptr [rbp + rcx*8 - 8]");
2239 try lowerToRmEnc(.mov, .r8b, RegisterOrMemory.mem(.byte_ptr, .{
2232 try lowerToRmEnc(.mov, Register.reg(.r8b), RegisterOrMemory.mem(.byte_ptr, .{
22402233 .disp = @bitCast(u32, @as(i32, -24)),
22412234 .base = .rsi,
22422235 .scale_index = .{
......@@ -2245,7 +2238,7 @@ test "lower RM encoding" {
22452238 },
22462239 }), emit.code());
22472240 try expectEqualHexStrings("\x44\x8A\x44\x0E\xE8", emit.lowered(), "mov r8b, byte ptr [rsi + rcx*1 - 24]");
2248 try lowerToRmEnc(.lea, .rsi, RegisterOrMemory.mem(.qword_ptr, .{
2241 try lowerToRmEnc(.lea, Register.reg(.rsi), RegisterOrMemory.mem(.qword_ptr, .{
22492242 .disp = 0,
22502243 .base = .rbp,
22512244 .scale_index = .{
......@@ -2259,20 +2252,20 @@ test "lower RM encoding" {
22592252test "lower MR encoding" {
22602253 var emit = TestEmit.init();
22612254 defer emit.deinit();
2262 try lowerToMrEnc(.mov, RegisterOrMemory.reg(.rax), .rbx, emit.code());
2255 try lowerToMrEnc(.mov, RegisterOrMemory.reg(.rax), Register.reg(.rbx), emit.code());
22632256 try expectEqualHexStrings("\x48\x89\xd8", emit.lowered(), "mov rax, rbx");
22642257 try lowerToMrEnc(.mov, RegisterOrMemory.mem(.qword_ptr, .{
22652258 .disp = @bitCast(u32, @as(i32, -4)),
22662259 .base = .rbp,
2267 }), .r11, emit.code());
2260 }), Register.reg(.r11), emit.code());
22682261 try expectEqualHexStrings("\x4c\x89\x5d\xfc", emit.lowered(), "mov qword ptr [rbp - 4], r11");
2269 try lowerToMrEnc(.add, RegisterOrMemory.mem(.byte_ptr, .{ .disp = 0x10000000 }), .r12b, emit.code());
2262 try lowerToMrEnc(.add, RegisterOrMemory.mem(.byte_ptr, .{ .disp = 0x10000000 }), Register.reg(.r12b), emit.code());
22702263 try expectEqualHexStrings(
22712264 "\x44\x00\x24\x25\x00\x00\x00\x10",
22722265 emit.lowered(),
22732266 "add byte ptr [ds:0x10000000], r12b",
22742267 );
2275 try lowerToMrEnc(.add, RegisterOrMemory.mem(.dword_ptr, .{ .disp = 0x10000000 }), .r12d, emit.code());
2268 try lowerToMrEnc(.add, RegisterOrMemory.mem(.dword_ptr, .{ .disp = 0x10000000 }), Register.reg(.r12d), emit.code());
22762269 try expectEqualHexStrings(
22772270 "\x44\x01\x24\x25\x00\x00\x00\x10",
22782271 emit.lowered(),
......@@ -2281,53 +2274,53 @@ test "lower MR encoding" {
22812274 try lowerToMrEnc(.sub, RegisterOrMemory.mem(.qword_ptr, .{
22822275 .disp = 0x10000000,
22832276 .base = .r11,
2284 }), .r12, emit.code());
2277 }), Register.reg(.r12), emit.code());
22852278 try expectEqualHexStrings(
22862279 "\x4D\x29\xA3\x00\x00\x00\x10",
22872280 emit.lowered(),
22882281 "sub qword ptr [r11 + 0x10000000], r12",
22892282 );
2290 try lowerToMrEnc(.mov, RegisterOrMemory.rip(.qword_ptr, 0x10), .r12, emit.code());
2283 try lowerToMrEnc(.mov, RegisterOrMemory.rip(.qword_ptr, 0x10), Register.reg(.r12), emit.code());
22912284 try expectEqualHexStrings("\x4C\x89\x25\x10\x00\x00\x00", emit.lowered(), "mov qword ptr [rip + 0x10], r12");
22922285}
22932286
22942287test "lower OI encoding" {
22952288 var emit = TestEmit.init();
22962289 defer emit.deinit();
2297 try lowerToOiEnc(.mov, .rax, 0x1000000000000000, emit.code());
2290 try lowerToOiEnc(.mov, Register.reg(.rax), 0x1000000000000000, emit.code());
22982291 try expectEqualHexStrings(
22992292 "\x48\xB8\x00\x00\x00\x00\x00\x00\x00\x10",
23002293 emit.lowered(),
23012294 "movabs rax, 0x1000000000000000",
23022295 );
2303 try lowerToOiEnc(.mov, .r11, 0x1000000000000000, emit.code());
2296 try lowerToOiEnc(.mov, Register.reg(.r11), 0x1000000000000000, emit.code());
23042297 try expectEqualHexStrings(
23052298 "\x49\xBB\x00\x00\x00\x00\x00\x00\x00\x10",
23062299 emit.lowered(),
23072300 "movabs r11, 0x1000000000000000",
23082301 );
2309 try lowerToOiEnc(.mov, .r11d, 0x10000000, emit.code());
2302 try lowerToOiEnc(.mov, Register.reg(.r11d), 0x10000000, emit.code());
23102303 try expectEqualHexStrings("\x41\xBB\x00\x00\x00\x10", emit.lowered(), "mov r11d, 0x10000000");
2311 try lowerToOiEnc(.mov, .r11w, 0x1000, emit.code());
2304 try lowerToOiEnc(.mov, Register.reg(.r11w), 0x1000, emit.code());
23122305 try expectEqualHexStrings("\x66\x41\xBB\x00\x10", emit.lowered(), "mov r11w, 0x1000");
2313 try lowerToOiEnc(.mov, .r11b, 0x10, emit.code());
2306 try lowerToOiEnc(.mov, Register.reg(.r11b), 0x10, emit.code());
23142307 try expectEqualHexStrings("\x41\xB3\x10", emit.lowered(), "mov r11b, 0x10");
23152308}
23162309
23172310test "lower FD/TD encoding" {
23182311 var emit = TestEmit.init();
23192312 defer emit.deinit();
2320 try lowerToFdEnc(.mov, .rax, 0x1000000000000000, emit.code());
2313 try lowerToFdEnc(.mov, Register.reg(.rax), 0x1000000000000000, emit.code());
23212314 try expectEqualHexStrings(
23222315 "\x48\xa1\x00\x00\x00\x00\x00\x00\x00\x10",
23232316 emit.lowered(),
23242317 "mov rax, ds:0x1000000000000000",
23252318 );
2326 try lowerToFdEnc(.mov, .eax, 0x10000000, emit.code());
2319 try lowerToFdEnc(.mov, Register.reg(.eax), 0x10000000, emit.code());
23272320 try expectEqualHexStrings("\xa1\x00\x00\x00\x10", emit.lowered(), "mov eax, ds:0x10000000");
2328 try lowerToFdEnc(.mov, .ax, 0x1000, emit.code());
2321 try lowerToFdEnc(.mov, Register.reg(.ax), 0x1000, emit.code());
23292322 try expectEqualHexStrings("\x66\xa1\x00\x10", emit.lowered(), "mov ax, ds:0x1000");
2330 try lowerToFdEnc(.mov, .al, 0x10, emit.code());
2323 try lowerToFdEnc(.mov, Register.reg(.al), 0x10, emit.code());
23312324 try expectEqualHexStrings("\xa0\x10", emit.lowered(), "mov al, ds:0x10");
23322325}
23332326
......@@ -2403,16 +2396,16 @@ test "lower M1 and MC encodings" {
24032396test "lower O encoding" {
24042397 var emit = TestEmit.init();
24052398 defer emit.deinit();
2406 try lowerToOEnc(.pop, .r12, emit.code());
2399 try lowerToOEnc(.pop, Register.reg(.r12), emit.code());
24072400 try expectEqualHexStrings("\x41\x5c", emit.lowered(), "pop r12");
2408 try lowerToOEnc(.push, .r12w, emit.code());
2401 try lowerToOEnc(.push, Register.reg(.r12w), emit.code());
24092402 try expectEqualHexStrings("\x66\x41\x54", emit.lowered(), "push r12w");
24102403}
24112404
24122405test "lower RMI encoding" {
24132406 var emit = TestEmit.init();
24142407 defer emit.deinit();
2415 try lowerToRmiEnc(.imul, .rax, RegisterOrMemory.mem(.qword_ptr, .{
2408 try lowerToRmiEnc(.imul, Register.reg(.rax), RegisterOrMemory.mem(.qword_ptr, .{
24162409 .disp = @bitCast(u32, @as(i32, -8)),
24172410 .base = .rbp,
24182411 }), 0x10, emit.code());
......@@ -2421,18 +2414,18 @@ test "lower RMI encoding" {
24212414 emit.lowered(),
24222415 "imul rax, qword ptr [rbp - 8], 0x10",
24232416 );
2424 try lowerToRmiEnc(.imul, .eax, RegisterOrMemory.mem(.dword_ptr, .{
2417 try lowerToRmiEnc(.imul, Register.reg(.eax), RegisterOrMemory.mem(.dword_ptr, .{
24252418 .disp = @bitCast(u32, @as(i32, -4)),
24262419 .base = .rbp,
24272420 }), 0x10, emit.code());
24282421 try expectEqualHexStrings("\x69\x45\xFC\x10\x00\x00\x00", emit.lowered(), "imul eax, dword ptr [rbp - 4], 0x10");
2429 try lowerToRmiEnc(.imul, .ax, RegisterOrMemory.mem(.word_ptr, .{
2422 try lowerToRmiEnc(.imul, Register.reg(.ax), RegisterOrMemory.mem(.word_ptr, .{
24302423 .disp = @bitCast(u32, @as(i32, -2)),
24312424 .base = .rbp,
24322425 }), 0x10, emit.code());
24332426 try expectEqualHexStrings("\x66\x69\x45\xFE\x10\x00", emit.lowered(), "imul ax, word ptr [rbp - 2], 0x10");
2434 try lowerToRmiEnc(.imul, .r12, RegisterOrMemory.reg(.r12), 0x10, emit.code());
2427 try lowerToRmiEnc(.imul, Register.reg(.r12), RegisterOrMemory.reg(.r12), 0x10, emit.code());
24352428 try expectEqualHexStrings("\x4D\x69\xE4\x10\x00\x00\x00", emit.lowered(), "imul r12, r12, 0x10");
2436 try lowerToRmiEnc(.imul, .r12w, RegisterOrMemory.reg(.r12w), 0x10, emit.code());
2429 try lowerToRmiEnc(.imul, Register.reg(.r12w), RegisterOrMemory.reg(.r12w), 0x10, emit.code());
24372430 try expectEqualHexStrings("\x66\x45\x69\xE4\x10\x00", emit.lowered(), "imul r12w, r12w, 0x10");
24382431}
src/arch/x86_64/bits.zig+117-89
......@@ -302,96 +302,113 @@ pub const Encoder = struct {
302302 self.code.appendAssumeCapacity(0x66);
303303 }
304304
305 pub fn Vex(comptime count: comptime_int) type {
306 if (count < 2 or count > 3) {
307 @compileError("VEX prefix can either be 2- or 3-byte long");
305 pub const Vex = struct {
306 rex_prefix: Rex = .{},
307 lead_opc: u5 = 0b0_0001,
308 register: u4 = 0b1111,
309 length: u1 = 0b0,
310 simd_prefix: u2 = 0b00,
311 wig: bool = false,
312 lig: bool = false,
313 lz: bool = false,
314
315 pub fn rex(self: *Vex, r: Rex) void {
316 self.rex_prefix = r;
308317 }
309318
310 return struct {
311 bytes: [count]u8 = switch (count) {
312 2 => .{ 0xc5, 0xf8 },
313 3 => .{ 0xc4, 0xe1, 0xf8 },
314 else => unreachable,
315 },
316
317 pub fn rex(self: *@This(), prefix: Rex) void {
318 const byte = &self.bytes[1];
319 if (prefix.w) switch (count) {
320 3 => self.bytes[2] &= 0b0111_1111,
321 else => unreachable,
322 };
323 if (prefix.r) byte.* &= 0b0111_1111;
324 if (prefix.x) switch (count) {
325 3 => byte.* &= 0b1011_1111,
326 else => unreachable,
327 };
328 if (prefix.b) switch (count) {
329 3 => byte.* &= 0b1101_1111,
330 else => unreachable,
331 };
332 }
319 pub fn lead_opc_0f(self: *Vex) void {
320 self.lead_opc = 0b0_0001;
321 }
333322
334 pub fn leading_opcode_0f(self: *@This()) void {
335 switch (count) {
336 3 => self.bytes[1] |= 0b0_0001,
337 else => {},
338 }
339 }
323 pub fn lead_opc_0f_38(self: *Vex) void {
324 self.lead_opc = 0b0_0010;
325 }
340326
341 pub fn leading_opcode_0f_38(self: *@This()) void {
342 switch (count) {
343 3 => self.bytes[1] |= 0b0_0010,
344 else => unreachable,
345 }
346 }
327 pub fn lead_opc_0f_3a(self: *Vex) void {
328 self.lead_opc = 0b0_0011;
329 }
347330
348 pub fn leading_opcode_0f_3a(self: *@This()) void {
349 switch (count) {
350 3 => self.bytes[1] |= 0b0_0011,
351 else => unreachable,
352 }
353 }
331 pub fn reg(self: *Vex, register: u4) void {
332 self.register = ~register;
333 }
354334
355 pub fn reg(self: *@This(), register: u4) void {
356 const byte = &self.bytes[count - 1];
357 const mask = 0b1_0000_111;
358 byte.* &= mask;
359 byte.* |= @intCast(u7, ~register) << 3;
360 }
335 pub fn len_128(self: *Vex) void {
336 self.length = 0;
337 }
361338
362 pub fn len_128(self: *@This()) void {
363 const byte = &self.bytes[count - 1];
364 byte.* &= 0b0_11;
365 }
339 pub fn len_256(self: *Vex) void {
340 assert(!self.lz);
341 self.length = 1;
342 }
366343
367 pub fn len_256(self: *@This()) void {
368 const byte = &self.bytes[count - 1];
369 byte.* |= 0b1_00;
370 }
344 pub fn simd_prefix_66(self: *Vex) void {
345 self.simd_prefix = 0b01;
346 }
371347
372 pub fn simd_prefix_66(self: *@This()) void {
373 const byte = &self.bytes[count - 1];
374 byte.* |= 0b01;
375 }
348 pub fn simd_prefix_f3(self: *Vex) void {
349 self.simd_prefix = 0b10;
350 }
376351
377 pub fn simd_prefix_f2(self: *@This()) void {
378 const byte = &self.bytes[count - 1];
379 byte.* |= 0b11;
352 pub fn simd_prefix_f2(self: *Vex) void {
353 self.simd_prefix = 0b11;
354 }
355
356 pub fn wig(self: *Vex) void {
357 self.wig = true;
358 }
359
360 pub fn lig(self: *Vex) void {
361 self.lig = true;
362 }
363
364 pub fn lz(self: *Vex) void {
365 self.lz = true;
366 }
367
368 pub fn write(self: Vex, writer: anytype) usize {
369 var buf: [3]u8 = .{0} ** 3;
370 const form_3byte: bool = blk: {
371 if (self.rex_prefix.w and !self.wig) break :blk true;
372 if (self.rex_prefix.x or self.rex_prefix.b) break :blk true;
373 break :blk self.lead_opc != 0b0_0001;
374 };
375
376 if (self.lz) {
377 assert(self.length == 0);
380378 }
381379
382 pub fn simd_prefix_f3(self: *@This()) void {
383 const byte = &self.bytes[count - 1];
384 byte.* |= 0b10;
380 if (form_3byte) {
381 // First byte
382 buf[0] = 0xc4;
383 // Second byte
384 const rxb_mask: u3 = @intCast(u3, @boolToInt(!self.rex_prefix.r)) << 2 |
385 @intCast(u2, @boolToInt(!self.rex_prefix.x)) << 1 |
386 @boolToInt(!self.rex_prefix.b);
387 buf[1] |= @intCast(u8, rxb_mask) << 5;
388 buf[1] |= self.lead_opc;
389 // Third byte
390 buf[2] |= @intCast(u8, @boolToInt(!self.rex_prefix.w)) << 7;
391 buf[2] |= @intCast(u7, self.register) << 3;
392 buf[2] |= @intCast(u3, self.length) << 2;
393 buf[2] |= self.simd_prefix;
394 } else {
395 // First byte
396 buf[0] = 0xc5;
397 // Second byte
398 buf[1] |= @intCast(u8, @boolToInt(!self.rex_prefix.r)) << 7;
399 buf[1] |= @intCast(u7, self.register) << 3;
400 buf[1] |= @intCast(u3, self.length) << 2;
401 buf[1] |= self.simd_prefix;
385402 }
386 };
387 }
388403
389 pub fn vex_2byte(self: Self, prefix: Vex(2)) void {
390 self.code.appendSliceAssumeCapacity(&prefix.bytes);
391 }
404 const count: usize = if (form_3byte) 3 else 2;
405 _ = writer.writeAll(buf[0..count]) catch unreachable;
406 return count;
407 }
408 };
392409
393 pub fn vex_3byte(self: Self, prefix: Vex(3)) void {
394 self.code.appendSliceAssumeCapacity(&prefix.bytes);
410 pub fn vex(self: Self, prefix: Vex) void {
411 _ = prefix.write(self.code.writer());
395412 }
396413
397414 /// From section 2.2.1.2 of the manual, REX is encoded as b0100WRXB
......@@ -759,39 +776,50 @@ test "Encoder helpers - general purpose registers" {
759776}
760777
761778test "Encoder helpers - Vex prefix" {
779 var buf: [3]u8 = undefined;
780 var stream = std.io.fixedBufferStream(&buf);
781 const writer = stream.writer();
782
762783 {
763 var vex_prefix = Encoder.Vex(2){};
784 var vex_prefix = Encoder.Vex{};
764785 vex_prefix.rex(.{
765786 .r = true,
766787 });
767 try testing.expectEqualSlices(u8, &[_]u8{ 0xc5, 0x78 }, &vex_prefix.bytes);
788 const nwritten = vex_prefix.write(writer);
789 try testing.expectEqualSlices(u8, &[_]u8{ 0xc5, 0x78 }, buf[0..nwritten]);
768790 }
769791
770792 {
771 var vex_prefix = Encoder.Vex(2){};
793 stream.reset();
794 var vex_prefix = Encoder.Vex{};
772795 vex_prefix.reg(AvxRegister.xmm15.id());
773 try testing.expectEqualSlices(u8, &[_]u8{ 0xc5, 0x80 }, &vex_prefix.bytes);
796 const nwritten = vex_prefix.write(writer);
797 try testing.expectEqualSlices(u8, &[_]u8{ 0xc5, 0x80 }, buf[0..nwritten]);
774798 }
775799
776800 {
777 var vex_prefix = Encoder.Vex(3){};
801 stream.reset();
802 var vex_prefix = Encoder.Vex{};
778803 vex_prefix.rex(.{
779804 .w = true,
780805 .x = true,
781806 });
782 try testing.expectEqualSlices(u8, &[_]u8{ 0xc4, 0b101_0_0001, 0b0_1111_0_00 }, &vex_prefix.bytes);
807 const nwritten = vex_prefix.write(writer);
808 try testing.expectEqualSlices(u8, &[_]u8{ 0xc4, 0b101_0_0001, 0b0_1111_0_00 }, buf[0..nwritten]);
783809 }
784810
785811 {
786 var vex_prefix = Encoder.Vex(3){};
812 stream.reset();
813 var vex_prefix = Encoder.Vex{};
787814 vex_prefix.rex(.{
788815 .w = true,
789816 .r = true,
790817 });
791818 vex_prefix.len_256();
792 vex_prefix.leading_opcode_0f();
819 vex_prefix.lead_opc_0f();
793820 vex_prefix.simd_prefix_66();
794 try testing.expectEqualSlices(u8, &[_]u8{ 0xc4, 0b011_0_0001, 0b0_1111_1_01 }, &vex_prefix.bytes);
821 const nwritten = vex_prefix.write(writer);
822 try testing.expectEqualSlices(u8, &[_]u8{ 0xc4, 0b011_0_0001, 0b0_1111_1_01 }, buf[0..nwritten]);
795823 }
796824
797825 var code = ArrayList(u8).init(testing.allocator);
......@@ -800,9 +828,9 @@ test "Encoder helpers - Vex prefix" {
800828 {
801829 // vmovapd xmm1, xmm2
802830 const encoder = try Encoder.init(&code, 4);
803 var vex = Encoder.Vex(2){};
831 var vex = Encoder.Vex{};
804832 vex.simd_prefix_66();
805 encoder.vex_2byte(vex); // use 64 bit operation
833 encoder.vex(vex); // use 64 bit operation
806834 encoder.opcode_1byte(0x28);
807835 encoder.modRm_direct(0, AvxRegister.xmm1.lowId());
808836 try testing.expectEqualSlices(u8, &[_]u8{ 0xC5, 0xF9, 0x28, 0xC1 }, code.items);
......@@ -813,13 +841,13 @@ test "Encoder helpers - Vex prefix" {
813841
814842 // vmovhpd xmm13, xmm1, qword ptr [rip]
815843 const encoder = try Encoder.init(&code, 9);
816 var vex = Encoder.Vex(2){};
844 var vex = Encoder.Vex{};
817845 vex.len_128();
818846 vex.simd_prefix_66();
819 vex.leading_opcode_0f();
847 vex.lead_opc_0f();
820848 vex.rex(.{ .r = true });
821849 vex.reg(AvxRegister.xmm1.id());
822 encoder.vex_2byte(vex);
850 encoder.vex(vex);
823851 encoder.opcode_1byte(0x16);
824852 encoder.modRm_RIPDisp32(AvxRegister.xmm13.lowId());
825853 encoder.disp32(0);