authorgravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2023-05-14 17:26:44-04:00
committergravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2023-05-15 03:07:51-04:00
log037bf1a580fe24b427e0ee5f7aecfec7202c1bf3
tree55cceeebcb554e3ffba8b586a2c75200d0480d26
parent6c6d8d67cfe14c50684c04a579c1e62bf287e8cb

x86_64: enable integer vector registers

1 files changed, 3 insertions(+), 3 deletions(-)

src/arch/x86_64/CodeGen.zig+3-3
...@@ -2261,11 +2261,11 @@ fn allocRegOrMemAdvanced(self: *Self, ty: Type, inst: ?Air.Inst.Index, reg_ok: b...@@ -2261,11 +2261,11 @@ fn allocRegOrMemAdvanced(self: *Self, ty: Type, inst: ?Air.Inst.Index, reg_ok: b
2261 },2261 },
2262 .Vector => switch (ty.childType().zigTypeTag()) {2262 .Vector => switch (ty.childType().zigTypeTag()) {
2263 .Float => switch (ty.childType().floatBits(self.target.*)) {2263 .Float => switch (ty.childType().floatBits(self.target.*)) {
2264 16, 32, 64 => if (self.hasFeature(.avx)) 32 else 16,2264 16, 32, 64, 128 => if (self.hasFeature(.avx)) 32 else 16,
2265 80, 128 => break :need_mem,2265 80 => break :need_mem,
2266 else => unreachable,2266 else => unreachable,
2267 },2267 },
2268 else => break :need_mem,2268 else => if (self.hasFeature(.avx)) 32 else 16,
2269 },2269 },
2270 else => 8,2270 else => 8,
2271 })) {2271 })) {