authorgravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2021-12-15 17:18:38+01:00
committergravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2021-12-15 17:28:48+01:00
log04784463772decb18d70734747d3fc89c043b979
tree2552ad30128a68dac5386c501414c21cd4a11425
parent510357355a3ca597daf13fadb6aa8f7df72ea26a

stage2: fix register size selection

This actually needs proper rework, and I'll get to that when refactoring MIR.

1 files changed, 4 insertions(+), 5 deletions(-)

src/arch/x86_64/CodeGen.zig+4-5
...@@ -1635,7 +1635,7 @@ fn genBinMathOpMir(...@@ -1635,7 +1635,7 @@ fn genBinMathOpMir(
1635 .tag = mir_tag,1635 .tag = mir_tag,
1636 .ops = (Mir.Ops{1636 .ops = (Mir.Ops{
1637 .reg1 = registerAlias(dst_reg, @intCast(u32, abi_size)),1637 .reg1 = registerAlias(dst_reg, @intCast(u32, abi_size)),
1638 .reg2 = .ebp,1638 .reg2 = registerAlias(.rbp, @intCast(u32, abi_size)),
1639 .flags = 0b01,1639 .flags = 0b01,
1640 }).encode(),1640 }).encode(),
1641 .data = .{ .imm = -@intCast(i32, adj_off) },1641 .data = .{ .imm = -@intCast(i32, adj_off) },
...@@ -1666,7 +1666,7 @@ fn genBinMathOpMir(...@@ -1666,7 +1666,7 @@ fn genBinMathOpMir(
1666 .tag = mir_tag,1666 .tag = mir_tag,
1667 .ops = (Mir.Ops{1667 .ops = (Mir.Ops{
1668 .reg1 = registerAlias(src_reg, @intCast(u32, abi_size)),1668 .reg1 = registerAlias(src_reg, @intCast(u32, abi_size)),
1669 .reg2 = .ebp,1669 .reg2 = registerAlias(.rbp, @intCast(u32, abi_size)),
1670 .flags = 0b10,1670 .flags = 0b10,
1671 }).encode(),1671 }).encode(),
1672 .data = .{ .imm = -@intCast(i32, adj_off) },1672 .data = .{ .imm = -@intCast(i32, adj_off) },
...@@ -2835,12 +2835,11 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro...@@ -2835,12 +2835,11 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
2835 }2835 }
2836 const abi_size = ty.abiSize(self.target.*);2836 const abi_size = ty.abiSize(self.target.*);
2837 const adj_off = stack_offset + abi_size;2837 const adj_off = stack_offset + abi_size;
2838 // TODO select instruction size
2839 _ = try self.addInst(.{2838 _ = try self.addInst(.{
2840 .tag = .mov,2839 .tag = .mov,
2841 .ops = (Mir.Ops{2840 .ops = (Mir.Ops{
2842 .reg1 = registerAlias(reg, @intCast(u32, abi_size)),2841 .reg1 = registerAlias(reg, @intCast(u32, abi_size)),
2843 .reg2 = .rbp,2842 .reg2 = registerAlias(.rbp, @intCast(u32, abi_size)),
2844 .flags = 0b10,2843 .flags = 0b10,
2845 }).encode(),2844 }).encode(),
2846 .data = .{ .imm = -@intCast(i32, adj_off) },2845 .data = .{ .imm = -@intCast(i32, adj_off) },
...@@ -3061,7 +3060,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void...@@ -3061,7 +3060,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
3061 .tag = .mov,3060 .tag = .mov,
3062 .ops = (Mir.Ops{3061 .ops = (Mir.Ops{
3063 .reg1 = registerAlias(reg, @intCast(u32, abi_size)),3062 .reg1 = registerAlias(reg, @intCast(u32, abi_size)),
3064 .reg2 = .ebp,3063 .reg2 = registerAlias(.rbp, @intCast(u32, abi_size)),
3065 .flags = 0b01,3064 .flags = 0b01,
3066 }).encode(),3065 }).encode(),
3067 .data = .{ .imm = ioff },3066 .data = .{ .imm = ioff },