From 0b67463b9285158d818d6cd196c5f2ba9961a05e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= <alex@alexrp.com>
Date: Wed, 13 Nov 2024 11:15:56 +0100
Subject: [PATCH] riscv64: Support the fp alias for register s0 in inline
 assembly.

---
 src/arch/riscv64/CodeGen.zig | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/arch/riscv64/CodeGen.zig b/src/arch/riscv64/CodeGen.zig
index 29a0a8b8b5b4e36e9f39890a0f0117620b4536ea..a836d02d711dac58bb9e78892d165268dcb597e0 100644
--- a/src/arch/riscv64/CodeGen.zig
+++ b/src/arch/riscv64/CodeGen.zig
@@ -8442,6 +8442,10 @@ fn failSymbol(func: *Func, comptime format: []const u8, args: anytype) InnerErro
 }
 
 fn parseRegName(name: []const u8) ?Register {
+    // The `fp` alias for `s0` is awkward to fit into the current `Register` scheme, so for now we
+    // special-case it here.
+    if (std.mem.eql(u8, name, "fp")) return .s0;
+
     return std.meta.stringToEnum(Register, name);
 }
 
-- 
2.54.0