From 0f09c3c55a2db5b05a38ea431d0b312320a7f178 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= <alex@alexrp.com>
Date: Tue, 20 Oct 2026 01:41:40 +0200
Subject: [PATCH] update_cpu_features: flesh out xcore data

LLVM's backend is very outdated so we can't extract any useful data from it.
---
 lib/std/Target.zig            |  2 +-
 lib/std/Target/xcore.zig      | 57 ++++++++++++++++++++++++++++++-----
 tools/update_cpu_features.zig | 43 ++++++++++++++++++++++++++
 3 files changed, 93 insertions(+), 9 deletions(-)

diff --git a/lib/std/Target.zig b/lib/std/Target.zig
index 5601a2661388baced89e175614510f0b61ae14f8..ff1ac2c563a9f923313ca3027570ad9db45fd3f7 100644
--- a/lib/std/Target.zig
+++ b/lib/std/Target.zig
@@ -2070,6 +2070,7 @@ pub const Cpu = struct {
                 .x86_16 => &x86.cpu.i86,
                 .x86 => &x86.cpu.i386,
                 .x86_64 => &x86.cpu.x86_64,
+                .xcore => &xcore.cpu.xs1b,
                 inline else => |a| &@field(Target, @tagName(a.family())).cpu.generic,
             };
         }
@@ -2157,7 +2158,6 @@ pub const Cpu = struct {
                     .ps5 => &x86.cpu.znver2,
                     else => generic(arch),
                 },
-                .xcore => &xcore.cpu.xs1b_generic,
                 .xtensa => &xtensa.cpu.esp32,
                 .wasm32, .wasm64 => &wasm.cpu.lime1,
 
diff --git a/lib/std/Target/xcore.zig b/lib/std/Target/xcore.zig
index e30381131e8a1ab33318588c72d380184b3352e4..b2580b5a7db89527e7926e903e98a64bde150690 100644
--- a/lib/std/Target/xcore.zig
+++ b/lib/std/Target/xcore.zig
@@ -4,7 +4,12 @@ const std = @import("../std.zig");
 const CpuFeature = std.Target.Cpu.Feature;
 const CpuModel = std.Target.Cpu.Model;
 
-pub const Feature = enum {};
+pub const Feature = enum {
+    fpu,
+    vpu,
+    xs2,
+    xs3,
+};
 
 pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
 pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
@@ -15,6 +20,32 @@ pub const all_features = blk: {
     const len = @typeInfo(Feature).@"enum".field_names.len;
     std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
     var result: [len]CpuFeature = undefined;
+    result[@backingInt(Feature.fpu)] = .{
+        .llvm_name = null,
+        .description = "Enable single-precision floating point unit",
+        .dependencies = featureSet(&[_]Feature{
+            .xs3,
+        }),
+    };
+    result[@backingInt(Feature.vpu)] = .{
+        .llvm_name = null,
+        .description = "Enable vector processing unit",
+        .dependencies = featureSet(&[_]Feature{
+            .xs3,
+        }),
+    };
+    result[@backingInt(Feature.xs2)] = .{
+        .llvm_name = null,
+        .description = "Enable XS2 architecture",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.xs3)] = .{
+        .llvm_name = null,
+        .description = "Enable XS3 architecture",
+        .dependencies = featureSet(&[_]Feature{
+            .xs2,
+        }),
+    };
     const ti = @typeInfo(Feature);
     for (&result, 0..) |*elem, i| {
         elem.index = i;
@@ -24,14 +55,24 @@ pub const all_features = blk: {
 };
 
 pub const cpu = struct {
-    pub const generic: CpuModel = .{
-        .name = "generic",
-        .llvm_name = "generic",
+    pub const xs1b: CpuModel = .{
+        .name = "xs1b",
+        .llvm_name = null,
         .features = featureSet(&[_]Feature{}),
     };
-    pub const xs1b_generic: CpuModel = .{
-        .name = "xs1b_generic",
-        .llvm_name = "xs1b-generic",
-        .features = featureSet(&[_]Feature{}),
+    pub const xs2a: CpuModel = .{
+        .name = "xs2a",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .xs2,
+        }),
+    };
+    pub const xs3a: CpuModel = .{
+        .name = "xs3a",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .fpu,
+            .vpu,
+        }),
     };
 };
diff --git a/tools/update_cpu_features.zig b/tools/update_cpu_features.zig
index e4c23d5c0f492eab58fa10b5ee06cf70171254e3..97fca809c35365b8d3aa97792cec69deaecf353e 100644
--- a/tools/update_cpu_features.zig
+++ b/tools/update_cpu_features.zig
@@ -2096,6 +2096,49 @@ const targets = [_]ArchTarget{
             .name = "XCore",
             .td_name = "XCore",
         },
+        .extra_features = &.{
+            .{
+                .zig_name = "xs2",
+                .desc = "Enable XS2 architecture",
+                .deps = &.{},
+            },
+            .{
+                .zig_name = "xs3",
+                .desc = "Enable XS3 architecture",
+                .deps = &.{"xs2"},
+            },
+            .{
+                .zig_name = "fpu",
+                .desc = "Enable single-precision floating point unit",
+                .deps = &.{"xs3"},
+            },
+            .{
+                .zig_name = "vpu",
+                .desc = "Enable vector processing unit",
+                .deps = &.{"xs3"},
+            },
+        },
+        .extra_cpus = &.{
+            .{
+                .llvm_name = null,
+                .zig_name = "xs1b",
+                .features = &.{},
+            },
+            .{
+                .llvm_name = null,
+                .zig_name = "xs2a",
+                .features = &.{"xs2"},
+            },
+            .{
+                .llvm_name = null,
+                .zig_name = "xs3a",
+                .features = &.{ "fpu", "vpu" },
+            },
+        },
+        .omit_cpus = &.{
+            "generic",
+            "xs1b-generic",
+        },
     },
     .{
         .zig_name = "xtensa",
-- 
2.54.0