Commit 109ec729247443200c2ba614f6acb0b991e44b4d | zig

author	Andrew Kelley <andrew@ziglang.org> 2024-04-25 16:54:33-07:00
committer	Andrew Kelley <andrew@ziglang.org> 2024-05-08 19:37:28-07:00
log	109ec729247443200c2ba614f6acb0b991e44b4d
tree	b3ca76a9b71efb0c5b4ae425ae9b60d4031abe64
parent	6a018d3e658a9886a5e8a04289d1466d0ab3514a

update CPU features to LLVM 18

release/18.x branch, commit 78b99c73ee4b96fe9ce0e294d4632326afb2db42

14 files changed, 2119 insertions(+), 206 deletions(-)

lib
- std
  - Target
    aarch64.zig
    amdgpu.zig
    arm.zig
    bpf.zig
    loongarch.zig
    nvptx.zig
    powerpc.zig
    riscv.zig
    s390x.zig
    sparc.zig
    ve.zig
    wasm.zig
    x86.zig
tools
- update_cpu_features.zig

lib/std/Target/aarch64.zig+411-46

...	...	@@ -6,15 +6,19 @@ const CpuModel = std.Target.Cpu.Model;
6	6
7	7	pub const Feature = enum {
8	8	a510,
	9	a520,
9	10	a65,
10	11	a710,
	12	a720,
11	13	a76,
12	14	a78,
13	15	a78c,
	16	addr_lsl_fast,
14	17	aes,
15	18	aggressive_fma,
16	19	alternate_sextload_cvt_f32_pattern,
17	20	altnzcv,
	21	alu_lsl_fast,
18	22	am,
19	23	amvs,
20	24	arith_bcc_fusion,
...	...	@@ -43,12 +47,14 @@ pub const Feature = enum {
43	47	complxnum,
44	48	contextidr_el2,
45	49	cortex_r82,
	50	cpa,
46	51	crc,
47	52	crypto,
48	53	cssc,
49		custom_cheap_as_move,
50	54	d128,
51	55	disable_latency_sched_heuristic,
	56	disable_ldp,
	57	disable_stp,
52	58	dit,
53	59	dotprod,
54	60	ecv,
...	...	@@ -59,13 +65,19 @@ pub const Feature = enum {
59	65	exynos_cheap_as_move,
60	66	f32mm,
61	67	f64mm,
	68	faminmax,
62	69	fgt,
63	70	fix_cortex_a53_835769,
64	71	flagm,
65	72	fmv,
66	73	force_32bit_jump_tables,
67	74	fp16fml,
	75	fp8,
	76	fp8dot2,
	77	fp8dot4,
	78	fp8fma,
68	79	fp_armv8,
	80	fpmr,
69	81	fptoint,
70	82	fullfp16,
71	83	fuse_address,
...	...	@@ -85,12 +97,13 @@ pub const Feature = enum {
85	97	i8mm,
86	98	ite,
87	99	jsconv,
	100	ldp_aligned_only,
88	101	lor,
89	102	ls64,
90	103	lse,
91	104	lse128,
92	105	lse2,
93		lsl_fast,
	106	lut,
94	107	mec,
95	108	mops,
96	109	mpam,
...	...	@@ -106,6 +119,7 @@ pub const Feature = enum {
106	119	pan,
107	120	pan_rwv,
108	121	pauth,
	122	pauth_lr,
109	123	perfmon,
110	124	predictable_select_expensive,
111	125	predres,
...	...	@@ -156,12 +170,21 @@ pub const Feature = enum {
156	170	sme2p1,
157	171	sme_f16f16,
158	172	sme_f64f64,
	173	sme_f8f16,
	174	sme_f8f32,
	175	sme_fa64,
159	176	sme_i16i64,
	177	sme_lutv2,
160	178	spe,
161	179	spe_eef,
162	180	specres2,
163	181	specrestrict,
164	182	ssbs,
	183	ssve_fp8dot2,
	184	ssve_fp8dot4,
	185	ssve_fp8fma,
	186	store_pair_suppress,
	187	stp_aligned_only,
165	188	strict_align,
166	189	sve,
167	190	sve2,
...	...	@@ -173,6 +196,7 @@ pub const Feature = enum {
173	196	tagged_globals,
174	197	the,
175	198	tlb_rmi,
	199	tlbiw,
176	200	tme,
177	201	tpidr_el1,
178	202	tpidr_el2,
...	...	@@ -200,6 +224,7 @@ pub const Feature = enum {
200	224	v9_2a,
201	225	v9_3a,
202	226	v9_4a,
	227	v9_5a,
203	228	v9a,
204	229	vh,
205	230	wfxt,
...	...	@@ -229,6 +254,15 @@ pub const all_features = blk: {
229	254	.use_postra_scheduler,
230	255	}),
231	256	};
	257	result[@intFromEnum(Feature.a520)] = .{
	258	.llvm_name = "a520",
	259	.description = "Cortex-A520 ARM processors",
	260	.dependencies = featureSet(&[_]Feature{
	261	.fuse_adrp_add,
	262	.fuse_aes,
	263	.use_postra_scheduler,
	264	}),
	265	};
232	266	result[@intFromEnum(Feature.a65)] = .{
233	267	.llvm_name = "a65",
234	268	.description = "Cortex-A65 ARM processors",
...	...	@@ -245,11 +279,26 @@ pub const all_features = blk: {
245	279	.llvm_name = "a710",
246	280	.description = "Cortex-A710 ARM processors",
247	281	.dependencies = featureSet(&[_]Feature{
	282	.addr_lsl_fast,
	283	.alu_lsl_fast,
	284	.cmp_bcc_fusion,
	285	.enable_select_opt,
	286	.fuse_adrp_add,
	287	.fuse_aes,
	288	.predictable_select_expensive,
	289	.use_postra_scheduler,
	290	}),
	291	};
	292	result[@intFromEnum(Feature.a720)] = .{
	293	.llvm_name = "a720",
	294	.description = "Cortex-A720 ARM processors",
	295	.dependencies = featureSet(&[_]Feature{
	296	.addr_lsl_fast,
	297	.alu_lsl_fast,
248	298	.cmp_bcc_fusion,
249	299	.enable_select_opt,
250	300	.fuse_adrp_add,
251	301	.fuse_aes,
252		.lsl_fast,
253	302	.predictable_select_expensive,
254	303	.use_postra_scheduler,
255	304	}),
...	...	@@ -258,10 +307,11 @@ pub const all_features = blk: {
258	307	.llvm_name = "a76",
259	308	.description = "Cortex-A76 ARM processors",
260	309	.dependencies = featureSet(&[_]Feature{
	310	.addr_lsl_fast,
	311	.alu_lsl_fast,
261	312	.enable_select_opt,
262	313	.fuse_adrp_add,
263	314	.fuse_aes,
264		.lsl_fast,
265	315	.predictable_select_expensive,
266	316	}),
267	317	};
...	...	@@ -269,11 +319,12 @@ pub const all_features = blk: {
269	319	.llvm_name = "a78",
270	320	.description = "Cortex-A78 ARM processors",
271	321	.dependencies = featureSet(&[_]Feature{
	322	.addr_lsl_fast,
	323	.alu_lsl_fast,
272	324	.cmp_bcc_fusion,
273	325	.enable_select_opt,
274	326	.fuse_adrp_add,
275	327	.fuse_aes,
276		.lsl_fast,
277	328	.predictable_select_expensive,
278	329	.use_postra_scheduler,
279	330	}),
...	...	@@ -282,15 +333,21 @@ pub const all_features = blk: {
282	333	.llvm_name = "a78c",
283	334	.description = "Cortex-A78C ARM processors",
284	335	.dependencies = featureSet(&[_]Feature{
	336	.addr_lsl_fast,
	337	.alu_lsl_fast,
285	338	.cmp_bcc_fusion,
286	339	.enable_select_opt,
287	340	.fuse_adrp_add,
288	341	.fuse_aes,
289		.lsl_fast,
290	342	.predictable_select_expensive,
291	343	.use_postra_scheduler,
292	344	}),
293	345	};
	346	result[@intFromEnum(Feature.addr_lsl_fast)] = .{
	347	.llvm_name = "addr-lsl-fast",
	348	.description = "Address operands with logical shift of up to 3 places are cheap",
	349	.dependencies = featureSet(&[_]Feature{}),
	350	};
294	351	result[@intFromEnum(Feature.aes)] = .{
295	352	.llvm_name = "aes",
296	353	.description = "Enable AES support (FEAT_AES, FEAT_PMULL)",
...	...	@@ -313,6 +370,11 @@ pub const all_features = blk: {
313	370	.description = "Enable alternative NZCV format for floating point comparisons (FEAT_FlagM2)",
314	371	.dependencies = featureSet(&[_]Feature{}),
315	372	};
	373	result[@intFromEnum(Feature.alu_lsl_fast)] = .{
	374	.llvm_name = "alu-lsl-fast",
	375	.description = "Add/Sub operations with lsl shift <= 4 are cheap",
	376	.dependencies = featureSet(&[_]Feature{}),
	377	};
316	378	result[@intFromEnum(Feature.am)] = .{
317	379	.llvm_name = "am",
318	380	.description = "Enable v8.4-A Activity Monitors extension (FEAT_AMUv1)",
...	...	@@ -343,7 +405,9 @@ pub const all_features = blk: {
343	405	result[@intFromEnum(Feature.b16b16)] = .{
344	406	.llvm_name = "b16b16",
345	407	.description = "Enable SVE2.1 or SME2.1 non-widening BFloat16 to BFloat16 instructions (FEAT_B16B16)",
346		.dependencies = featureSet(&[_]Feature{}),
	408	.dependencies = featureSet(&[_]Feature{
	409	.bf16,
	410	}),
347	411	};
348	412	result[@intFromEnum(Feature.balance_fp_ops)] = .{
349	413	.llvm_name = "balance-fp-ops",
...	...	@@ -459,6 +523,11 @@ pub const all_features = blk: {
459	523	.use_postra_scheduler,
460	524	}),
461	525	};
	526	result[@intFromEnum(Feature.cpa)] = .{
	527	.llvm_name = "cpa",
	528	.description = "Enable Armv9.5-A Checked Pointer Arithmetic (FEAT_CPA)",
	529	.dependencies = featureSet(&[_]Feature{}),
	530	};
462	531	result[@intFromEnum(Feature.crc)] = .{
463	532	.llvm_name = "crc",
464	533	.description = "Enable ARMv8 CRC-32 checksum instructions (FEAT_CRC32)",
...	...	@@ -477,11 +546,6 @@ pub const all_features = blk: {
477	546	.description = "Enable Common Short Sequence Compression (CSSC) instructions (FEAT_CSSC)",
478	547	.dependencies = featureSet(&[_]Feature{}),
479	548	};
480		result[@intFromEnum(Feature.custom_cheap_as_move)] = .{
481		.llvm_name = "custom-cheap-as-move",
482		.description = "Use custom handling of cheap instructions",
483		.dependencies = featureSet(&[_]Feature{}),
484		};
485	549	result[@intFromEnum(Feature.d128)] = .{
486	550	.llvm_name = "d128",
487	551	.description = "Enable Armv9.4-A 128-bit Page Table Descriptors, System Registers and Instructions (FEAT_D128, FEAT_LVA3, FEAT_SYSREG128, FEAT_SYSINSTR128)",
...	...	@@ -494,6 +558,16 @@ pub const all_features = blk: {
494	558	.description = "Disable latency scheduling heuristic",
495	559	.dependencies = featureSet(&[_]Feature{}),
496	560	};
	561	result[@intFromEnum(Feature.disable_ldp)] = .{
	562	.llvm_name = "disable-ldp",
	563	.description = "Do not emit ldp",
	564	.dependencies = featureSet(&[_]Feature{}),
	565	};
	566	result[@intFromEnum(Feature.disable_stp)] = .{
	567	.llvm_name = "disable-stp",
	568	.description = "Do not emit stp",
	569	.dependencies = featureSet(&[_]Feature{}),
	570	};
497	571	result[@intFromEnum(Feature.dit)] = .{
498	572	.llvm_name = "dit",
499	573	.description = "Enable v8.4-A Data Independent Timing instructions (FEAT_DIT)",
...	...	@@ -534,9 +608,7 @@ pub const all_features = blk: {
534	608	result[@intFromEnum(Feature.exynos_cheap_as_move)] = .{
535	609	.llvm_name = "exynos-cheap-as-move",
536	610	.description = "Use Exynos specific handling of cheap instructions",
537		.dependencies = featureSet(&[_]Feature{
538		.custom_cheap_as_move,
539		}),
	611	.dependencies = featureSet(&[_]Feature{}),
540	612	};
541	613	result[@intFromEnum(Feature.f32mm)] = .{
542	614	.llvm_name = "f32mm",
...	...	@@ -552,6 +624,11 @@ pub const all_features = blk: {
552	624	.sve,
553	625	}),
554	626	};
	627	result[@intFromEnum(Feature.faminmax)] = .{
	628	.llvm_name = "faminmax",
	629	.description = "Enable FAMIN and FAMAX instructions (FEAT_FAMINMAX)",
	630	.dependencies = featureSet(&[_]Feature{}),
	631	};
555	632	result[@intFromEnum(Feature.fgt)] = .{
556	633	.llvm_name = "fgt",
557	634	.description = "Enable fine grained virtualization traps extension (FEAT_FGT)",
...	...	@@ -584,11 +661,36 @@ pub const all_features = blk: {
584	661	.fullfp16,
585	662	}),
586	663	};
	664	result[@intFromEnum(Feature.fp8)] = .{
	665	.llvm_name = "fp8",
	666	.description = "Enable FP8 instructions (FEAT_FP8)",
	667	.dependencies = featureSet(&[_]Feature{}),
	668	};
	669	result[@intFromEnum(Feature.fp8dot2)] = .{
	670	.llvm_name = "fp8dot2",
	671	.description = "Enable fp8 2-way dot instructions (FEAT_FP8DOT2)",
	672	.dependencies = featureSet(&[_]Feature{}),
	673	};
	674	result[@intFromEnum(Feature.fp8dot4)] = .{
	675	.llvm_name = "fp8dot4",
	676	.description = "Enable fp8 4-way dot instructions (FEAT_FP8DOT4)",
	677	.dependencies = featureSet(&[_]Feature{}),
	678	};
	679	result[@intFromEnum(Feature.fp8fma)] = .{
	680	.llvm_name = "fp8fma",
	681	.description = "Enable fp8 multiply-add instructions (FEAT_FP8FMA)",
	682	.dependencies = featureSet(&[_]Feature{}),
	683	};
587	684	result[@intFromEnum(Feature.fp_armv8)] = .{
588	685	.llvm_name = "fp-armv8",
589	686	.description = "Enable ARMv8 FP (FEAT_FP)",
590	687	.dependencies = featureSet(&[_]Feature{}),
591	688	};
	689	result[@intFromEnum(Feature.fpmr)] = .{
	690	.llvm_name = "fpmr",
	691	.description = "Enable FPMR Register (FEAT_FPMR)",
	692	.dependencies = featureSet(&[_]Feature{}),
	693	};
592	694	result[@intFromEnum(Feature.fptoint)] = .{
593	695	.llvm_name = "fptoint",
594	696	.description = "Enable FRInt[32\|64][Z\|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int (FEAT_FRINTTS)",
...	...	@@ -692,6 +794,11 @@ pub const all_features = blk: {
692	794	.fp_armv8,
693	795	}),
694	796	};
	797	result[@intFromEnum(Feature.ldp_aligned_only)] = .{
	798	.llvm_name = "ldp-aligned-only",
	799	.description = "In order to emit ldp, first check if the load will be aligned to 2 * element_size",
	800	.dependencies = featureSet(&[_]Feature{}),
	801	};
695	802	result[@intFromEnum(Feature.lor)] = .{
696	803	.llvm_name = "lor",
697	804	.description = "Enables ARM v8.1 Limited Ordering Regions extension (FEAT_LOR)",
...	...	@@ -719,9 +826,9 @@ pub const all_features = blk: {
719	826	.description = "Enable ARMv8.4 Large System Extension 2 (LSE2) atomicity rules (FEAT_LSE2)",
720	827	.dependencies = featureSet(&[_]Feature{}),
721	828	};
722		result[@intFromEnum(Feature.lsl_fast)] = .{
723		.llvm_name = "lsl-fast",
724		.description = "CPU has a fastpath logical shift of up to 3 places",
	829	result[@intFromEnum(Feature.lut)] = .{
	830	.llvm_name = "lut",
	831	.description = "Enable Lookup Table instructions (FEAT_LUT)",
725	832	.dependencies = featureSet(&[_]Feature{}),
726	833	};
727	834	result[@intFromEnum(Feature.mec)] = .{
...	...	@@ -805,6 +912,11 @@ pub const all_features = blk: {
805	912	.description = "Enable v8.3-A Pointer Authentication extension (FEAT_PAuth)",
806	913	.dependencies = featureSet(&[_]Feature{}),
807	914	};
	915	result[@intFromEnum(Feature.pauth_lr)] = .{
	916	.llvm_name = "pauth-lr",
	917	.description = "Enable Armv9.5-A PAC enhancements (FEAT_PAuth_LR)",
	918	.dependencies = featureSet(&[_]Feature{}),
	919	};
808	920	result[@intFromEnum(Feature.perfmon)] = .{
809	921	.llvm_name = "perfmon",
810	922	.description = "Enable Code Generation for ARMv8 PMUv3 Performance Monitors extension (FEAT_PMUv3)",
...	...	@@ -1076,6 +1188,30 @@ pub const all_features = blk: {
1076	1188	.sme,
1077	1189	}),
1078	1190	};
	1191	result[@intFromEnum(Feature.sme_f8f16)] = .{
	1192	.llvm_name = "sme-f8f16",
	1193	.description = "Enable Scalable Matrix Extension (SME) F8F16 instructions(FEAT_SME_F8F16)",
	1194	.dependencies = featureSet(&[_]Feature{
	1195	.fp8,
	1196	.sme2,
	1197	}),
	1198	};
	1199	result[@intFromEnum(Feature.sme_f8f32)] = .{
	1200	.llvm_name = "sme-f8f32",
	1201	.description = "Enable Scalable Matrix Extension (SME) F8F32 instructions (FEAT_SME_F8F32)",
	1202	.dependencies = featureSet(&[_]Feature{
	1203	.fp8,
	1204	.sme2,
	1205	}),
	1206	};
	1207	result[@intFromEnum(Feature.sme_fa64)] = .{
	1208	.llvm_name = "sme-fa64",
	1209	.description = "Enable the full A64 instruction set in streaming SVE mode (FEAT_SME_FA64)",
	1210	.dependencies = featureSet(&[_]Feature{
	1211	.sme,
	1212	.sve2,
	1213	}),
	1214	};
1079	1215	result[@intFromEnum(Feature.sme_i16i64)] = .{
1080	1216	.llvm_name = "sme-i16i64",
1081	1217	.description = "Enable Scalable Matrix Extension (SME) I16I64 instructions (FEAT_SME_I16I64)",
...	...	@@ -1083,6 +1219,11 @@ pub const all_features = blk: {
1083	1219	.sme,
1084	1220	}),
1085	1221	};
	1222	result[@intFromEnum(Feature.sme_lutv2)] = .{
	1223	.llvm_name = "sme-lutv2",
	1224	.description = "Enable Scalable Matrix Extension (SME) LUTv2 instructions (FEAT_SME_LUTv2)",
	1225	.dependencies = featureSet(&[_]Feature{}),
	1226	};
1086	1227	result[@intFromEnum(Feature.spe)] = .{
1087	1228	.llvm_name = "spe",
1088	1229	.description = "Enable Statistical Profiling extension (FEAT_SPE)",
...	...	@@ -1110,6 +1251,37 @@ pub const all_features = blk: {
1110	1251	.description = "Enable Speculative Store Bypass Safe bit (FEAT_SSBS, FEAT_SSBS2)",
1111	1252	.dependencies = featureSet(&[_]Feature{}),
1112	1253	};
	1254	result[@intFromEnum(Feature.ssve_fp8dot2)] = .{
	1255	.llvm_name = "ssve-fp8dot2",
	1256	.description = "Enable SVE2 fp8 2-way dot product instructions (FEAT_SSVE_FP8DOT2)",
	1257	.dependencies = featureSet(&[_]Feature{
	1258	.sme2,
	1259	}),
	1260	};
	1261	result[@intFromEnum(Feature.ssve_fp8dot4)] = .{
	1262	.llvm_name = "ssve-fp8dot4",
	1263	.description = "Enable SVE2 fp8 4-way dot product instructions (FEAT_SSVE_FP8DOT4)",
	1264	.dependencies = featureSet(&[_]Feature{
	1265	.sme2,
	1266	}),
	1267	};
	1268	result[@intFromEnum(Feature.ssve_fp8fma)] = .{
	1269	.llvm_name = "ssve-fp8fma",
	1270	.description = "Enable SVE2 fp8 multiply-add instructions (FEAT_SSVE_FP8FMA)",
	1271	.dependencies = featureSet(&[_]Feature{
	1272	.sme2,
	1273	}),
	1274	};
	1275	result[@intFromEnum(Feature.store_pair_suppress)] = .{
	1276	.llvm_name = "store-pair-suppress",
	1277	.description = "Enable Store Pair Suppression heuristics",
	1278	.dependencies = featureSet(&[_]Feature{}),
	1279	};
	1280	result[@intFromEnum(Feature.stp_aligned_only)] = .{
	1281	.llvm_name = "stp-aligned-only",
	1282	.description = "In order to emit stp, first check if the store will be aligned to 2 * element_size",
	1283	.dependencies = featureSet(&[_]Feature{}),
	1284	};
1113	1285	result[@intFromEnum(Feature.strict_align)] = .{
1114	1286	.llvm_name = "strict-align",
1115	1287	.description = "Disallow all unaligned memory access",
...	...	@@ -1183,6 +1355,11 @@ pub const all_features = blk: {
1183	1355	.description = "Enable v8.4-A TLB Range and Maintenance Instructions (FEAT_TLBIOS, FEAT_TLBIRANGE)",
1184	1356	.dependencies = featureSet(&[_]Feature{}),
1185	1357	};
	1358	result[@intFromEnum(Feature.tlbiw)] = .{
	1359	.llvm_name = "tlbiw",
	1360	.description = "Enable ARMv9.5-A TLBI VMALL for Dirty State (FEAT_TLBIW)",
	1361	.dependencies = featureSet(&[_]Feature{}),
	1362	};
1186	1363	result[@intFromEnum(Feature.tme)] = .{
1187	1364	.llvm_name = "tme",
1188	1365	.description = "Enable Transactional Memory Extension (FEAT_TME)",
...	...	@@ -1424,6 +1601,14 @@ pub const all_features = blk: {
1424	1601	.v9_3a,
1425	1602	}),
1426	1603	};
	1604	result[@intFromEnum(Feature.v9_5a)] = .{
	1605	.llvm_name = "v9.5a",
	1606	.description = "Support ARM v9.5a instructions",
	1607	.dependencies = featureSet(&[_]Feature{
	1608	.cpa,
	1609	.v9_4a,
	1610	}),
	1611	};
1427	1612	result[@intFromEnum(Feature.v9a)] = .{
1428	1613	.llvm_name = "v9a",
1429	1614	.description = "Support ARM v9a instructions",
...	...	@@ -1491,6 +1676,7 @@ pub const cpu = struct {
1491	1676	.perfmon,
1492	1677	.predictable_select_expensive,
1493	1678	.sha2,
	1679	.store_pair_suppress,
1494	1680	.sve,
1495	1681	.use_postra_scheduler,
1496	1682	.v8_2a,
...	...	@@ -1500,17 +1686,21 @@ pub const cpu = struct {
1500	1686	.name = "ampere1",
1501	1687	.llvm_name = "ampere1",
1502	1688	.features = featureSet(&[_]Feature{
	1689	.addr_lsl_fast,
1503	1690	.aes,
1504	1691	.aggressive_fma,
	1692	.alu_lsl_fast,
1505	1693	.arith_bcc_fusion,
1506	1694	.cmp_bcc_fusion,
1507	1695	.fuse_address,
1508	1696	.fuse_aes,
1509	1697	.fuse_literals,
1510		.lsl_fast,
	1698	.ldp_aligned_only,
1511	1699	.perfmon,
1512	1700	.rand,
1513	1701	.sha3,
	1702	.store_pair_suppress,
	1703	.stp_aligned_only,
1514	1704	.use_postra_scheduler,
1515	1705	.v8_6a,
1516	1706	}),
...	...	@@ -1519,23 +1709,57 @@ pub const cpu = struct {
1519	1709	.name = "ampere1a",
1520	1710	.llvm_name = "ampere1a",
1521	1711	.features = featureSet(&[_]Feature{
	1712	.addr_lsl_fast,
1522	1713	.aes,
1523	1714	.aggressive_fma,
	1715	.alu_lsl_fast,
1524	1716	.arith_bcc_fusion,
1525	1717	.cmp_bcc_fusion,
1526	1718	.fuse_address,
1527	1719	.fuse_aes,
1528	1720	.fuse_literals,
1529		.lsl_fast,
	1721	.ldp_aligned_only,
1530	1722	.mte,
1531	1723	.perfmon,
1532	1724	.rand,
1533	1725	.sha3,
1534	1726	.sm4,
	1727	.store_pair_suppress,
	1728	.stp_aligned_only,
1535	1729	.use_postra_scheduler,
1536	1730	.v8_6a,
1537	1731	}),
1538	1732	};
	1733	pub const ampere1b = CpuModel{
	1734	.name = "ampere1b",
	1735	.llvm_name = "ampere1b",
	1736	.features = featureSet(&[_]Feature{
	1737	.addr_lsl_fast,
	1738	.aes,
	1739	.aggressive_fma,
	1740	.alu_lsl_fast,
	1741	.arith_bcc_fusion,
	1742	.cmp_bcc_fusion,
	1743	.cssc,
	1744	.enable_select_opt,
	1745	.fullfp16,
	1746	.fuse_address,
	1747	.fuse_adrp_add,
	1748	.fuse_aes,
	1749	.fuse_literals,
	1750	.ldp_aligned_only,
	1751	.mte,
	1752	.perfmon,
	1753	.predictable_select_expensive,
	1754	.rand,
	1755	.sha3,
	1756	.sm4,
	1757	.store_pair_suppress,
	1758	.stp_aligned_only,
	1759	.use_postra_scheduler,
	1760	.v8_7a,
	1761	}),
	1762	};
1539	1763	pub const apple_a10 = CpuModel{
1540	1764	.name = "apple_a10",
1541	1765	.llvm_name = "apple-a10",
...	...	@@ -1552,6 +1776,7 @@ pub const cpu = struct {
1552	1776	.pan,
1553	1777	.perfmon,
1554	1778	.rdm,
	1779	.store_pair_suppress,
1555	1780	.v8a,
1556	1781	.vh,
1557	1782	.zcm,
...	...	@@ -1571,6 +1796,7 @@ pub const cpu = struct {
1571	1796	.fuse_aes,
1572	1797	.fuse_crypto_eor,
1573	1798	.perfmon,
	1799	.store_pair_suppress,
1574	1800	.v8_2a,
1575	1801	.zcm,
1576	1802	.zcz,
...	...	@@ -1589,6 +1815,7 @@ pub const cpu = struct {
1589	1815	.fuse_aes,
1590	1816	.fuse_crypto_eor,
1591	1817	.perfmon,
	1818	.store_pair_suppress,
1592	1819	.v8_3a,
1593	1820	.zcm,
1594	1821	.zcz,
...	...	@@ -1608,6 +1835,7 @@ pub const cpu = struct {
1608	1835	.fuse_crypto_eor,
1609	1836	.perfmon,
1610	1837	.sha3,
	1838	.store_pair_suppress,
1611	1839	.v8_4a,
1612	1840	.zcm,
1613	1841	.zcz,
...	...	@@ -1640,6 +1868,7 @@ pub const cpu = struct {
1640	1868	.sha3,
1641	1869	.specrestrict,
1642	1870	.ssbs,
	1871	.store_pair_suppress,
1643	1872	.v8_4a,
1644	1873	.zcm,
1645	1874	.zcz,
...	...	@@ -1663,6 +1892,7 @@ pub const cpu = struct {
1663	1892	.fuse_literals,
1664	1893	.perfmon,
1665	1894	.sha3,
	1895	.store_pair_suppress,
1666	1896	.v8_6a,
1667	1897	.zcm,
1668	1898	.zcz,
...	...	@@ -1687,6 +1917,32 @@ pub const cpu = struct {
1687	1917	.hcx,
1688	1918	.perfmon,
1689	1919	.sha3,
	1920	.store_pair_suppress,
	1921	.v8_6a,
	1922	.zcm,
	1923	.zcz,
	1924	}),
	1925	};
	1926	pub const apple_a17 = CpuModel{
	1927	.name = "apple_a17",
	1928	.llvm_name = "apple-a17",
	1929	.features = featureSet(&[_]Feature{
	1930	.alternate_sextload_cvt_f32_pattern,
	1931	.arith_bcc_fusion,
	1932	.arith_cbz_fusion,
	1933	.crypto,
	1934	.disable_latency_sched_heuristic,
	1935	.fp16fml,
	1936	.fuse_address,
	1937	.fuse_aes,
	1938	.fuse_arith_logic,
	1939	.fuse_crypto_eor,
	1940	.fuse_csel,
	1941	.fuse_literals,
	1942	.hcx,
	1943	.perfmon,
	1944	.sha3,
	1945	.store_pair_suppress,
1690	1946	.v8_6a,
1691	1947	.zcm,
1692	1948	.zcz,
...	...	@@ -1704,6 +1960,7 @@ pub const cpu = struct {
1704	1960	.fuse_aes,
1705	1961	.fuse_crypto_eor,
1706	1962	.perfmon,
	1963	.store_pair_suppress,
1707	1964	.v8a,
1708	1965	.zcm,
1709	1966	.zcz,
...	...	@@ -1722,6 +1979,7 @@ pub const cpu = struct {
1722	1979	.fuse_aes,
1723	1980	.fuse_crypto_eor,
1724	1981	.perfmon,
	1982	.store_pair_suppress,
1725	1983	.v8a,
1726	1984	.zcm,
1727	1985	.zcz,
...	...	@@ -1740,6 +1998,7 @@ pub const cpu = struct {
1740	1998	.fuse_aes,
1741	1999	.fuse_crypto_eor,
1742	2000	.perfmon,
	2001	.store_pair_suppress,
1743	2002	.v8a,
1744	2003	.zcm,
1745	2004	.zcz,
...	...	@@ -1765,6 +2024,7 @@ pub const cpu = struct {
1765	2024	.hcx,
1766	2025	.perfmon,
1767	2026	.sha3,
	2027	.store_pair_suppress,
1768	2028	.v8_6a,
1769	2029	.zcm,
1770	2030	.zcz,
...	...	@@ -1797,6 +2057,7 @@ pub const cpu = struct {
1797	2057	.sha3,
1798	2058	.specrestrict,
1799	2059	.ssbs,
	2060	.store_pair_suppress,
1800	2061	.v8_4a,
1801	2062	.zcm,
1802	2063	.zcz,
...	...	@@ -1820,6 +2081,32 @@ pub const cpu = struct {
1820	2081	.fuse_literals,
1821	2082	.perfmon,
1822	2083	.sha3,
	2084	.store_pair_suppress,
	2085	.v8_6a,
	2086	.zcm,
	2087	.zcz,
	2088	}),
	2089	};
	2090	pub const apple_m3 = CpuModel{
	2091	.name = "apple_m3",
	2092	.llvm_name = "apple-m3",
	2093	.features = featureSet(&[_]Feature{
	2094	.alternate_sextload_cvt_f32_pattern,
	2095	.arith_bcc_fusion,
	2096	.arith_cbz_fusion,
	2097	.crypto,
	2098	.disable_latency_sched_heuristic,
	2099	.fp16fml,
	2100	.fuse_address,
	2101	.fuse_aes,
	2102	.fuse_arith_logic,
	2103	.fuse_crypto_eor,
	2104	.fuse_csel,
	2105	.fuse_literals,
	2106	.hcx,
	2107	.perfmon,
	2108	.sha3,
	2109	.store_pair_suppress,
1823	2110	.v8_6a,
1824	2111	.zcm,
1825	2112	.zcz,
...	...	@@ -1838,6 +2125,7 @@ pub const cpu = struct {
1838	2125	.fuse_aes,
1839	2126	.fuse_crypto_eor,
1840	2127	.perfmon,
	2128	.store_pair_suppress,
1841	2129	.v8_3a,
1842	2130	.zcm,
1843	2131	.zcz,
...	...	@@ -1856,6 +2144,7 @@ pub const cpu = struct {
1856	2144	.fuse_aes,
1857	2145	.fuse_crypto_eor,
1858	2146	.perfmon,
	2147	.store_pair_suppress,
1859	2148	.v8_3a,
1860	2149	.zcm,
1861	2150	.zcz,
...	...	@@ -1905,6 +2194,19 @@ pub const cpu = struct {
1905	2194	.v9a,
1906	2195	}),
1907	2196	};
	2197	pub const cortex_a520 = CpuModel{
	2198	.name = "cortex_a520",
	2199	.llvm_name = "cortex-a520",
	2200	.features = featureSet(&[_]Feature{
	2201	.a520,
	2202	.ete,
	2203	.fp16fml,
	2204	.mte,
	2205	.perfmon,
	2206	.sve2_bitperm,
	2207	.v9_2a,
	2208	}),
	2209	};
1908	2210	pub const cortex_a53 = CpuModel{
1909	2211	.name = "cortex_a53",
1910	2212	.llvm_name = "cortex-a53",
...	...	@@ -1912,7 +2214,6 @@ pub const cpu = struct {
1912	2214	.balance_fp_ops,
1913	2215	.crc,
1914	2216	.crypto,
1915		.custom_cheap_as_move,
1916	2217	.fuse_adrp_add,
1917	2218	.fuse_aes,
1918	2219	.perfmon,
...	...	@@ -1943,7 +2244,6 @@ pub const cpu = struct {
1943	2244	.balance_fp_ops,
1944	2245	.crc,
1945	2246	.crypto,
1946		.custom_cheap_as_move,
1947	2247	.enable_select_opt,
1948	2248	.fuse_adrp_add,
1949	2249	.fuse_aes,
...	...	@@ -2001,6 +2301,8 @@ pub const cpu = struct {
2001	2301	.name = "cortex_a715",
2002	2302	.llvm_name = "cortex-a715",
2003	2303	.features = featureSet(&[_]Feature{
	2304	.addr_lsl_fast,
	2305	.alu_lsl_fast,
2004	2306	.bf16,
2005	2307	.cmp_bcc_fusion,
2006	2308	.enable_select_opt,
...	...	@@ -2009,7 +2311,6 @@ pub const cpu = struct {
2009	2311	.fuse_adrp_add,
2010	2312	.fuse_aes,
2011	2313	.i8mm,
2012		.lsl_fast,
2013	2314	.mte,
2014	2315	.perfmon,
2015	2316	.predictable_select_expensive,
...	...	@@ -2034,6 +2335,21 @@ pub const cpu = struct {
2034	2335	.v8a,
2035	2336	}),
2036	2337	};
	2338	pub const cortex_a720 = CpuModel{
	2339	.name = "cortex_a720",
	2340	.llvm_name = "cortex-a720",
	2341	.features = featureSet(&[_]Feature{
	2342	.a720,
	2343	.ete,
	2344	.fp16fml,
	2345	.mte,
	2346	.perfmon,
	2347	.spe,
	2348	.spe_eef,
	2349	.sve2_bitperm,
	2350	.v9_2a,
	2351	}),
	2352	};
2037	2353	pub const cortex_a73 = CpuModel{
2038	2354	.name = "cortex_a73",
2039	2355	.llvm_name = "cortex-a73",
...	...	@@ -2096,6 +2412,8 @@ pub const cpu = struct {
2096	2412	.name = "cortex_a77",
2097	2413	.llvm_name = "cortex-a77",
2098	2414	.features = featureSet(&[_]Feature{
	2415	.addr_lsl_fast,
	2416	.alu_lsl_fast,
2099	2417	.cmp_bcc_fusion,
2100	2418	.crypto,
2101	2419	.dotprod,
...	...	@@ -2103,7 +2421,6 @@ pub const cpu = struct {
2103	2421	.fullfp16,
2104	2422	.fuse_adrp_add,
2105	2423	.fuse_aes,
2106		.lsl_fast,
2107	2424	.perfmon,
2108	2425	.predictable_select_expensive,
2109	2426	.rcpc,
...	...	@@ -2134,7 +2451,7 @@ pub const cpu = struct {
2134	2451	.crypto,
2135	2452	.dotprod,
2136	2453	.flagm,
2137		.fp16fml,
	2454	.fullfp16,
2138	2455	.pauth,
2139	2456	.perfmon,
2140	2457	.rcpc,
...	...	@@ -2160,6 +2477,8 @@ pub const cpu = struct {
2160	2477	.name = "cortex_x1",
2161	2478	.llvm_name = "cortex-x1",
2162	2479	.features = featureSet(&[_]Feature{
	2480	.addr_lsl_fast,
	2481	.alu_lsl_fast,
2163	2482	.cmp_bcc_fusion,
2164	2483	.crypto,
2165	2484	.dotprod,
...	...	@@ -2167,7 +2486,6 @@ pub const cpu = struct {
2167	2486	.fullfp16,
2168	2487	.fuse_adrp_add,
2169	2488	.fuse_aes,
2170		.lsl_fast,
2171	2489	.perfmon,
2172	2490	.predictable_select_expensive,
2173	2491	.rcpc,
...	...	@@ -2181,6 +2499,8 @@ pub const cpu = struct {
2181	2499	.name = "cortex_x1c",
2182	2500	.llvm_name = "cortex-x1c",
2183	2501	.features = featureSet(&[_]Feature{
	2502	.addr_lsl_fast,
	2503	.alu_lsl_fast,
2184	2504	.cmp_bcc_fusion,
2185	2505	.crypto,
2186	2506	.dotprod,
...	...	@@ -2190,7 +2510,6 @@ pub const cpu = struct {
2190	2510	.fuse_adrp_add,
2191	2511	.fuse_aes,
2192	2512	.lse2,
2193		.lsl_fast,
2194	2513	.pauth,
2195	2514	.perfmon,
2196	2515	.predictable_select_expensive,
...	...	@@ -2205,6 +2524,8 @@ pub const cpu = struct {
2205	2524	.name = "cortex_x2",
2206	2525	.llvm_name = "cortex-x2",
2207	2526	.features = featureSet(&[_]Feature{
	2527	.addr_lsl_fast,
	2528	.alu_lsl_fast,
2208	2529	.bf16,
2209	2530	.cmp_bcc_fusion,
2210	2531	.enable_select_opt,
...	...	@@ -2213,7 +2534,6 @@ pub const cpu = struct {
2213	2534	.fuse_adrp_add,
2214	2535	.fuse_aes,
2215	2536	.i8mm,
2216		.lsl_fast,
2217	2537	.mte,
2218	2538	.perfmon,
2219	2539	.predictable_select_expensive,
...	...	@@ -2226,6 +2546,8 @@ pub const cpu = struct {
2226	2546	.name = "cortex_x3",
2227	2547	.llvm_name = "cortex-x3",
2228	2548	.features = featureSet(&[_]Feature{
	2549	.addr_lsl_fast,
	2550	.alu_lsl_fast,
2229	2551	.bf16,
2230	2552	.enable_select_opt,
2231	2553	.ete,
...	...	@@ -2233,7 +2555,6 @@ pub const cpu = struct {
2233	2555	.fuse_adrp_add,
2234	2556	.fuse_aes,
2235	2557	.i8mm,
2236		.lsl_fast,
2237	2558	.mte,
2238	2559	.perfmon,
2239	2560	.predictable_select_expensive,
...	...	@@ -2243,6 +2564,27 @@ pub const cpu = struct {
2243	2564	.v9a,
2244	2565	}),
2245	2566	};
	2567	pub const cortex_x4 = CpuModel{
	2568	.name = "cortex_x4",
	2569	.llvm_name = "cortex-x4",
	2570	.features = featureSet(&[_]Feature{
	2571	.addr_lsl_fast,
	2572	.alu_lsl_fast,
	2573	.enable_select_opt,
	2574	.ete,
	2575	.fp16fml,
	2576	.fuse_adrp_add,
	2577	.fuse_aes,
	2578	.mte,
	2579	.perfmon,
	2580	.predictable_select_expensive,
	2581	.spe,
	2582	.spe_eef,
	2583	.sve2_bitperm,
	2584	.use_postra_scheduler,
	2585	.v9_2a,
	2586	}),
	2587	};
2246	2588	pub const cyclone = CpuModel{
2247	2589	.name = "cyclone",
2248	2590	.llvm_name = "cyclone",
...	...	@@ -2255,6 +2597,7 @@ pub const cpu = struct {
2255	2597	.fuse_aes,
2256	2598	.fuse_crypto_eor,
2257	2599	.perfmon,
	2600	.store_pair_suppress,
2258	2601	.v8a,
2259	2602	.zcm,
2260	2603	.zcz,
...	...	@@ -2308,6 +2651,8 @@ pub const cpu = struct {
2308	2651	.name = "exynos_m3",
2309	2652	.llvm_name = "exynos-m3",
2310	2653	.features = featureSet(&[_]Feature{
	2654	.addr_lsl_fast,
	2655	.alu_lsl_fast,
2311	2656	.crc,
2312	2657	.crypto,
2313	2658	.exynos_cheap_as_move,
...	...	@@ -2317,9 +2662,9 @@ pub const cpu = struct {
2317	2662	.fuse_aes,
2318	2663	.fuse_csel,
2319	2664	.fuse_literals,
2320		.lsl_fast,
2321	2665	.perfmon,
2322	2666	.predictable_select_expensive,
	2667	.store_pair_suppress,
2323	2668	.use_postra_scheduler,
2324	2669	.v8a,
2325	2670	}),
...	...	@@ -2328,6 +2673,8 @@ pub const cpu = struct {
2328	2673	.name = "exynos_m4",
2329	2674	.llvm_name = "exynos-m4",
2330	2675	.features = featureSet(&[_]Feature{
	2676	.addr_lsl_fast,
	2677	.alu_lsl_fast,
2331	2678	.arith_bcc_fusion,
2332	2679	.arith_cbz_fusion,
2333	2680	.crypto,
...	...	@@ -2341,8 +2688,8 @@ pub const cpu = struct {
2341	2688	.fuse_arith_logic,
2342	2689	.fuse_csel,
2343	2690	.fuse_literals,
2344		.lsl_fast,
2345	2691	.perfmon,
	2692	.store_pair_suppress,
2346	2693	.use_postra_scheduler,
2347	2694	.v8_2a,
2348	2695	.zcz,
...	...	@@ -2352,6 +2699,8 @@ pub const cpu = struct {
2352	2699	.name = "exynos_m5",
2353	2700	.llvm_name = "exynos-m5",
2354	2701	.features = featureSet(&[_]Feature{
	2702	.addr_lsl_fast,
	2703	.alu_lsl_fast,
2355	2704	.arith_bcc_fusion,
2356	2705	.arith_cbz_fusion,
2357	2706	.crypto,
...	...	@@ -2365,8 +2714,8 @@ pub const cpu = struct {
2365	2714	.fuse_arith_logic,
2366	2715	.fuse_csel,
2367	2716	.fuse_literals,
2368		.lsl_fast,
2369	2717	.perfmon,
	2718	.store_pair_suppress,
2370	2719	.use_postra_scheduler,
2371	2720	.v8_2a,
2372	2721	.zcz,
...	...	@@ -2376,14 +2725,15 @@ pub const cpu = struct {
2376	2725	.name = "falkor",
2377	2726	.llvm_name = "falkor",
2378	2727	.features = featureSet(&[_]Feature{
	2728	.addr_lsl_fast,
	2729	.alu_lsl_fast,
2379	2730	.crc,
2380	2731	.crypto,
2381		.custom_cheap_as_move,
2382		.lsl_fast,
2383	2732	.perfmon,
2384	2733	.predictable_select_expensive,
2385	2734	.rdm,
2386	2735	.slow_strqro_store,
	2736	.store_pair_suppress,
2387	2737	.use_postra_scheduler,
2388	2738	.v8a,
2389	2739	.zcz,
...	...	@@ -2405,12 +2755,13 @@ pub const cpu = struct {
2405	2755	.name = "kryo",
2406	2756	.llvm_name = "kryo",
2407	2757	.features = featureSet(&[_]Feature{
	2758	.addr_lsl_fast,
	2759	.alu_lsl_fast,
2408	2760	.crc,
2409	2761	.crypto,
2410		.custom_cheap_as_move,
2411		.lsl_fast,
2412	2762	.perfmon,
2413	2763	.predictable_select_expensive,
	2764	.store_pair_suppress,
2414	2765	.use_postra_scheduler,
2415	2766	.v8a,
2416	2767	.zcz,
...	...	@@ -2420,6 +2771,8 @@ pub const cpu = struct {
2420	2771	.name = "neoverse_512tvb",
2421	2772	.llvm_name = "neoverse-512tvb",
2422	2773	.features = featureSet(&[_]Feature{
	2774	.addr_lsl_fast,
	2775	.alu_lsl_fast,
2423	2776	.bf16,
2424	2777	.ccdp,
2425	2778	.crypto,
...	...	@@ -2428,7 +2781,6 @@ pub const cpu = struct {
2428	2781	.fuse_adrp_add,
2429	2782	.fuse_aes,
2430	2783	.i8mm,
2431		.lsl_fast,
2432	2784	.perfmon,
2433	2785	.predictable_select_expensive,
2434	2786	.rand,
...	...	@@ -2459,13 +2811,14 @@ pub const cpu = struct {
2459	2811	.name = "neoverse_n1",
2460	2812	.llvm_name = "neoverse-n1",
2461	2813	.features = featureSet(&[_]Feature{
	2814	.addr_lsl_fast,
	2815	.alu_lsl_fast,
2462	2816	.crypto,
2463	2817	.dotprod,
2464	2818	.enable_select_opt,
2465	2819	.fullfp16,
2466	2820	.fuse_adrp_add,
2467	2821	.fuse_aes,
2468		.lsl_fast,
2469	2822	.perfmon,
2470	2823	.predictable_select_expensive,
2471	2824	.rcpc,
...	...	@@ -2479,26 +2832,28 @@ pub const cpu = struct {
2479	2832	.name = "neoverse_n2",
2480	2833	.llvm_name = "neoverse-n2",
2481	2834	.features = featureSet(&[_]Feature{
	2835	.addr_lsl_fast,
	2836	.alu_lsl_fast,
2482	2837	.bf16,
2483		.crypto,
2484	2838	.enable_select_opt,
2485	2839	.ete,
2486	2840	.fuse_adrp_add,
2487	2841	.fuse_aes,
2488	2842	.i8mm,
2489		.lsl_fast,
2490	2843	.mte,
2491	2844	.perfmon,
2492	2845	.predictable_select_expensive,
2493	2846	.sve2_bitperm,
2494	2847	.use_postra_scheduler,
2495		.v8_5a,
	2848	.v9a,
2496	2849	}),
2497	2850	};
2498	2851	pub const neoverse_v1 = CpuModel{
2499	2852	.name = "neoverse_v1",
2500	2853	.llvm_name = "neoverse-v1",
2501	2854	.features = featureSet(&[_]Feature{
	2855	.addr_lsl_fast,
	2856	.alu_lsl_fast,
2502	2857	.bf16,
2503	2858	.ccdp,
2504	2859	.crypto,
...	...	@@ -2507,7 +2862,6 @@ pub const cpu = struct {
2507	2862	.fuse_adrp_add,
2508	2863	.fuse_aes,
2509	2864	.i8mm,
2510		.lsl_fast,
2511	2865	.no_sve_fp_ld1r,
2512	2866	.perfmon,
2513	2867	.predictable_select_expensive,
...	...	@@ -2523,13 +2877,15 @@ pub const cpu = struct {
2523	2877	.name = "neoverse_v2",
2524	2878	.llvm_name = "neoverse-v2",
2525	2879	.features = featureSet(&[_]Feature{
	2880	.addr_lsl_fast,
	2881	.alu_lsl_fast,
2526	2882	.bf16,
2527	2883	.enable_select_opt,
2528	2884	.ete,
2529	2885	.fp16fml,
	2886	.fuse_adrp_add,
2530	2887	.fuse_aes,
2531	2888	.i8mm,
2532		.lsl_fast,
2533	2889	.mte,
2534	2890	.perfmon,
2535	2891	.predictable_select_expensive,
...	...	@@ -2544,12 +2900,13 @@ pub const cpu = struct {
2544	2900	.name = "saphira",
2545	2901	.llvm_name = "saphira",
2546	2902	.features = featureSet(&[_]Feature{
	2903	.addr_lsl_fast,
	2904	.alu_lsl_fast,
2547	2905	.crypto,
2548		.custom_cheap_as_move,
2549		.lsl_fast,
2550	2906	.perfmon,
2551	2907	.predictable_select_expensive,
2552	2908	.spe,
	2909	.store_pair_suppress,
2553	2910	.use_postra_scheduler,
2554	2911	.v8_4a,
2555	2912	.zcz,
...	...	@@ -2563,6 +2920,7 @@ pub const cpu = struct {
2563	2920	.crypto,
2564	2921	.perfmon,
2565	2922	.predictable_select_expensive,
	2923	.store_pair_suppress,
2566	2924	.use_postra_scheduler,
2567	2925	.v8a,
2568	2926	}),
...	...	@@ -2575,6 +2933,7 @@ pub const cpu = struct {
2575	2933	.arith_bcc_fusion,
2576	2934	.crypto,
2577	2935	.predictable_select_expensive,
	2936	.store_pair_suppress,
2578	2937	.use_postra_scheduler,
2579	2938	.v8_1a,
2580	2939	}),
...	...	@@ -2589,6 +2948,7 @@ pub const cpu = struct {
2589	2948	.crypto,
2590	2949	.perfmon,
2591	2950	.predictable_select_expensive,
	2951	.store_pair_suppress,
2592	2952	.strict_align,
2593	2953	.use_postra_scheduler,
2594	2954	.v8_3a,
...	...	@@ -2602,6 +2962,7 @@ pub const cpu = struct {
2602	2962	.crypto,
2603	2963	.perfmon,
2604	2964	.predictable_select_expensive,
	2965	.store_pair_suppress,
2605	2966	.use_postra_scheduler,
2606	2967	.v8a,
2607	2968	}),
...	...	@@ -2614,6 +2975,7 @@ pub const cpu = struct {
2614	2975	.crypto,
2615	2976	.perfmon,
2616	2977	.predictable_select_expensive,
	2978	.store_pair_suppress,
2617	2979	.use_postra_scheduler,
2618	2980	.v8a,
2619	2981	}),
...	...	@@ -2626,6 +2988,7 @@ pub const cpu = struct {
2626	2988	.crypto,
2627	2989	.perfmon,
2628	2990	.predictable_select_expensive,
	2991	.store_pair_suppress,
2629	2992	.use_postra_scheduler,
2630	2993	.v8a,
2631	2994	}),
...	...	@@ -2634,13 +2997,15 @@ pub const cpu = struct {
2634	2997	.name = "tsv110",
2635	2998	.llvm_name = "tsv110",
2636	2999	.features = featureSet(&[_]Feature{
	3000	.complxnum,
2637	3001	.crypto,
2638		.custom_cheap_as_move,
2639	3002	.dotprod,
2640	3003	.fp16fml,
2641	3004	.fuse_aes,
	3005	.jsconv,
2642	3006	.perfmon,
2643	3007	.spe,
	3008	.store_pair_suppress,
2644	3009	.use_postra_scheduler,
2645	3010	.v8_2a,
2646	3011	}),

lib/std/Target/amdgpu.zig+269-1

...	...	@@ -13,6 +13,7 @@ pub const Feature = enum {
13	13	architected_sgprs,
14	14	atomic_buffer_global_pk_add_f16_insts,
15	15	atomic_buffer_global_pk_add_f16_no_rtn_insts,
	16	atomic_csub_no_rtn_insts,
16	17	atomic_ds_pk_add_16_insts,
17	18	atomic_fadd_no_rtn_insts,
18	19	atomic_fadd_rtn_insts,
...	...	@@ -22,6 +23,8 @@ pub const Feature = enum {
22	23	back_off_barrier,
23	24	ci_insts,
24	25	cumode,
	26	default_component_broadcast,
	27	default_component_zero,
25	28	dl_insts,
26	29	dot10_insts,
27	30	dot1_insts,
...	...	@@ -36,6 +39,7 @@ pub const Feature = enum {
36	39	dpp,
37	40	dpp8,
38	41	dpp_64bit,
	42	dpp_src1_sgpr,
39	43	ds128,
40	44	ds_src2_insts,
41	45	extended_image_insts,
...	...	@@ -54,10 +58,12 @@ pub const Feature = enum {
54	58	fmaf,
55	59	force_store_sc0_sc1,
56	60	fp64,
	61	fp8_conversion_insts,
57	62	fp8_insts,
58	63	full_rate_64_ops,
59	64	g16,
60	65	gcn3_encoding,
	66	gds,
61	67	get_wave_id_inst,
62	68	gfx10,
63	69	gfx10_3_insts,
...	...	@@ -67,12 +73,15 @@ pub const Feature = enum {
67	73	gfx11,
68	74	gfx11_full_vgprs,
69	75	gfx11_insts,
	76	gfx12,
	77	gfx12_insts,
70	78	gfx7_gfx8_gfx9_insts,
71	79	gfx8_insts,
72	80	gfx9,
73	81	gfx90a_insts,
74	82	gfx940_insts,
75	83	gfx9_insts,
	84	gws,
76	85	half_rate_64_ops,
77	86	image_gather4_d16_bug,
78	87	image_insts,
...	...	@@ -80,6 +89,7 @@ pub const Feature = enum {
80	89	inst_fwd_prefetch_bug,
81	90	int_clamp_insts,
82	91	inv_2pi_inline_imm,
	92	kernarg_preload,
83	93	lds_branch_vmem_war_hazard,
84	94	lds_misaligned_bug,
85	95	ldsbankcount16,
...	...	@@ -97,6 +107,7 @@ pub const Feature = enum {
97	107	mfma_inline_literal_bug,
98	108	mimg_r128,
99	109	movrel,
	110	msaa_load_dst_sel_bug,
100	111	negative_scratch_offset_bug,
101	112	negative_unaligned_scratch_offset_bug,
102	113	no_data_dep_hazard,
...	...	@@ -111,10 +122,15 @@ pub const Feature = enum {
111	122	pk_fmac_f16_inst,
112	123	promote_alloca,
113	124	prt_strict_null,
	125	pseudo_scalar_trans,
114	126	r128_a16,
	127	real_true16,
	128	restricted_soffset,
115	129	s_memrealtime,
116	130	s_memtime_inst,
	131	salu_float,
117	132	scalar_atomics,
	133	scalar_dwordx3_loads,
118	134	scalar_flat_scratch_insts,
119	135	scalar_stores,
120	136	sdwa,
...	...	@@ -125,6 +141,7 @@ pub const Feature = enum {
125	141	sdwa_sdst,
126	142	sea_islands,
127	143	sgpr_init_bug,
	144	shader_cycles_hi_lo_registers,
128	145	shader_cycles_register,
129	146	si_scheduler,
130	147	smem_to_vector_write_hazard,
...	...	@@ -146,6 +163,7 @@ pub const Feature = enum {
146	163	vcmpx_exec_war_hazard,
147	164	vcmpx_permlane_hazard,
148	165	vgpr_index_mode,
	166	vgpr_singleuse_hint,
149	167	vmem_to_scalar_write_hazard,
150	168	volcanic_islands,
151	169	vop3_literal,
...	...	@@ -212,6 +230,11 @@ pub const all_features = blk: {
212	230	.flat_global_insts,
213	231	}),
214	232	};
	233	result[@intFromEnum(Feature.atomic_csub_no_rtn_insts)] = .{
	234	.llvm_name = "atomic-csub-no-rtn-insts",
	235	.description = "Has buffer_atomic_csub and global_atomic_csub instructions that don't return original value",
	236	.dependencies = featureSet(&[_]Feature{}),
	237	};
215	238	result[@intFromEnum(Feature.atomic_ds_pk_add_16_insts)] = .{
216	239	.llvm_name = "atomic-ds-pk-add-16-insts",
217	240	.description = "Has ds_pk_add_bf16, ds_pk_add_f16, ds_pk_add_rtn_bf16, ds_pk_add_rtn_f16 instructions",
...	...	@@ -263,6 +286,16 @@ pub const all_features = blk: {
263	286	.description = "Enable CU wavefront execution mode",
264	287	.dependencies = featureSet(&[_]Feature{}),
265	288	};
	289	result[@intFromEnum(Feature.default_component_broadcast)] = .{
	290	.llvm_name = "default-component-broadcast",
	291	.description = "BUFFER/IMAGE store instructions set unspecified components to x component (GFX12)",
	292	.dependencies = featureSet(&[_]Feature{}),
	293	};
	294	result[@intFromEnum(Feature.default_component_zero)] = .{
	295	.llvm_name = "default-component-zero",
	296	.description = "BUFFER/IMAGE store instructions set unspecified components to zero (before GFX12)",
	297	.dependencies = featureSet(&[_]Feature{}),
	298	};
266	299	result[@intFromEnum(Feature.dl_insts)] = .{
267	300	.llvm_name = "dl-insts",
268	301	.description = "Has v_fmac_f32 and v_xnor_b32 instructions",
...	...	@@ -330,7 +363,12 @@ pub const all_features = blk: {
330	363	};
331	364	result[@intFromEnum(Feature.dpp_64bit)] = .{
332	365	.llvm_name = "dpp-64bit",
333		.description = "Support DPP (Data Parallel Primitives) extension",
	366	.description = "Support DPP (Data Parallel Primitives) extension in DP ALU",
	367	.dependencies = featureSet(&[_]Feature{}),
	368	};
	369	result[@intFromEnum(Feature.dpp_src1_sgpr)] = .{
	370	.llvm_name = "dpp-src1-sgpr",
	371	.description = "Support SGPR for Src1 of DPP instructions",
334	372	.dependencies = featureSet(&[_]Feature{}),
335	373	};
336	374	result[@intFromEnum(Feature.ds128)] = .{
...	...	@@ -423,6 +461,11 @@ pub const all_features = blk: {
423	461	.description = "Enable double precision operations",
424	462	.dependencies = featureSet(&[_]Feature{}),
425	463	};
	464	result[@intFromEnum(Feature.fp8_conversion_insts)] = .{
	465	.llvm_name = "fp8-conversion-insts",
	466	.description = "Has fp8 and bf8 conversion instructions",
	467	.dependencies = featureSet(&[_]Feature{}),
	468	};
426	469	result[@intFromEnum(Feature.fp8_insts)] = .{
427	470	.llvm_name = "fp8-insts",
428	471	.description = "Has fp8 and bf8 instructions",
...	...	@@ -443,6 +486,11 @@ pub const all_features = blk: {
443	486	.description = "Encoding format for VI",
444	487	.dependencies = featureSet(&[_]Feature{}),
445	488	};
	489	result[@intFromEnum(Feature.gds)] = .{
	490	.llvm_name = "gds",
	491	.description = "Has Global Data Share",
	492	.dependencies = featureSet(&[_]Feature{}),
	493	};
446	494	result[@intFromEnum(Feature.get_wave_id_inst)] = .{
447	495	.llvm_name = "get-wave-id-inst",
448	496	.description = "Has s_get_waveid_in_workgroup instruction",
...	...	@@ -457,6 +505,7 @@ pub const all_features = blk: {
457	505	.add_no_carry_insts,
458	506	.aperture_regs,
459	507	.ci_insts,
	508	.default_component_zero,
460	509	.dpp,
461	510	.dpp8,
462	511	.extended_image_insts,
...	...	@@ -469,9 +518,11 @@ pub const all_features = blk: {
469	518	.fma_mix_insts,
470	519	.fp64,
471	520	.g16,
	521	.gds,
472	522	.gfx10_insts,
473	523	.gfx8_insts,
474	524	.gfx9_insts,
	525	.gws,
475	526	.image_insts,
476	527	.int_clamp_insts,
477	528	.inv_2pi_inline_imm,
...	...	@@ -523,6 +574,7 @@ pub const all_features = blk: {
523	574	.add_no_carry_insts,
524	575	.aperture_regs,
525	576	.ci_insts,
	577	.default_component_zero,
526	578	.dpp,
527	579	.dpp8,
528	580	.extended_image_insts,
...	...	@@ -535,6 +587,7 @@ pub const all_features = blk: {
535	587	.fma_mix_insts,
536	588	.fp64,
537	589	.g16,
	590	.gds,
538	591	.gfx10_3_insts,
539	592	.gfx10_a_encoding,
540	593	.gfx10_b_encoding,
...	...	@@ -542,6 +595,7 @@ pub const all_features = blk: {
542	595	.gfx11_insts,
543	596	.gfx8_insts,
544	597	.gfx9_insts,
	598	.gws,
545	599	.int_clamp_insts,
546	600	.inv_2pi_inline_imm,
547	601	.localmemorysize65536,
...	...	@@ -569,6 +623,57 @@ pub const all_features = blk: {
569	623	.description = "Additional instructions for GFX11+",
570	624	.dependencies = featureSet(&[_]Feature{}),
571	625	};
	626	result[@intFromEnum(Feature.gfx12)] = .{
	627	.llvm_name = "gfx12",
	628	.description = "GFX12 GPU generation",
	629	.dependencies = featureSet(&[_]Feature{
	630	.@"16_bit_insts",
	631	.a16,
	632	.add_no_carry_insts,
	633	.aperture_regs,
	634	.ci_insts,
	635	.default_component_broadcast,
	636	.dpp,
	637	.dpp8,
	638	.fast_denormal_f32,
	639	.fast_fmaf,
	640	.flat_address_space,
	641	.flat_global_insts,
	642	.flat_inst_offsets,
	643	.flat_scratch_insts,
	644	.fma_mix_insts,
	645	.fp64,
	646	.g16,
	647	.gfx10_3_insts,
	648	.gfx10_a_encoding,
	649	.gfx10_b_encoding,
	650	.gfx10_insts,
	651	.gfx11_insts,
	652	.gfx12_insts,
	653	.gfx8_insts,
	654	.gfx9_insts,
	655	.int_clamp_insts,
	656	.inv_2pi_inline_imm,
	657	.localmemorysize65536,
	658	.mimg_r128,
	659	.movrel,
	660	.no_data_dep_hazard,
	661	.no_sdst_cmpx,
	662	.pk_fmac_f16_inst,
	663	.true16,
	664	.unaligned_buffer_access,
	665	.unaligned_ds_access,
	666	.vop3_literal,
	667	.vop3p,
	668	.vopd,
	669	.vscnt,
	670	}),
	671	};
	672	result[@intFromEnum(Feature.gfx12_insts)] = .{
	673	.llvm_name = "gfx12-insts",
	674	.description = "Additional instructions for GFX12+",
	675	.dependencies = featureSet(&[_]Feature{}),
	676	};
572	677	result[@intFromEnum(Feature.gfx7_gfx8_gfx9_insts)] = .{
573	678	.llvm_name = "gfx7-gfx8-gfx9-insts",
574	679	.description = "Instructions shared in GFX7, GFX8, GFX9",
...	...	@@ -588,6 +693,7 @@ pub const all_features = blk: {
588	693	.add_no_carry_insts,
589	694	.aperture_regs,
590	695	.ci_insts,
	696	.default_component_zero,
591	697	.dpp,
592	698	.fast_denormal_f32,
593	699	.fast_fmaf,
...	...	@@ -600,6 +706,7 @@ pub const all_features = blk: {
600	706	.gfx7_gfx8_gfx9_insts,
601	707	.gfx8_insts,
602	708	.gfx9_insts,
	709	.gws,
603	710	.int_clamp_insts,
604	711	.inv_2pi_inline_imm,
605	712	.localmemorysize65536,
...	...	@@ -637,6 +744,11 @@ pub const all_features = blk: {
637	744	.description = "Additional instructions for GFX9+",
638	745	.dependencies = featureSet(&[_]Feature{}),
639	746	};
	747	result[@intFromEnum(Feature.gws)] = .{
	748	.llvm_name = "gws",
	749	.description = "Has Global Wave Sync",
	750	.dependencies = featureSet(&[_]Feature{}),
	751	};
640	752	result[@intFromEnum(Feature.half_rate_64_ops)] = .{
641	753	.llvm_name = "half-rate-64-ops",
642	754	.description = "Most fp64 instructions are half rate instead of quarter",
...	...	@@ -672,6 +784,11 @@ pub const all_features = blk: {
672	784	.description = "Has 1 / (2 * pi) as inline immediate",
673	785	.dependencies = featureSet(&[_]Feature{}),
674	786	};
	787	result[@intFromEnum(Feature.kernarg_preload)] = .{
	788	.llvm_name = "kernarg-preload",
	789	.description = "Hardware supports preloading of kernel arguments in user SGPRs.",
	790	.dependencies = featureSet(&[_]Feature{}),
	791	};
675	792	result[@intFromEnum(Feature.lds_branch_vmem_war_hazard)] = .{
676	793	.llvm_name = "lds-branch-vmem-war-hazard",
677	794	.description = "Switching between LDS and VMEM-tex not waiting VM_VSRC=0",
...	...	@@ -757,6 +874,11 @@ pub const all_features = blk: {
757	874	.description = "Has v_movrel*_b32 instructions",
758	875	.dependencies = featureSet(&[_]Feature{}),
759	876	};
	877	result[@intFromEnum(Feature.msaa_load_dst_sel_bug)] = .{
	878	.llvm_name = "msaa-load-dst-sel-bug",
	879	.description = "MSAA loads not honoring dst_sel bug",
	880	.dependencies = featureSet(&[_]Feature{}),
	881	};
760	882	result[@intFromEnum(Feature.negative_scratch_offset_bug)] = .{
761	883	.llvm_name = "negative-scratch-offset-bug",
762	884	.description = "Negative immediate offsets in scratch instructions with an SGPR offset page fault on GFX9",
...	...	@@ -827,11 +949,26 @@ pub const all_features = blk: {
827	949	.description = "Enable zeroing of result registers for sparse texture fetches",
828	950	.dependencies = featureSet(&[_]Feature{}),
829	951	};
	952	result[@intFromEnum(Feature.pseudo_scalar_trans)] = .{
	953	.llvm_name = "pseudo-scalar-trans",
	954	.description = "Has Pseudo Scalar Transcendental instructions",
	955	.dependencies = featureSet(&[_]Feature{}),
	956	};
830	957	result[@intFromEnum(Feature.r128_a16)] = .{
831	958	.llvm_name = "r128-a16",
832	959	.description = "Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128",
833	960	.dependencies = featureSet(&[_]Feature{}),
834	961	};
	962	result[@intFromEnum(Feature.real_true16)] = .{
	963	.llvm_name = "real-true16",
	964	.description = "Use true 16-bit registers",
	965	.dependencies = featureSet(&[_]Feature{}),
	966	};
	967	result[@intFromEnum(Feature.restricted_soffset)] = .{
	968	.llvm_name = "restricted-soffset",
	969	.description = "Has restricted SOffset (immediate not supported).",
	970	.dependencies = featureSet(&[_]Feature{}),
	971	};
835	972	result[@intFromEnum(Feature.s_memrealtime)] = .{
836	973	.llvm_name = "s-memrealtime",
837	974	.description = "Has s_memrealtime instruction",
...	...	@@ -842,11 +979,21 @@ pub const all_features = blk: {
842	979	.description = "Has s_memtime instruction",
843	980	.dependencies = featureSet(&[_]Feature{}),
844	981	};
	982	result[@intFromEnum(Feature.salu_float)] = .{
	983	.llvm_name = "salu-float",
	984	.description = "Has SALU floating point instructions",
	985	.dependencies = featureSet(&[_]Feature{}),
	986	};
845	987	result[@intFromEnum(Feature.scalar_atomics)] = .{
846	988	.llvm_name = "scalar-atomics",
847	989	.description = "Has atomic scalar memory instructions",
848	990	.dependencies = featureSet(&[_]Feature{}),
849	991	};
	992	result[@intFromEnum(Feature.scalar_dwordx3_loads)] = .{
	993	.llvm_name = "scalar-dwordx3-loads",
	994	.description = "Has 96-bit scalar load instructions",
	995	.dependencies = featureSet(&[_]Feature{}),
	996	};
850	997	result[@intFromEnum(Feature.scalar_flat_scratch_insts)] = .{
851	998	.llvm_name = "scalar-flat-scratch-insts",
852	999	.description = "Have s_scratch_* flat memory instructions",
...	...	@@ -892,11 +1039,14 @@ pub const all_features = blk: {
892	1039	.description = "SEA_ISLANDS GPU generation",
893	1040	.dependencies = featureSet(&[_]Feature{
894	1041	.ci_insts,
	1042	.default_component_zero,
895	1043	.ds_src2_insts,
896	1044	.extended_image_insts,
897	1045	.flat_address_space,
898	1046	.fp64,
	1047	.gds,
899	1048	.gfx7_gfx8_gfx9_insts,
	1049	.gws,
900	1050	.image_insts,
901	1051	.localmemorysize65536,
902	1052	.mad_mac_f32_insts,
...	...	@@ -913,6 +1063,11 @@ pub const all_features = blk: {
913	1063	.description = "VI SGPR initialization bug requiring a fixed SGPR allocation size",
914	1064	.dependencies = featureSet(&[_]Feature{}),
915	1065	};
	1066	result[@intFromEnum(Feature.shader_cycles_hi_lo_registers)] = .{
	1067	.llvm_name = "shader-cycles-hi-lo-registers",
	1068	.description = "Has SHADER_CYCLES_HI/LO hardware registers",
	1069	.dependencies = featureSet(&[_]Feature{}),
	1070	};
916	1071	result[@intFromEnum(Feature.shader_cycles_register)] = .{
917	1072	.llvm_name = "shader-cycles-register",
918	1073	.description = "Has SHADER_CYCLES hardware register",
...	...	@@ -932,9 +1087,12 @@ pub const all_features = blk: {
932	1087	.llvm_name = "southern-islands",
933	1088	.description = "SOUTHERN_ISLANDS GPU generation",
934	1089	.dependencies = featureSet(&[_]Feature{
	1090	.default_component_zero,
935	1091	.ds_src2_insts,
936	1092	.extended_image_insts,
937	1093	.fp64,
	1094	.gds,
	1095	.gws,
938	1096	.image_insts,
939	1097	.ldsbankcount32,
940	1098	.localmemorysize32768,
...	...	@@ -1031,6 +1189,11 @@ pub const all_features = blk: {
1031	1189	.description = "Has VGPR mode register indexing",
1032	1190	.dependencies = featureSet(&[_]Feature{}),
1033	1191	};
	1192	result[@intFromEnum(Feature.vgpr_singleuse_hint)] = .{
	1193	.llvm_name = "vgpr-singleuse-hint",
	1194	.description = "Has single-use VGPR hint instructions",
	1195	.dependencies = featureSet(&[_]Feature{}),
	1196	};
1034	1197	result[@intFromEnum(Feature.vmem_to_scalar_write_hazard)] = .{
1035	1198	.llvm_name = "vmem-to-scalar-write-hazard",
1036	1199	.description = "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution.",
...	...	@@ -1042,6 +1205,7 @@ pub const all_features = blk: {
1042	1205	.dependencies = featureSet(&[_]Feature{
1043	1206	.@"16_bit_insts",
1044	1207	.ci_insts,
	1208	.default_component_zero,
1045	1209	.dpp,
1046	1210	.ds_src2_insts,
1047	1211	.extended_image_insts,
...	...	@@ -1049,8 +1213,10 @@ pub const all_features = blk: {
1049	1213	.flat_address_space,
1050	1214	.fp64,
1051	1215	.gcn3_encoding,
	1216	.gds,
1052	1217	.gfx7_gfx8_gfx9_insts,
1053	1218	.gfx8_insts,
	1219	.gws,
1054	1220	.image_insts,
1055	1221	.int_clamp_insts,
1056	1222	.inv_2pi_inline_imm,
...	...	@@ -1157,6 +1323,8 @@ pub const cpu = struct {
1157	1323	.name = "generic",
1158	1324	.llvm_name = "generic",
1159	1325	.features = featureSet(&[_]Feature{
	1326	.gds,
	1327	.gws,
1160	1328	.wavefrontsize64,
1161	1329	}),
1162	1330	};
...	...	@@ -1165,6 +1333,8 @@ pub const cpu = struct {
1165	1333	.llvm_name = "generic-hsa",
1166	1334	.features = featureSet(&[_]Feature{
1167	1335	.flat_address_space,
	1336	.gds,
	1337	.gws,
1168	1338	.wavefrontsize64,
1169	1339	}),
1170	1340	};
...	...	@@ -1478,6 +1648,7 @@ pub const cpu = struct {
1478	1648	.image_insts,
1479	1649	.ldsbankcount32,
1480	1650	.mad_intra_fwd_bug,
	1651	.msaa_load_dst_sel_bug,
1481	1652	.nsa_encoding,
1482	1653	.packed_tid,
1483	1654	.partial_nsa_encoding,
...	...	@@ -1507,6 +1678,7 @@ pub const cpu = struct {
1507	1678	.image_insts,
1508	1679	.ldsbankcount32,
1509	1680	.mad_intra_fwd_bug,
	1681	.msaa_load_dst_sel_bug,
1510	1682	.nsa_encoding,
1511	1683	.packed_tid,
1512	1684	.partial_nsa_encoding,
...	...	@@ -1534,6 +1706,7 @@ pub const cpu = struct {
1534	1706	.image_insts,
1535	1707	.ldsbankcount32,
1536	1708	.mad_intra_fwd_bug,
	1709	.msaa_load_dst_sel_bug,
1537	1710	.nsa_encoding,
1538	1711	.packed_tid,
1539	1712	.partial_nsa_encoding,
...	...	@@ -1562,6 +1735,7 @@ pub const cpu = struct {
1562	1735	.image_insts,
1563	1736	.ldsbankcount32,
1564	1737	.mad_intra_fwd_bug,
	1738	.msaa_load_dst_sel_bug,
1565	1739	.nsa_encoding,
1566	1740	.packed_tid,
1567	1741	.partial_nsa_encoding,
...	...	@@ -1584,6 +1758,7 @@ pub const cpu = struct {
1584	1758	.dot7_insts,
1585	1759	.dot8_insts,
1586	1760	.dot9_insts,
	1761	.dpp_src1_sgpr,
1587	1762	.flat_atomic_fadd_f32_inst,
1588	1763	.gfx11,
1589	1764	.image_insts,
...	...	@@ -1592,8 +1767,10 @@ pub const cpu = struct {
1592	1767	.nsa_encoding,
1593	1768	.packed_tid,
1594	1769	.partial_nsa_encoding,
	1770	.salu_float,
1595	1771	.shader_cycles_register,
1596	1772	.vcmpx_permlane_hazard,
	1773	.vgpr_singleuse_hint,
1597	1774	.wavefrontsize32,
1598	1775	}),
1599	1776	};
...	...	@@ -1610,6 +1787,7 @@ pub const cpu = struct {
1610	1787	.dot7_insts,
1611	1788	.dot8_insts,
1612	1789	.dot9_insts,
	1790	.dpp_src1_sgpr,
1613	1791	.flat_atomic_fadd_f32_inst,
1614	1792	.gfx11,
1615	1793	.gfx11_full_vgprs,
...	...	@@ -1619,8 +1797,84 @@ pub const cpu = struct {
1619	1797	.nsa_encoding,
1620	1798	.packed_tid,
1621	1799	.partial_nsa_encoding,
	1800	.salu_float,
1622	1801	.shader_cycles_register,
1623	1802	.vcmpx_permlane_hazard,
	1803	.vgpr_singleuse_hint,
	1804	.wavefrontsize32,
	1805	}),
	1806	};
	1807	pub const gfx1200 = CpuModel{
	1808	.name = "gfx1200",
	1809	.llvm_name = "gfx1200",
	1810	.features = featureSet(&[_]Feature{
	1811	.architected_flat_scratch,
	1812	.architected_sgprs,
	1813	.atomic_buffer_global_pk_add_f16_insts,
	1814	.atomic_ds_pk_add_16_insts,
	1815	.atomic_fadd_no_rtn_insts,
	1816	.atomic_fadd_rtn_insts,
	1817	.atomic_flat_pk_add_16_insts,
	1818	.atomic_global_pk_add_bf16_inst,
	1819	.dl_insts,
	1820	.dot10_insts,
	1821	.dot7_insts,
	1822	.dot8_insts,
	1823	.dot9_insts,
	1824	.dpp_src1_sgpr,
	1825	.extended_image_insts,
	1826	.flat_atomic_fadd_f32_inst,
	1827	.fp8_conversion_insts,
	1828	.gfx12,
	1829	.image_insts,
	1830	.ldsbankcount32,
	1831	.nsa_encoding,
	1832	.packed_tid,
	1833	.partial_nsa_encoding,
	1834	.pseudo_scalar_trans,
	1835	.restricted_soffset,
	1836	.salu_float,
	1837	.scalar_dwordx3_loads,
	1838	.shader_cycles_hi_lo_registers,
	1839	.vcmpx_permlane_hazard,
	1840	.vgpr_singleuse_hint,
	1841	.wavefrontsize32,
	1842	}),
	1843	};
	1844	pub const gfx1201 = CpuModel{
	1845	.name = "gfx1201",
	1846	.llvm_name = "gfx1201",
	1847	.features = featureSet(&[_]Feature{
	1848	.architected_flat_scratch,
	1849	.architected_sgprs,
	1850	.atomic_buffer_global_pk_add_f16_insts,
	1851	.atomic_ds_pk_add_16_insts,
	1852	.atomic_fadd_no_rtn_insts,
	1853	.atomic_fadd_rtn_insts,
	1854	.atomic_flat_pk_add_16_insts,
	1855	.atomic_global_pk_add_bf16_inst,
	1856	.dl_insts,
	1857	.dot10_insts,
	1858	.dot7_insts,
	1859	.dot8_insts,
	1860	.dot9_insts,
	1861	.dpp_src1_sgpr,
	1862	.extended_image_insts,
	1863	.flat_atomic_fadd_f32_inst,
	1864	.fp8_conversion_insts,
	1865	.gfx12,
	1866	.image_insts,
	1867	.ldsbankcount32,
	1868	.nsa_encoding,
	1869	.packed_tid,
	1870	.partial_nsa_encoding,
	1871	.pseudo_scalar_trans,
	1872	.restricted_soffset,
	1873	.salu_float,
	1874	.scalar_dwordx3_loads,
	1875	.shader_cycles_hi_lo_registers,
	1876	.vcmpx_permlane_hazard,
	1877	.vgpr_singleuse_hint,
1624	1878	.wavefrontsize32,
1625	1879	}),
1626	1880	};
...	...	@@ -1756,6 +2010,7 @@ pub const cpu = struct {
1756	2010	.features = featureSet(&[_]Feature{
1757	2011	.ds_src2_insts,
1758	2012	.extended_image_insts,
	2013	.gds,
1759	2014	.gfx9,
1760	2015	.image_gather4_d16_bug,
1761	2016	.image_insts,
...	...	@@ -1770,6 +2025,7 @@ pub const cpu = struct {
1770	2025	.features = featureSet(&[_]Feature{
1771	2026	.ds_src2_insts,
1772	2027	.extended_image_insts,
	2028	.gds,
1773	2029	.gfx9,
1774	2030	.image_gather4_d16_bug,
1775	2031	.image_insts,
...	...	@@ -1785,6 +2041,7 @@ pub const cpu = struct {
1785	2041	.ds_src2_insts,
1786	2042	.extended_image_insts,
1787	2043	.fma_mix_insts,
	2044	.gds,
1788	2045	.gfx9,
1789	2046	.image_gather4_d16_bug,
1790	2047	.image_insts,
...	...	@@ -1804,6 +2061,7 @@ pub const cpu = struct {
1804	2061	.ds_src2_insts,
1805	2062	.extended_image_insts,
1806	2063	.fma_mix_insts,
	2064	.gds,
1807	2065	.gfx9,
1808	2066	.half_rate_64_ops,
1809	2067	.image_gather4_d16_bug,
...	...	@@ -1831,6 +2089,7 @@ pub const cpu = struct {
1831	2089	.ds_src2_insts,
1832	2090	.extended_image_insts,
1833	2091	.fma_mix_insts,
	2092	.gds,
1834	2093	.gfx9,
1835	2094	.half_rate_64_ops,
1836	2095	.image_gather4_d16_bug,
...	...	@@ -1849,6 +2108,7 @@ pub const cpu = struct {
1849	2108	.features = featureSet(&[_]Feature{
1850	2109	.ds_src2_insts,
1851	2110	.extended_image_insts,
	2111	.gds,
1852	2112	.gfx9,
1853	2113	.image_gather4_d16_bug,
1854	2114	.image_insts,
...	...	@@ -1881,6 +2141,7 @@ pub const cpu = struct {
1881	2141	.gfx9,
1882	2142	.gfx90a_insts,
1883	2143	.image_insts,
	2144	.kernarg_preload,
1884	2145	.ldsbankcount32,
1885	2146	.mad_mac_f32_insts,
1886	2147	.mai_insts,
...	...	@@ -1896,6 +2157,7 @@ pub const cpu = struct {
1896	2157	.features = featureSet(&[_]Feature{
1897	2158	.ds_src2_insts,
1898	2159	.extended_image_insts,
	2160	.gds,
1899	2161	.gfx9,
1900	2162	.image_gather4_d16_bug,
1901	2163	.image_insts,
...	...	@@ -1930,11 +2192,13 @@ pub const cpu = struct {
1930	2192	.fma_mix_insts,
1931	2193	.fmacf64_inst,
1932	2194	.force_store_sc0_sc1,
	2195	.fp8_conversion_insts,
1933	2196	.fp8_insts,
1934	2197	.full_rate_64_ops,
1935	2198	.gfx9,
1936	2199	.gfx90a_insts,
1937	2200	.gfx940_insts,
	2201	.kernarg_preload,
1938	2202	.ldsbankcount32,
1939	2203	.mai_insts,
1940	2204	.packed_fp32_ops,
...	...	@@ -1969,11 +2233,13 @@ pub const cpu = struct {
1969	2233	.fma_mix_insts,
1970	2234	.fmacf64_inst,
1971	2235	.force_store_sc0_sc1,
	2236	.fp8_conversion_insts,
1972	2237	.fp8_insts,
1973	2238	.full_rate_64_ops,
1974	2239	.gfx9,
1975	2240	.gfx90a_insts,
1976	2241	.gfx940_insts,
	2242	.kernarg_preload,
1977	2243	.ldsbankcount32,
1978	2244	.mai_insts,
1979	2245	.packed_fp32_ops,
...	...	@@ -2007,11 +2273,13 @@ pub const cpu = struct {
2007	2273	.flat_atomic_fadd_f32_inst,
2008	2274	.fma_mix_insts,
2009	2275	.fmacf64_inst,
	2276	.fp8_conversion_insts,
2010	2277	.fp8_insts,
2011	2278	.full_rate_64_ops,
2012	2279	.gfx9,
2013	2280	.gfx90a_insts,
2014	2281	.gfx940_insts,
	2282	.kernarg_preload,
2015	2283	.ldsbankcount32,
2016	2284	.mai_insts,
2017	2285	.packed_fp32_ops,

lib/std/Target/arm.zig+41-1

...	...	@@ -186,6 +186,8 @@ pub const Feature = enum {
186	186	v9_2a,
187	187	v9_3a,
188	188	v9_4a,
	189	v9_5a,
	190	v9_5a,
189	191	v9a,
190	192	vfp2,
191	193	vfp2sp,
...	...	@@ -1572,6 +1574,29 @@ pub const all_features = blk: {
1572	1574	.virtualization,
1573	1575	}),
1574	1576	};
	1577	result[@intFromEnum(Feature.v9_5a)] = .{
	1578	.llvm_name = "armv9.5-a",
	1579	.description = "ARMv95a architecture",
	1580	.dependencies = featureSet(&[_]Feature{
	1581	.aclass,
	1582	.crc,
	1583	.db,
	1584	.dsp,
	1585	.fp_armv8,
	1586	.mp,
	1587	.ras,
	1588	.trustzone,
	1589	.v9_5a,
	1590	.virtualization,
	1591	}),
	1592	};
	1593	result[@intFromEnum(Feature.v9_5a)] = .{
	1594	.llvm_name = "v9.5a",
	1595	.description = "Support ARM v9.5a instructions",
	1596	.dependencies = featureSet(&[_]Feature{
	1597	.has_v9_4a,
	1598	}),
	1599	};
1575	1600	result[@intFromEnum(Feature.v9a)] = .{
1576	1601	.llvm_name = "armv9-a",
1577	1602	.description = "ARMv9a architecture",
...	...	@@ -2238,6 +2263,21 @@ pub const cpu = struct {
2238	2263	.v7em,
2239	2264	}),
2240	2265	};
	2266	pub const cortex_m52 = CpuModel{
	2267	.name = "cortex_m52",
	2268	.llvm_name = "cortex-m52",
	2269	.features = featureSet(&[_]Feature{
	2270	.fp_armv8d16,
	2271	.loop_align,
	2272	.mve1beat,
	2273	.mve_fp,
	2274	.no_branch_predictor,
	2275	.pacbti,
	2276	.slowfpvmlx,
	2277	.use_misched,
	2278	.v8_1m_main,
	2279	}),
	2280	};
2241	2281	pub const cortex_m55 = CpuModel{
2242	2282	.name = "cortex_m55",
2243	2283	.llvm_name = "cortex-m55",
...	...	@@ -2499,7 +2539,7 @@ pub const cpu = struct {
2499	2539	.features = featureSet(&[_]Feature{
2500	2540	.bf16,
2501	2541	.i8mm,
2502		.v8_5a,
	2542	.v9a,
2503	2543	}),
2504	2544	};
2505	2545	pub const neoverse_v1 = CpuModel{

lib/std/Target/bpf.zig+7

...	...	@@ -70,4 +70,11 @@ pub const cpu = struct {
70	70	.alu32,
71	71	}),
72	72	};
	73	pub const v4 = CpuModel{
	74	.name = "v4",
	75	.llvm_name = "v4",
	76	.features = featureSet(&[_]Feature{
	77	.alu32,
	78	}),
	79	};
73	80	};

lib/std/Target/loongarch.zig+18

...	...	@@ -7,8 +7,10 @@ const CpuModel = std.Target.Cpu.Model;
7	7	pub const Feature = enum {
8	8	@"32bit",
9	9	@"64bit",
	10	auto_vec,
10	11	d,
11	12	f,
	13	frecipe,
12	14	la_global_with_abs,
13	15	la_global_with_pcrel,
14	16	la_local_with_abs,
...	...	@@ -16,6 +18,7 @@ pub const Feature = enum {
16	18	lbt,
17	19	lsx,
18	20	lvz,
	21	relax,
19	22	ual,
20	23	};
21	24
...	...	@@ -38,6 +41,11 @@ pub const all_features = blk: {
38	41	.description = "LA64 Basic Integer and Privilege Instruction Set",
39	42	.dependencies = featureSet(&[_]Feature{}),
40	43	};
	44	result[@intFromEnum(Feature.auto_vec)] = .{
	45	.llvm_name = "auto-vec",
	46	.description = "Experimental auto vectorization",
	47	.dependencies = featureSet(&[_]Feature{}),
	48	};
41	49	result[@intFromEnum(Feature.d)] = .{
42	50	.llvm_name = "d",
43	51	.description = "'D' (Double-Precision Floating-Point)",
...	...	@@ -50,6 +58,11 @@ pub const all_features = blk: {
50	58	.description = "'F' (Single-Precision Floating-Point)",
51	59	.dependencies = featureSet(&[_]Feature{}),
52	60	};
	61	result[@intFromEnum(Feature.frecipe)] = .{
	62	.llvm_name = "frecipe",
	63	.description = "Support frecipe.{s/d} and frsqrte.{s/d} instructions.",
	64	.dependencies = featureSet(&[_]Feature{}),
	65	};
53	66	result[@intFromEnum(Feature.la_global_with_abs)] = .{
54	67	.llvm_name = "la-global-with-abs",
55	68	.description = "Expand la.global as la.abs",
...	...	@@ -89,6 +102,11 @@ pub const all_features = blk: {
89	102	.description = "'LVZ' (Loongson Virtualization Extension)",
90	103	.dependencies = featureSet(&[_]Feature{}),
91	104	};
	105	result[@intFromEnum(Feature.relax)] = .{
	106	.llvm_name = "relax",
	107	.description = "Enable Linker relaxation",
	108	.dependencies = featureSet(&[_]Feature{}),
	109	};
92	110	result[@intFromEnum(Feature.ual)] = .{
93	111	.llvm_name = "ual",
94	112	.description = "Allow memory accesses to be unaligned",

lib/std/Target/nvptx.zig+26

...	...	@@ -27,6 +27,8 @@ pub const Feature = enum {
27	27	ptx78,
28	28	ptx80,
29	29	ptx81,
	30	ptx82,
	31	ptx83,
30	32	sm_20,
31	33	sm_21,
32	34	sm_30,
...	...	@@ -47,6 +49,7 @@ pub const Feature = enum {
47	49	sm_87,
48	50	sm_89,
49	51	sm_90,
	52	sm_90a,
50	53	};
51	54
52	55	pub const featureSet = CpuFeature.feature_set_fns(Feature).featureSet;
...	...	@@ -168,6 +171,16 @@ pub const all_features = blk: {
168	171	.description = "Use PTX version 81",
169	172	.dependencies = featureSet(&[_]Feature{}),
170	173	};
	174	result[@intFromEnum(Feature.ptx82)] = .{
	175	.llvm_name = "ptx82",
	176	.description = "Use PTX version 82",
	177	.dependencies = featureSet(&[_]Feature{}),
	178	};
	179	result[@intFromEnum(Feature.ptx83)] = .{
	180	.llvm_name = "ptx83",
	181	.description = "Use PTX version 83",
	182	.dependencies = featureSet(&[_]Feature{}),
	183	};
171	184	result[@intFromEnum(Feature.sm_20)] = .{
172	185	.llvm_name = "sm_20",
173	186	.description = "Target SM 20",
...	...	@@ -268,6 +281,11 @@ pub const all_features = blk: {
268	281	.description = "Target SM 90",
269	282	.dependencies = featureSet(&[_]Feature{}),
270	283	};
	284	result[@intFromEnum(Feature.sm_90a)] = .{
	285	.llvm_name = "sm_90a",
	286	.description = "Target SM 90a",
	287	.dependencies = featureSet(&[_]Feature{}),
	288	};
271	289	const ti = @typeInfo(Feature);
272	290	for (&result, 0..) \|*elem, i\| {
273	291	elem.index = i;
...	...	@@ -436,4 +454,12 @@ pub const cpu = struct {
436	454	.sm_90,
437	455	}),
438	456	};
	457	pub const sm_90a = CpuModel{
	458	.name = "sm_90a",
	459	.llvm_name = "sm_90a",
	460	.features = featureSet(&[_]Feature{
	461	.ptx80,
	462	.sm_90a,
	463	}),
	464	};
439	465	};

lib/std/Target/powerpc.zig+6

...	...	@@ -8,6 +8,7 @@ pub const Feature = enum {
8	8	@"64bit",
9	9	@"64bitregs",
10	10	aix,
	11	aix_small_local_exec_tls,
11	12	allow_unaligned_fp_access,
12	13	altivec,
13	14	booke,
...	...	@@ -112,6 +113,11 @@ pub const all_features = blk: {
112	113	.description = "AIX OS",
113	114	.dependencies = featureSet(&[_]Feature{}),
114	115	};
	116	result[@intFromEnum(Feature.aix_small_local_exec_tls)] = .{
	117	.llvm_name = "aix-small-local-exec-tls",
	118	.description = "Produce a TOC-free local-exec TLS sequence for this function for 64-bit AIX",
	119	.dependencies = featureSet(&[_]Feature{}),
	120	};
115	121	result[@intFromEnum(Feature.allow_unaligned_fp_access)] = .{
116	122	.llvm_name = "allow-unaligned-fp-access",
117	123	.description = "CPU does not trap on unaligned FP access",

lib/std/Target/riscv.zig+482-134

...	...	@@ -8,38 +8,28 @@ pub const Feature = enum {
8	8	@"32bit",
9	9	@"64bit",
10	10	a,
	11	auipc_addi_fusion,
11	12	c,
	13	conditional_cmv_fusion,
12	14	d,
13	15	dlen_factor_2,
14	16	e,
15		experimental_smaia,
16		experimental_ssaia,
	17	experimental,
17	18	experimental_zacas,
18		experimental_zfa,
	19	experimental_zcmop,
19	20	experimental_zfbfmin,
20		experimental_zicond,
21		experimental_zihintntl,
	21	experimental_zicfilp,
	22	experimental_zicfiss,
	23	experimental_zimop,
22	24	experimental_ztso,
23		experimental_zvbb,
24		experimental_zvbc,
25	25	experimental_zvfbfmin,
26	26	experimental_zvfbfwma,
27		experimental_zvkg,
28		experimental_zvkn,
29		experimental_zvknc,
30		experimental_zvkned,
31		experimental_zvkng,
32		experimental_zvknha,
33		experimental_zvknhb,
34		experimental_zvks,
35		experimental_zvksc,
36		experimental_zvksed,
37		experimental_zvksg,
38		experimental_zvksh,
39		experimental_zvkt,
40	27	f,
	28	fast_unaligned_access,
41	29	forced_atomics,
42	30	h,
	31	i,
	32	ld_add_fusion,
43	33	lui_addi_fusion,
44	34	m,
45	35	no_default_unroll,
...	...	@@ -79,18 +69,30 @@ pub const Feature = enum {
79	69	reserve_x9,
80	70	save_restore,
81	71	seq_cst_trailing_fence,
	72	shifted_zextw_fusion,
82	73	short_forward_branch_opt,
	74	smaia,
	75	smepmp,
	76	ssaia,
83	77	svinval,
84	78	svnapot,
85	79	svpbmt,
86	80	tagged_globals,
87		unaligned_scalar_mem,
88		unaligned_vector_mem,
	81	use_postra_scheduler,
89	82	v,
	83	ventana_veyron,
	84	xcvalu,
	85	xcvbi,
90	86	xcvbitmanip,
	87	xcvelw,
91	88	xcvmac,
92		xsfcie,
	89	xcvmem,
	90	xcvsimd,
93	91	xsfvcp,
	92	xsfvfnrclipxfqf,
	93	xsfvfwmaccqqq,
	94	xsfvqmaccdod,
	95	xsfvqmaccqoq,
94	96	xtheadba,
95	97	xtheadbb,
96	98	xtheadbs,
...	...	@@ -103,6 +105,8 @@ pub const Feature = enum {
103	105	xtheadsync,
104	106	xtheadvdot,
105	107	xventanacondops,
	108	za128rs,
	109	za64rs,
106	110	zawrs,
107	111	zba,
108	112	zbb,
...	...	@@ -119,17 +123,27 @@ pub const Feature = enum {
119	123	zcmp,
120	124	zcmt,
121	125	zdinx,
	126	zexth_fusion,
	127	zextw_fusion,
	128	zfa,
122	129	zfh,
123	130	zfhmin,
124	131	zfinx,
125	132	zhinx,
126	133	zhinxmin,
	134	zic64b,
127	135	zicbom,
128	136	zicbop,
129	137	zicboz,
	138	ziccamoa,
	139	ziccif,
	140	zicclsm,
	141	ziccrse,
130	142	zicntr,
	143	zicond,
131	144	zicsr,
132	145	zifencei,
	146	zihintntl,
133	147	zihintpause,
134	148	zihpm,
135	149	zk,
...	...	@@ -143,12 +157,29 @@ pub const Feature = enum {
143	157	zksh,
144	158	zkt,
145	159	zmmul,
	160	zvbb,
	161	zvbc,
146	162	zve32f,
147	163	zve32x,
148	164	zve64d,
149	165	zve64f,
150	166	zve64x,
151	167	zvfh,
	168	zvfhmin,
	169	zvkb,
	170	zvkg,
	171	zvkn,
	172	zvknc,
	173	zvkned,
	174	zvkng,
	175	zvknha,
	176	zvknhb,
	177	zvks,
	178	zvksc,
	179	zvksed,
	180	zvksg,
	181	zvksh,
	182	zvkt,
152	183	zvl1024b,
153	184	zvl128b,
154	185	zvl16384b,
...	...	@@ -187,11 +218,21 @@ pub const all_features = blk: {
187	218	.description = "'A' (Atomic Instructions)",
188	219	.dependencies = featureSet(&[_]Feature{}),
189	220	};
	221	result[@intFromEnum(Feature.auipc_addi_fusion)] = .{
	222	.llvm_name = "auipc-addi-fusion",
	223	.description = "Enable AUIPC+ADDI macrofusion",
	224	.dependencies = featureSet(&[_]Feature{}),
	225	};
190	226	result[@intFromEnum(Feature.c)] = .{
191	227	.llvm_name = "c",
192	228	.description = "'C' (Compressed Instructions)",
193	229	.dependencies = featureSet(&[_]Feature{}),
194	230	};
	231	result[@intFromEnum(Feature.conditional_cmv_fusion)] = .{
	232	.llvm_name = "conditional-cmv-fusion",
	233	.description = "Enable branch+c.mv fusion",
	234	.dependencies = featureSet(&[_]Feature{}),
	235	};
195	236	result[@intFromEnum(Feature.d)] = .{
196	237	.llvm_name = "d",
197	238	.description = "'D' (Double-Precision Floating-Point)",
...	...	@@ -209,14 +250,9 @@ pub const all_features = blk: {
209	250	.description = "Implements RV{32,64}E (provides 16 rather than 32 GPRs)",
210	251	.dependencies = featureSet(&[_]Feature{}),
211	252	};
212		result[@intFromEnum(Feature.experimental_smaia)] = .{
213		.llvm_name = "experimental-smaia",
214		.description = "'Smaia' (Smaia encompasses all added CSRs and all modifications to interrupt response behavior that the AIA specifies for a hart, over all privilege levels.)",
215		.dependencies = featureSet(&[_]Feature{}),
216		};
217		result[@intFromEnum(Feature.experimental_ssaia)] = .{
218		.llvm_name = "experimental-ssaia",
219		.description = "'Ssaia' (Ssaia is essentially the same as Smaia except excluding the machine-level CSRs and behavior not directly visible to supervisor level.)",
	253	result[@intFromEnum(Feature.experimental)] = .{
	254	.llvm_name = "experimental",
	255	.description = "Experimental intrinsics",
220	256	.dependencies = featureSet(&[_]Feature{}),
221	257	};
222	258	result[@intFromEnum(Feature.experimental_zacas)] = .{
...	...	@@ -224,11 +260,11 @@ pub const all_features = blk: {
224	260	.description = "'Zacas' (Atomic Compare-And-Swap Instructions)",
225	261	.dependencies = featureSet(&[_]Feature{}),
226	262	};
227		result[@intFromEnum(Feature.experimental_zfa)] = .{
228		.llvm_name = "experimental-zfa",
229		.description = "'Zfa' (Additional Floating-Point)",
	263	result[@intFromEnum(Feature.experimental_zcmop)] = .{
	264	.llvm_name = "experimental-zcmop",
	265	.description = "'Zcmop' (Compressed May-Be-Operations)",
230	266	.dependencies = featureSet(&[_]Feature{
231		.f,
	267	.zca,
232	268	}),
233	269	};
234	270	result[@intFromEnum(Feature.experimental_zfbfmin)] = .{
...	...	@@ -238,14 +274,22 @@ pub const all_features = blk: {
238	274	.f,
239	275	}),
240	276	};
241		result[@intFromEnum(Feature.experimental_zicond)] = .{
242		.llvm_name = "experimental-zicond",
243		.description = "'Zicond' (Integer Conditional Operations)",
	277	result[@intFromEnum(Feature.experimental_zicfilp)] = .{
	278	.llvm_name = "experimental-zicfilp",
	279	.description = "'Zicfilp' (Landing pad)",
244	280	.dependencies = featureSet(&[_]Feature{}),
245	281	};
246		result[@intFromEnum(Feature.experimental_zihintntl)] = .{
247		.llvm_name = "experimental-zihintntl",
248		.description = "'Zihintntl' (Non-Temporal Locality Hints)",
	282	result[@intFromEnum(Feature.experimental_zicfiss)] = .{
	283	.llvm_name = "experimental-zicfiss",
	284	.description = "'Zicfiss' (Shadow stack)",
	285	.dependencies = featureSet(&[_]Feature{
	286	.experimental_zimop,
	287	.zicsr,
	288	}),
	289	};
	290	result[@intFromEnum(Feature.experimental_zimop)] = .{
	291	.llvm_name = "experimental-zimop",
	292	.description = "'Zimop' (May-Be-Operations)",
249	293	.dependencies = featureSet(&[_]Feature{}),
250	294	};
251	295	result[@intFromEnum(Feature.experimental_ztso)] = .{
...	...	@@ -253,16 +297,6 @@ pub const all_features = blk: {
253	297	.description = "'Ztso' (Memory Model - Total Store Order)",
254	298	.dependencies = featureSet(&[_]Feature{}),
255	299	};
256		result[@intFromEnum(Feature.experimental_zvbb)] = .{
257		.llvm_name = "experimental-zvbb",
258		.description = "'Zvbb' (Vector Bit-manipulation used in Cryptography)",
259		.dependencies = featureSet(&[_]Feature{}),
260		};
261		result[@intFromEnum(Feature.experimental_zvbc)] = .{
262		.llvm_name = "experimental-zvbc",
263		.description = "'Zvbc' (Vector Carryless Multiplication)",
264		.dependencies = featureSet(&[_]Feature{}),
265		};
266	300	result[@intFromEnum(Feature.experimental_zvfbfmin)] = .{
267	301	.llvm_name = "experimental-zvfbfmin",
268	302	.description = "'Zvbfmin' (Vector BF16 Converts)",
...	...	@@ -274,76 +308,10 @@ pub const all_features = blk: {
274	308	.llvm_name = "experimental-zvfbfwma",
275	309	.description = "'Zvfbfwma' (Vector BF16 widening mul-add)",
276	310	.dependencies = featureSet(&[_]Feature{
277		.zve32f,
	311	.experimental_zfbfmin,
	312	.experimental_zvfbfmin,
278	313	}),
279	314	};
280		result[@intFromEnum(Feature.experimental_zvkg)] = .{
281		.llvm_name = "experimental-zvkg",
282		.description = "'Zvkg' (Vector GCM instructions for Cryptography)",
283		.dependencies = featureSet(&[_]Feature{}),
284		};
285		result[@intFromEnum(Feature.experimental_zvkn)] = .{
286		.llvm_name = "experimental-zvkn",
287		.description = "This extension is shorthand for the following set of other extensions: Zvkned, Zvknhb, Zvbb, Zvbc, and Zvkt.",
288		.dependencies = featureSet(&[_]Feature{}),
289		};
290		result[@intFromEnum(Feature.experimental_zvknc)] = .{
291		.llvm_name = "experimental-zvknc",
292		.description = "This extension is shorthand for the following set of other extensions: Zvkn and Zvbc.",
293		.dependencies = featureSet(&[_]Feature{}),
294		};
295		result[@intFromEnum(Feature.experimental_zvkned)] = .{
296		.llvm_name = "experimental-zvkned",
297		.description = "'Zvkned' (Vector AES Encryption & Decryption (Single Round))",
298		.dependencies = featureSet(&[_]Feature{}),
299		};
300		result[@intFromEnum(Feature.experimental_zvkng)] = .{
301		.llvm_name = "experimental-zvkng",
302		.description = "This extension is shorthand for the following set of other extensions: Zvkn and Zvkg.",
303		.dependencies = featureSet(&[_]Feature{}),
304		};
305		result[@intFromEnum(Feature.experimental_zvknha)] = .{
306		.llvm_name = "experimental-zvknha",
307		.description = "'Zvknha' (Vector SHA-2 (SHA-256 only))",
308		.dependencies = featureSet(&[_]Feature{}),
309		};
310		result[@intFromEnum(Feature.experimental_zvknhb)] = .{
311		.llvm_name = "experimental-zvknhb",
312		.description = "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))",
313		.dependencies = featureSet(&[_]Feature{
314		.experimental_zvknha,
315		}),
316		};
317		result[@intFromEnum(Feature.experimental_zvks)] = .{
318		.llvm_name = "experimental-zvks",
319		.description = "This extension is shorthand for the following set of other extensions: Zvksed, Zvksh, Zvbb, Zvbc, and Zvkt.",
320		.dependencies = featureSet(&[_]Feature{}),
321		};
322		result[@intFromEnum(Feature.experimental_zvksc)] = .{
323		.llvm_name = "experimental-zvksc",
324		.description = "This extension is shorthand for the following set of other extensions: Zvks and Zvbc.",
325		.dependencies = featureSet(&[_]Feature{}),
326		};
327		result[@intFromEnum(Feature.experimental_zvksed)] = .{
328		.llvm_name = "experimental-zvksed",
329		.description = "'Zvksed' (SM4 Block Cipher Instructions)",
330		.dependencies = featureSet(&[_]Feature{}),
331		};
332		result[@intFromEnum(Feature.experimental_zvksg)] = .{
333		.llvm_name = "experimental-zvksg",
334		.description = "This extension is shorthand for the following set of other extensions: Zvks and Zvkg.",
335		.dependencies = featureSet(&[_]Feature{}),
336		};
337		result[@intFromEnum(Feature.experimental_zvksh)] = .{
338		.llvm_name = "experimental-zvksh",
339		.description = "'Zvksh' (SM3 Hash Function Instructions)",
340		.dependencies = featureSet(&[_]Feature{}),
341		};
342		result[@intFromEnum(Feature.experimental_zvkt)] = .{
343		.llvm_name = "experimental-zvkt",
344		.description = "'Zvkt' (Vector Data-Independent Execution Latency)",
345		.dependencies = featureSet(&[_]Feature{}),
346		};
347	315	result[@intFromEnum(Feature.f)] = .{
348	316	.llvm_name = "f",
349	317	.description = "'F' (Single-Precision Floating-Point)",
...	...	@@ -351,6 +319,11 @@ pub const all_features = blk: {
351	319	.zicsr,
352	320	}),
353	321	};
	322	result[@intFromEnum(Feature.fast_unaligned_access)] = .{
	323	.llvm_name = "fast-unaligned-access",
	324	.description = "Has reasonably performant unaligned loads and stores (both scalar and vector)",
	325	.dependencies = featureSet(&[_]Feature{}),
	326	};
354	327	result[@intFromEnum(Feature.forced_atomics)] = .{
355	328	.llvm_name = "forced-atomics",
356	329	.description = "Assume that lock-free native-width atomics are available",
...	...	@@ -361,9 +334,19 @@ pub const all_features = blk: {
361	334	.description = "'H' (Hypervisor)",
362	335	.dependencies = featureSet(&[_]Feature{}),
363	336	};
	337	result[@intFromEnum(Feature.i)] = .{
	338	.llvm_name = "i",
	339	.description = "'I' (Base Integer Instruction Set)",
	340	.dependencies = featureSet(&[_]Feature{}),
	341	};
	342	result[@intFromEnum(Feature.ld_add_fusion)] = .{
	343	.llvm_name = "ld-add-fusion",
	344	.description = "Enable LD+ADD macrofusion",
	345	.dependencies = featureSet(&[_]Feature{}),
	346	};
364	347	result[@intFromEnum(Feature.lui_addi_fusion)] = .{
365	348	.llvm_name = "lui-addi-fusion",
366		.description = "Enable LUI+ADDI macrofusion",
	349	.description = "Enable LUI+ADDI macro fusion",
367	350	.dependencies = featureSet(&[_]Feature{}),
368	351	};
369	352	result[@intFromEnum(Feature.m)] = .{
...	...	@@ -556,11 +539,31 @@ pub const all_features = blk: {
556	539	.description = "Enable trailing fence for seq-cst store.",
557	540	.dependencies = featureSet(&[_]Feature{}),
558	541	};
	542	result[@intFromEnum(Feature.shifted_zextw_fusion)] = .{
	543	.llvm_name = "shifted-zextw-fusion",
	544	.description = "Enable SLLI+SRLI to be fused when computing (shifted) word zero extension",
	545	.dependencies = featureSet(&[_]Feature{}),
	546	};
559	547	result[@intFromEnum(Feature.short_forward_branch_opt)] = .{
560	548	.llvm_name = "short-forward-branch-opt",
561	549	.description = "Enable short forward branch optimization",
562	550	.dependencies = featureSet(&[_]Feature{}),
563	551	};
	552	result[@intFromEnum(Feature.smaia)] = .{
	553	.llvm_name = "smaia",
	554	.description = "'Smaia' (Advanced Interrupt Architecture Machine Level)",
	555	.dependencies = featureSet(&[_]Feature{}),
	556	};
	557	result[@intFromEnum(Feature.smepmp)] = .{
	558	.llvm_name = "smepmp",
	559	.description = "'Smepmp' (Enhanced Physical Memory Protection)",
	560	.dependencies = featureSet(&[_]Feature{}),
	561	};
	562	result[@intFromEnum(Feature.ssaia)] = .{
	563	.llvm_name = "ssaia",
	564	.description = "'Ssaia' (Advanced Interrupt Architecture Supervisor Level)",
	565	.dependencies = featureSet(&[_]Feature{}),
	566	};
564	567	result[@intFromEnum(Feature.svinval)] = .{
565	568	.llvm_name = "svinval",
566	569	.description = "'Svinval' (Fine-Grained Address-Translation Cache Invalidation)",
...	...	@@ -581,14 +584,9 @@ pub const all_features = blk: {
581	584	.description = "Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits",
582	585	.dependencies = featureSet(&[_]Feature{}),
583	586	};
584		result[@intFromEnum(Feature.unaligned_scalar_mem)] = .{
585		.llvm_name = "unaligned-scalar-mem",
586		.description = "Has reasonably performant unaligned scalar loads and stores",
587		.dependencies = featureSet(&[_]Feature{}),
588		};
589		result[@intFromEnum(Feature.unaligned_vector_mem)] = .{
590		.llvm_name = "unaligned-vector-mem",
591		.description = "Has reasonably performant unaligned vector loads and stores",
	587	result[@intFromEnum(Feature.use_postra_scheduler)] = .{
	588	.llvm_name = "use-postra-scheduler",
	589	.description = "Schedule again after register allocation",
592	590	.dependencies = featureSet(&[_]Feature{}),
593	591	};
594	592	result[@intFromEnum(Feature.v)] = .{
...	...	@@ -599,19 +597,44 @@ pub const all_features = blk: {
599	597	.zvl128b,
600	598	}),
601	599	};
	600	result[@intFromEnum(Feature.ventana_veyron)] = .{
	601	.llvm_name = "ventana-veyron",
	602	.description = "Ventana Veyron-Series processors",
	603	.dependencies = featureSet(&[_]Feature{}),
	604	};
	605	result[@intFromEnum(Feature.xcvalu)] = .{
	606	.llvm_name = "xcvalu",
	607	.description = "'XCValu' (CORE-V ALU Operations)",
	608	.dependencies = featureSet(&[_]Feature{}),
	609	};
	610	result[@intFromEnum(Feature.xcvbi)] = .{
	611	.llvm_name = "xcvbi",
	612	.description = "'XCVbi' (CORE-V Immediate Branching)",
	613	.dependencies = featureSet(&[_]Feature{}),
	614	};
602	615	result[@intFromEnum(Feature.xcvbitmanip)] = .{
603	616	.llvm_name = "xcvbitmanip",
604	617	.description = "'XCVbitmanip' (CORE-V Bit Manipulation)",
605	618	.dependencies = featureSet(&[_]Feature{}),
606	619	};
	620	result[@intFromEnum(Feature.xcvelw)] = .{
	621	.llvm_name = "xcvelw",
	622	.description = "'XCVelw' (CORE-V Event Load Word)",
	623	.dependencies = featureSet(&[_]Feature{}),
	624	};
607	625	result[@intFromEnum(Feature.xcvmac)] = .{
608	626	.llvm_name = "xcvmac",
609	627	.description = "'XCVmac' (CORE-V Multiply-Accumulate)",
610	628	.dependencies = featureSet(&[_]Feature{}),
611	629	};
612		result[@intFromEnum(Feature.xsfcie)] = .{
613		.llvm_name = "xsfcie",
614		.description = "'XSfcie' (SiFive Custom Instruction Extension SCIE.)",
	630	result[@intFromEnum(Feature.xcvmem)] = .{
	631	.llvm_name = "xcvmem",
	632	.description = "'XCVmem' (CORE-V Post-incrementing Load & Store)",
	633	.dependencies = featureSet(&[_]Feature{}),
	634	};
	635	result[@intFromEnum(Feature.xcvsimd)] = .{
	636	.llvm_name = "xcvsimd",
	637	.description = "'XCVsimd' (CORE-V SIMD ALU)",
615	638	.dependencies = featureSet(&[_]Feature{}),
616	639	};
617	640	result[@intFromEnum(Feature.xsfvcp)] = .{
...	...	@@ -621,6 +644,34 @@ pub const all_features = blk: {
621	644	.zve32x,
622	645	}),
623	646	};
	647	result[@intFromEnum(Feature.xsfvfnrclipxfqf)] = .{
	648	.llvm_name = "xsfvfnrclipxfqf",
	649	.description = "'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)",
	650	.dependencies = featureSet(&[_]Feature{
	651	.zve32f,
	652	}),
	653	};
	654	result[@intFromEnum(Feature.xsfvfwmaccqqq)] = .{
	655	.llvm_name = "xsfvfwmaccqqq",
	656	.description = "'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction and 4-by-4))",
	657	.dependencies = featureSet(&[_]Feature{
	658	.experimental_zvfbfmin,
	659	}),
	660	};
	661	result[@intFromEnum(Feature.xsfvqmaccdod)] = .{
	662	.llvm_name = "xsfvqmaccdod",
	663	.description = "'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2))",
	664	.dependencies = featureSet(&[_]Feature{
	665	.zve32x,
	666	}),
	667	};
	668	result[@intFromEnum(Feature.xsfvqmaccqoq)] = .{
	669	.llvm_name = "xsfvqmaccqoq",
	670	.description = "'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4))",
	671	.dependencies = featureSet(&[_]Feature{
	672	.zve32x,
	673	}),
	674	};
624	675	result[@intFromEnum(Feature.xtheadba)] = .{
625	676	.llvm_name = "xtheadba",
626	677	.description = "'xtheadba' (T-Head address calculation instructions)",
...	...	@@ -685,6 +736,16 @@ pub const all_features = blk: {
685	736	.description = "'XVentanaCondOps' (Ventana Conditional Ops)",
686	737	.dependencies = featureSet(&[_]Feature{}),
687	738	};
	739	result[@intFromEnum(Feature.za128rs)] = .{
	740	.llvm_name = "za128rs",
	741	.description = "'Za128rs' (Reservation Set Size of at Most 128 Bytes)",
	742	.dependencies = featureSet(&[_]Feature{}),
	743	};
	744	result[@intFromEnum(Feature.za64rs)] = .{
	745	.llvm_name = "za64rs",
	746	.description = "'Za64rs' (Reservation Set Size of at Most 64 Bytes)",
	747	.dependencies = featureSet(&[_]Feature{}),
	748	};
688	749	result[@intFromEnum(Feature.zawrs)] = .{
689	750	.llvm_name = "zawrs",
690	751	.description = "'Zawrs' (Wait on Reservation Set)",
...	...	@@ -782,11 +843,28 @@ pub const all_features = blk: {
782	843	.zfinx,
783	844	}),
784	845	};
	846	result[@intFromEnum(Feature.zexth_fusion)] = .{
	847	.llvm_name = "zexth-fusion",
	848	.description = "Enable SLLI+SRLI to be fused to zero extension of halfword",
	849	.dependencies = featureSet(&[_]Feature{}),
	850	};
	851	result[@intFromEnum(Feature.zextw_fusion)] = .{
	852	.llvm_name = "zextw-fusion",
	853	.description = "Enable SLLI+SRLI to be fused to zero extension of word",
	854	.dependencies = featureSet(&[_]Feature{}),
	855	};
	856	result[@intFromEnum(Feature.zfa)] = .{
	857	.llvm_name = "zfa",
	858	.description = "'Zfa' (Additional Floating-Point)",
	859	.dependencies = featureSet(&[_]Feature{
	860	.f,
	861	}),
	862	};
785	863	result[@intFromEnum(Feature.zfh)] = .{
786	864	.llvm_name = "zfh",
787	865	.description = "'Zfh' (Half-Precision Floating-Point)",
788	866	.dependencies = featureSet(&[_]Feature{
789		.f,
	867	.zfhmin,
790	868	}),
791	869	};
792	870	result[@intFromEnum(Feature.zfhmin)] = .{
...	...	@@ -807,7 +885,7 @@ pub const all_features = blk: {
807	885	.llvm_name = "zhinx",
808	886	.description = "'Zhinx' (Half Float in Integer)",
809	887	.dependencies = featureSet(&[_]Feature{
810		.zfinx,
	888	.zhinxmin,
811	889	}),
812	890	};
813	891	result[@intFromEnum(Feature.zhinxmin)] = .{
...	...	@@ -817,6 +895,11 @@ pub const all_features = blk: {
817	895	.zfinx,
818	896	}),
819	897	};
	898	result[@intFromEnum(Feature.zic64b)] = .{
	899	.llvm_name = "zic64b",
	900	.description = "'Zic64b' (Cache Block Size Is 64 Bytes)",
	901	.dependencies = featureSet(&[_]Feature{}),
	902	};
820	903	result[@intFromEnum(Feature.zicbom)] = .{
821	904	.llvm_name = "zicbom",
822	905	.description = "'Zicbom' (Cache-Block Management Instructions)",
...	...	@@ -832,6 +915,26 @@ pub const all_features = blk: {
832	915	.description = "'Zicboz' (Cache-Block Zero Instructions)",
833	916	.dependencies = featureSet(&[_]Feature{}),
834	917	};
	918	result[@intFromEnum(Feature.ziccamoa)] = .{
	919	.llvm_name = "ziccamoa",
	920	.description = "'Ziccamoa' (Main Memory Supports All Atomics in A)",
	921	.dependencies = featureSet(&[_]Feature{}),
	922	};
	923	result[@intFromEnum(Feature.ziccif)] = .{
	924	.llvm_name = "ziccif",
	925	.description = "'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement)",
	926	.dependencies = featureSet(&[_]Feature{}),
	927	};
	928	result[@intFromEnum(Feature.zicclsm)] = .{
	929	.llvm_name = "zicclsm",
	930	.description = "'Zicclsm' (Main Memory Supports Misaligned Loads/Stores)",
	931	.dependencies = featureSet(&[_]Feature{}),
	932	};
	933	result[@intFromEnum(Feature.ziccrse)] = .{
	934	.llvm_name = "ziccrse",
	935	.description = "'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences)",
	936	.dependencies = featureSet(&[_]Feature{}),
	937	};
835	938	result[@intFromEnum(Feature.zicntr)] = .{
836	939	.llvm_name = "zicntr",
837	940	.description = "'Zicntr' (Base Counters and Timers)",
...	...	@@ -839,6 +942,11 @@ pub const all_features = blk: {
839	942	.zicsr,
840	943	}),
841	944	};
	945	result[@intFromEnum(Feature.zicond)] = .{
	946	.llvm_name = "zicond",
	947	.description = "'Zicond' (Integer Conditional Operations)",
	948	.dependencies = featureSet(&[_]Feature{}),
	949	};
842	950	result[@intFromEnum(Feature.zicsr)] = .{
843	951	.llvm_name = "zicsr",
844	952	.description = "'zicsr' (CSRs)",
...	...	@@ -849,6 +957,11 @@ pub const all_features = blk: {
849	957	.description = "'Zifencei' (fence.i)",
850	958	.dependencies = featureSet(&[_]Feature{}),
851	959	};
	960	result[@intFromEnum(Feature.zihintntl)] = .{
	961	.llvm_name = "zihintntl",
	962	.description = "'Zihintntl' (Non-Temporal Locality Hints)",
	963	.dependencies = featureSet(&[_]Feature{}),
	964	};
852	965	result[@intFromEnum(Feature.zihintpause)] = .{
853	966	.llvm_name = "zihintpause",
854	967	.description = "'Zihintpause' (Pause Hint)",
...	...	@@ -933,6 +1046,18 @@ pub const all_features = blk: {
933	1046	.description = "'Zmmul' (Integer Multiplication)",
934	1047	.dependencies = featureSet(&[_]Feature{}),
935	1048	};
	1049	result[@intFromEnum(Feature.zvbb)] = .{
	1050	.llvm_name = "zvbb",
	1051	.description = "'Zvbb' (Vector basic bit-manipulation instructions)",
	1052	.dependencies = featureSet(&[_]Feature{
	1053	.zvkb,
	1054	}),
	1055	};
	1056	result[@intFromEnum(Feature.zvbc)] = .{
	1057	.llvm_name = "zvbc",
	1058	.description = "'Zvbc' (Vector Carryless Multiplication)",
	1059	.dependencies = featureSet(&[_]Feature{}),
	1060	};
936	1061	result[@intFromEnum(Feature.zve32f)] = .{
937	1062	.llvm_name = "zve32f",
938	1063	.description = "'Zve32f' (Vector Extensions for Embedded Processors with maximal 32 EEW and F extension)",
...	...	@@ -978,9 +1103,110 @@ pub const all_features = blk: {
978	1103	.description = "'Zvfh' (Vector Half-Precision Floating-Point)",
979	1104	.dependencies = featureSet(&[_]Feature{
980	1105	.zfhmin,
	1106	.zvfhmin,
	1107	}),
	1108	};
	1109	result[@intFromEnum(Feature.zvfhmin)] = .{
	1110	.llvm_name = "zvfhmin",
	1111	.description = "'Zvfhmin' (Vector Half-Precision Floating-Point Minimal)",
	1112	.dependencies = featureSet(&[_]Feature{
981	1113	.zve32f,
982	1114	}),
983	1115	};
	1116	result[@intFromEnum(Feature.zvkb)] = .{
	1117	.llvm_name = "zvkb",
	1118	.description = "'Zvkb' (Vector Bit-manipulation used in Cryptography)",
	1119	.dependencies = featureSet(&[_]Feature{}),
	1120	};
	1121	result[@intFromEnum(Feature.zvkg)] = .{
	1122	.llvm_name = "zvkg",
	1123	.description = "'Zvkg' (Vector GCM instructions for Cryptography)",
	1124	.dependencies = featureSet(&[_]Feature{}),
	1125	};
	1126	result[@intFromEnum(Feature.zvkn)] = .{
	1127	.llvm_name = "zvkn",
	1128	.description = "'Zvkn' (shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and 'Zvkt')",
	1129	.dependencies = featureSet(&[_]Feature{
	1130	.zvkb,
	1131	.zvkned,
	1132	.zvknhb,
	1133	.zvkt,
	1134	}),
	1135	};
	1136	result[@intFromEnum(Feature.zvknc)] = .{
	1137	.llvm_name = "zvknc",
	1138	.description = "'Zvknc' (shorthand for 'Zvknc' and 'Zvbc')",
	1139	.dependencies = featureSet(&[_]Feature{
	1140	.zvbc,
	1141	.zvkn,
	1142	}),
	1143	};
	1144	result[@intFromEnum(Feature.zvkned)] = .{
	1145	.llvm_name = "zvkned",
	1146	.description = "'Zvkned' (Vector AES Encryption & Decryption (Single Round))",
	1147	.dependencies = featureSet(&[_]Feature{}),
	1148	};
	1149	result[@intFromEnum(Feature.zvkng)] = .{
	1150	.llvm_name = "zvkng",
	1151	.description = "'zvkng' (shorthand for 'Zvkn' and 'Zvkg')",
	1152	.dependencies = featureSet(&[_]Feature{
	1153	.zvkg,
	1154	.zvkn,
	1155	}),
	1156	};
	1157	result[@intFromEnum(Feature.zvknha)] = .{
	1158	.llvm_name = "zvknha",
	1159	.description = "'Zvknha' (Vector SHA-2 (SHA-256 only))",
	1160	.dependencies = featureSet(&[_]Feature{}),
	1161	};
	1162	result[@intFromEnum(Feature.zvknhb)] = .{
	1163	.llvm_name = "zvknhb",
	1164	.description = "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))",
	1165	.dependencies = featureSet(&[_]Feature{
	1166	.zve64x,
	1167	}),
	1168	};
	1169	result[@intFromEnum(Feature.zvks)] = .{
	1170	.llvm_name = "zvks",
	1171	.description = "'Zvks' (shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and 'Zvkt')",
	1172	.dependencies = featureSet(&[_]Feature{
	1173	.zvkb,
	1174	.zvksed,
	1175	.zvksh,
	1176	.zvkt,
	1177	}),
	1178	};
	1179	result[@intFromEnum(Feature.zvksc)] = .{
	1180	.llvm_name = "zvksc",
	1181	.description = "'Zvksc' (shorthand for 'Zvks' and 'Zvbc')",
	1182	.dependencies = featureSet(&[_]Feature{
	1183	.zvbc,
	1184	.zvks,
	1185	}),
	1186	};
	1187	result[@intFromEnum(Feature.zvksed)] = .{
	1188	.llvm_name = "zvksed",
	1189	.description = "'Zvksed' (SM4 Block Cipher Instructions)",
	1190	.dependencies = featureSet(&[_]Feature{}),
	1191	};
	1192	result[@intFromEnum(Feature.zvksg)] = .{
	1193	.llvm_name = "zvksg",
	1194	.description = "'Zvksg' (shorthand for 'Zvks' and 'Zvkg')",
	1195	.dependencies = featureSet(&[_]Feature{
	1196	.zvkg,
	1197	.zvks,
	1198	}),
	1199	};
	1200	result[@intFromEnum(Feature.zvksh)] = .{
	1201	.llvm_name = "zvksh",
	1202	.description = "'Zvksh' (SM3 Hash Function Instructions)",
	1203	.dependencies = featureSet(&[_]Feature{}),
	1204	};
	1205	result[@intFromEnum(Feature.zvkt)] = .{
	1206	.llvm_name = "zvkt",
	1207	.description = "'Zvkt' (Vector Data-Independent Execution Latency)",
	1208	.dependencies = featureSet(&[_]Feature{}),
	1209	};
984	1210	result[@intFromEnum(Feature.zvl1024b)] = .{
985	1211	.llvm_name = "zvl1024b",
986	1212	.description = "'Zvl' (Minimum Vector Length) 1024",
...	...	@@ -1217,6 +1443,77 @@ pub const cpu = struct {
1217	1443	.zifencei,
1218	1444	}),
1219	1445	};
	1446	pub const sifive_p450 = CpuModel{
	1447	.name = "sifive_p450",
	1448	.llvm_name = "sifive-p450",
	1449	.features = featureSet(&[_]Feature{
	1450	.@"64bit",
	1451	.a,
	1452	.auipc_addi_fusion,
	1453	.c,
	1454	.conditional_cmv_fusion,
	1455	.d,
	1456	.fast_unaligned_access,
	1457	.lui_addi_fusion,
	1458	.m,
	1459	.no_default_unroll,
	1460	.za64rs,
	1461	.zba,
	1462	.zbb,
	1463	.zbs,
	1464	.zfhmin,
	1465	.zic64b,
	1466	.zicbom,
	1467	.zicbop,
	1468	.zicboz,
	1469	.ziccamoa,
	1470	.ziccif,
	1471	.zicclsm,
	1472	.ziccrse,
	1473	.zifencei,
	1474	.zihintntl,
	1475	.zihintpause,
	1476	.zihpm,
	1477	}),
	1478	};
	1479	pub const sifive_p670 = CpuModel{
	1480	.name = "sifive_p670",
	1481	.llvm_name = "sifive-p670",
	1482	.features = featureSet(&[_]Feature{
	1483	.@"64bit",
	1484	.a,
	1485	.auipc_addi_fusion,
	1486	.c,
	1487	.conditional_cmv_fusion,
	1488	.fast_unaligned_access,
	1489	.lui_addi_fusion,
	1490	.m,
	1491	.no_default_unroll,
	1492	.v,
	1493	.za64rs,
	1494	.zba,
	1495	.zbb,
	1496	.zbs,
	1497	.zfhmin,
	1498	.zic64b,
	1499	.zicbom,
	1500	.zicbop,
	1501	.zicboz,
	1502	.ziccamoa,
	1503	.ziccif,
	1504	.zicclsm,
	1505	.ziccrse,
	1506	.zifencei,
	1507	.zihintntl,
	1508	.zihintpause,
	1509	.zihpm,
	1510	.zvbb,
	1511	.zvknc,
	1512	.zvkng,
	1513	.zvksc,
	1514	.zvksg,
	1515	}),
	1516	};
1220	1517	pub const sifive_s21 = CpuModel{
1221	1518	.name = "sifive_s21",
1222	1519	.llvm_name = "sifive-s21",
...	...	@@ -1264,7 +1561,6 @@ pub const cpu = struct {
1264	1561	.m,
1265	1562	.no_default_unroll,
1266	1563	.short_forward_branch_opt,
1267		.xsfcie,
1268	1564	.zifencei,
1269	1565	.zihintpause,
1270	1566	}),
...	...	@@ -1338,4 +1634,56 @@ pub const cpu = struct {
1338	1634	.zifencei,
1339	1635	}),
1340	1636	};
	1637	pub const veyron_v1 = CpuModel{
	1638	.name = "veyron_v1",
	1639	.llvm_name = "veyron-v1",
	1640	.features = featureSet(&[_]Feature{
	1641	.@"64bit",
	1642	.a,
	1643	.auipc_addi_fusion,
	1644	.c,
	1645	.d,
	1646	.ld_add_fusion,
	1647	.lui_addi_fusion,
	1648	.m,
	1649	.shifted_zextw_fusion,
	1650	.ventana_veyron,
	1651	.xventanacondops,
	1652	.zba,
	1653	.zbb,
	1654	.zbc,
	1655	.zbs,
	1656	.zexth_fusion,
	1657	.zextw_fusion,
	1658	.zicbom,
	1659	.zicbop,
	1660	.zicboz,
	1661	.zicntr,
	1662	.zifencei,
	1663	.zihintpause,
	1664	.zihpm,
	1665	}),
	1666	};
	1667	pub const xiangshan_nanhu = CpuModel{
	1668	.name = "xiangshan_nanhu",
	1669	.llvm_name = "xiangshan-nanhu",
	1670	.features = featureSet(&[_]Feature{
	1671	.@"64bit",
	1672	.a,
	1673	.c,
	1674	.d,
	1675	.m,
	1676	.svinval,
	1677	.zba,
	1678	.zbb,
	1679	.zbc,
	1680	.zbs,
	1681	.zicbom,
	1682	.zicboz,
	1683	.zifencei,
	1684	.zkn,
	1685	.zksed,
	1686	.zksh,
	1687	}),
	1688	};
1341	1689	};

lib/std/Target/s390x.zig+6

...	...	@@ -5,6 +5,7 @@ const CpuFeature = std.Target.Cpu.Feature;
5	5	const CpuModel = std.Target.Cpu.Model;
6	6
7	7	pub const Feature = enum {
	8	backchain,
8	9	bear_enhancement,
9	10	deflate_conversion,
10	11	dfp_packed_conversion,
...	...	@@ -57,6 +58,11 @@ pub const all_features = blk: {
57	58	const len = @typeInfo(Feature).Enum.fields.len;
58	59	std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
59	60	var result: [len]CpuFeature = undefined;
	61	result[@intFromEnum(Feature.backchain)] = .{
	62	.llvm_name = "backchain",
	63	.description = "Store the address of the caller's frame into the callee's stack frame",
	64	.dependencies = featureSet(&[_]Feature{}),
	65	};
60	66	result[@intFromEnum(Feature.bear_enhancement)] = .{
61	67	.llvm_name = "bear-enhancement",
62	68	.description = "Assume that the BEAR-enhancement facility is installed",

lib/std/Target/sparc.zig+172-2

...	...	@@ -18,6 +18,34 @@ pub const Feature = enum {
18	18	no_fmuls,
19	19	no_fsmuld,
20	20	popc,
	21	reserve_g1,
	22	reserve_g2,
	23	reserve_g3,
	24	reserve_g4,
	25	reserve_g5,
	26	reserve_g6,
	27	reserve_g7,
	28	reserve_i0,
	29	reserve_i1,
	30	reserve_i2,
	31	reserve_i3,
	32	reserve_i4,
	33	reserve_i5,
	34	reserve_l0,
	35	reserve_l1,
	36	reserve_l2,
	37	reserve_l3,
	38	reserve_l4,
	39	reserve_l5,
	40	reserve_l6,
	41	reserve_l7,
	42	reserve_o0,
	43	reserve_o1,
	44	reserve_o2,
	45	reserve_o3,
	46	reserve_o4,
	47	reserve_o5,
	48	slow_rdpc,
21	49	soft_float,
22	50	soft_mul_div,
23	51	v9,
...	...	@@ -100,6 +128,148 @@ pub const all_features = blk: {
100	128	.description = "Use the popc (population count) instruction",
101	129	.dependencies = featureSet(&[_]Feature{}),
102	130	};
	131	result[@intFromEnum(Feature.reserve_g1)] = .{
	132	.llvm_name = "reserve-g1",
	133	.description = "Reserve G1, making it unavailable as a GPR",
	134	.dependencies = featureSet(&[_]Feature{}),
	135	};
	136	result[@intFromEnum(Feature.reserve_g2)] = .{
	137	.llvm_name = "reserve-g2",
	138	.description = "Reserve G2, making it unavailable as a GPR",
	139	.dependencies = featureSet(&[_]Feature{}),
	140	};
	141	result[@intFromEnum(Feature.reserve_g3)] = .{
	142	.llvm_name = "reserve-g3",
	143	.description = "Reserve G3, making it unavailable as a GPR",
	144	.dependencies = featureSet(&[_]Feature{}),
	145	};
	146	result[@intFromEnum(Feature.reserve_g4)] = .{
	147	.llvm_name = "reserve-g4",
	148	.description = "Reserve G4, making it unavailable as a GPR",
	149	.dependencies = featureSet(&[_]Feature{}),
	150	};
	151	result[@intFromEnum(Feature.reserve_g5)] = .{
	152	.llvm_name = "reserve-g5",
	153	.description = "Reserve G5, making it unavailable as a GPR",
	154	.dependencies = featureSet(&[_]Feature{}),
	155	};
	156	result[@intFromEnum(Feature.reserve_g6)] = .{
	157	.llvm_name = "reserve-g6",
	158	.description = "Reserve G6, making it unavailable as a GPR",
	159	.dependencies = featureSet(&[_]Feature{}),
	160	};
	161	result[@intFromEnum(Feature.reserve_g7)] = .{
	162	.llvm_name = "reserve-g7",
	163	.description = "Reserve G7, making it unavailable as a GPR",
	164	.dependencies = featureSet(&[_]Feature{}),
	165	};
	166	result[@intFromEnum(Feature.reserve_i0)] = .{
	167	.llvm_name = "reserve-i0",
	168	.description = "Reserve I0, making it unavailable as a GPR",
	169	.dependencies = featureSet(&[_]Feature{}),
	170	};
	171	result[@intFromEnum(Feature.reserve_i1)] = .{
	172	.llvm_name = "reserve-i1",
	173	.description = "Reserve I1, making it unavailable as a GPR",
	174	.dependencies = featureSet(&[_]Feature{}),
	175	};
	176	result[@intFromEnum(Feature.reserve_i2)] = .{
	177	.llvm_name = "reserve-i2",
	178	.description = "Reserve I2, making it unavailable as a GPR",
	179	.dependencies = featureSet(&[_]Feature{}),
	180	};
	181	result[@intFromEnum(Feature.reserve_i3)] = .{
	182	.llvm_name = "reserve-i3",
	183	.description = "Reserve I3, making it unavailable as a GPR",
	184	.dependencies = featureSet(&[_]Feature{}),
	185	};
	186	result[@intFromEnum(Feature.reserve_i4)] = .{
	187	.llvm_name = "reserve-i4",
	188	.description = "Reserve I4, making it unavailable as a GPR",
	189	.dependencies = featureSet(&[_]Feature{}),
	190	};
	191	result[@intFromEnum(Feature.reserve_i5)] = .{
	192	.llvm_name = "reserve-i5",
	193	.description = "Reserve I5, making it unavailable as a GPR",
	194	.dependencies = featureSet(&[_]Feature{}),
	195	};
	196	result[@intFromEnum(Feature.reserve_l0)] = .{
	197	.llvm_name = "reserve-l0",
	198	.description = "Reserve L0, making it unavailable as a GPR",
	199	.dependencies = featureSet(&[_]Feature{}),
	200	};
	201	result[@intFromEnum(Feature.reserve_l1)] = .{
	202	.llvm_name = "reserve-l1",
	203	.description = "Reserve L1, making it unavailable as a GPR",
	204	.dependencies = featureSet(&[_]Feature{}),
	205	};
	206	result[@intFromEnum(Feature.reserve_l2)] = .{
	207	.llvm_name = "reserve-l2",
	208	.description = "Reserve L2, making it unavailable as a GPR",
	209	.dependencies = featureSet(&[_]Feature{}),
	210	};
	211	result[@intFromEnum(Feature.reserve_l3)] = .{
	212	.llvm_name = "reserve-l3",
	213	.description = "Reserve L3, making it unavailable as a GPR",
	214	.dependencies = featureSet(&[_]Feature{}),
	215	};
	216	result[@intFromEnum(Feature.reserve_l4)] = .{
	217	.llvm_name = "reserve-l4",
	218	.description = "Reserve L4, making it unavailable as a GPR",
	219	.dependencies = featureSet(&[_]Feature{}),
	220	};
	221	result[@intFromEnum(Feature.reserve_l5)] = .{
	222	.llvm_name = "reserve-l5",
	223	.description = "Reserve L5, making it unavailable as a GPR",
	224	.dependencies = featureSet(&[_]Feature{}),
	225	};
	226	result[@intFromEnum(Feature.reserve_l6)] = .{
	227	.llvm_name = "reserve-l6",
	228	.description = "Reserve L6, making it unavailable as a GPR",
	229	.dependencies = featureSet(&[_]Feature{}),
	230	};
	231	result[@intFromEnum(Feature.reserve_l7)] = .{
	232	.llvm_name = "reserve-l7",
	233	.description = "Reserve L7, making it unavailable as a GPR",
	234	.dependencies = featureSet(&[_]Feature{}),
	235	};
	236	result[@intFromEnum(Feature.reserve_o0)] = .{
	237	.llvm_name = "reserve-o0",
	238	.description = "Reserve O0, making it unavailable as a GPR",
	239	.dependencies = featureSet(&[_]Feature{}),
	240	};
	241	result[@intFromEnum(Feature.reserve_o1)] = .{
	242	.llvm_name = "reserve-o1",
	243	.description = "Reserve O1, making it unavailable as a GPR",
	244	.dependencies = featureSet(&[_]Feature{}),
	245	};
	246	result[@intFromEnum(Feature.reserve_o2)] = .{
	247	.llvm_name = "reserve-o2",
	248	.description = "Reserve O2, making it unavailable as a GPR",
	249	.dependencies = featureSet(&[_]Feature{}),
	250	};
	251	result[@intFromEnum(Feature.reserve_o3)] = .{
	252	.llvm_name = "reserve-o3",
	253	.description = "Reserve O3, making it unavailable as a GPR",
	254	.dependencies = featureSet(&[_]Feature{}),
	255	};
	256	result[@intFromEnum(Feature.reserve_o4)] = .{
	257	.llvm_name = "reserve-o4",
	258	.description = "Reserve O4, making it unavailable as a GPR",
	259	.dependencies = featureSet(&[_]Feature{}),
	260	};
	261	result[@intFromEnum(Feature.reserve_o5)] = .{
	262	.llvm_name = "reserve-o5",
	263	.description = "Reserve O5, making it unavailable as a GPR",
	264	.dependencies = featureSet(&[_]Feature{}),
	265	};
	266	result[@intFromEnum(Feature.slow_rdpc)] = .{
	267	.llvm_name = "slow-rdpc",
	268	.description = "rd %pc, %XX is slow",
	269	.dependencies = featureSet(&[_]Feature{
	270	.v9,
	271	}),
	272	};
103	273	result[@intFromEnum(Feature.soft_float)] = .{
104	274	.llvm_name = "soft-float",
105	275	.description = "Use software emulation for floating point",
...	...	@@ -407,7 +577,7 @@ pub const cpu = struct {
407	577	.llvm_name = "ultrasparc",
408	578	.features = featureSet(&[_]Feature{
409	579	.deprecated_v8,
410		.v9,
	580	.slow_rdpc,
411	581	.vis,
412	582	}),
413	583	};
...	...	@@ -416,7 +586,7 @@ pub const cpu = struct {
416	586	.llvm_name = "ultrasparc3",
417	587	.features = featureSet(&[_]Feature{
418	588	.deprecated_v8,
419		.v9,
	589	.slow_rdpc,
420	590	.vis,
421	591	.vis2,
422	592	}),

lib/std/Target/ve.zig+3-1

...	...	@@ -34,6 +34,8 @@ pub const cpu = struct {
34	34	pub const generic = CpuModel{
35	35	.name = "generic",
36	36	.llvm_name = "generic",
37		.features = featureSet(&[_]Feature{}),
	37	.features = featureSet(&[_]Feature{
	38	.vpu,
	39	}),
38	40	};
39	41	};

lib/std/Target/wasm.zig+6

...	...	@@ -9,6 +9,7 @@ pub const Feature = enum {
9	9	bulk_memory,
10	10	exception_handling,
11	11	extended_const,
	12	multimemory,
12	13	multivalue,
13	14	mutable_globals,
14	15	nontrapping_fptoint,
...	...	@@ -48,6 +49,11 @@ pub const all_features = blk: {
48	49	.description = "Enable extended const expressions",
49	50	.dependencies = featureSet(&[_]Feature{}),
50	51	};
	52	result[@intFromEnum(Feature.multimemory)] = .{
	53	.llvm_name = "multimemory",
	54	.description = "Enable multiple memories",
	55	.dependencies = featureSet(&[_]Feature{}),
	56	};
51	57	result[@intFromEnum(Feature.multivalue)] = .{
52	58	.llvm_name = "multivalue",
53	59	.description = "Enable multivalue blocks, instructions, and functions",

lib/std/Target/x86.zig+656-21

...	...	@@ -19,6 +19,8 @@ pub const Feature = enum {
19	19	amx_int8,
20	20	amx_tile,
21	21	avx,
	22	avx10_1_256,
	23	avx10_1_512,
22	24	avx2,
23	25	avx512bf16,
24	26	avx512bitalg,
...	...	@@ -44,6 +46,8 @@ pub const Feature = enum {
44	46	bmi,
45	47	bmi2,
46	48	branchfusion,
	49	ccmp,
	50	cf,
47	51	cldemote,
48	52	clflushopt,
49	53	clwb,
...	...	@@ -53,8 +57,10 @@ pub const Feature = enum {
53	57	crc32,
54	58	cx16,
55	59	cx8,
	60	egpr,
56	61	enqcmd,
57	62	ermsb,
	63	evex512,
58	64	f16c,
59	65	false_deps_getmant,
60	66	false_deps_lzcnt_tzcnt,
...	...	@@ -104,6 +110,7 @@ pub const Feature = enum {
104	110	movdir64b,
105	111	movdiri,
106	112	mwaitx,
	113	ndd,
107	114	no_bypass_delay,
108	115	no_bypass_delay_blend,
109	116	no_bypass_delay_mov,
...	...	@@ -114,14 +121,18 @@ pub const Feature = enum {
114	121	pconfig,
115	122	pku,
116	123	popcnt,
	124	ppx,
117	125	prefer_128_bit,
118	126	prefer_256_bit,
119	127	prefer_mask_registers,
120	128	prefer_movmsk_over_vtest,
	129	prefer_no_gather,
	130	prefer_no_scatter,
121	131	prefetchi,
122	132	prefetchwt1,
123	133	prfchw,
124	134	ptwrite,
	135	push2pop2,
125	136	raoint,
126	137	rdpid,
127	138	rdpru,
...	...	@@ -167,6 +178,7 @@ pub const Feature = enum {
167	178	uintr,
168	179	use_glm_div_sqrt_costs,
169	180	use_slm_arith_costs,
	181	usermsr,
170	182	vaes,
171	183	vpclmulqdq,
172	184	vzeroupper,
...	...	@@ -276,6 +288,31 @@ pub const all_features = blk: {
276	288	.sse4_2,
277	289	}),
278	290	};
	291	result[@intFromEnum(Feature.avx10_1_256)] = .{
	292	.llvm_name = "avx10.1-256",
	293	.description = "Support AVX10.1 up to 256-bit instruction",
	294	.dependencies = featureSet(&[_]Feature{
	295	.avx512bf16,
	296	.avx512bitalg,
	297	.avx512cd,
	298	.avx512fp16,
	299	.avx512ifma,
	300	.avx512vbmi,
	301	.avx512vbmi2,
	302	.avx512vnni,
	303	.avx512vpopcntdq,
	304	.vaes,
	305	.vpclmulqdq,
	306	}),
	307	};
	308	result[@intFromEnum(Feature.avx10_1_512)] = .{
	309	.llvm_name = "avx10.1-512",
	310	.description = "Support AVX10.1 up to 512-bit instruction",
	311	.dependencies = featureSet(&[_]Feature{
	312	.avx10_1_256,
	313	.evex512,
	314	}),
	315	};
279	316	result[@intFromEnum(Feature.avx2)] = .{
280	317	.llvm_name = "avx2",
281	318	.description = "Enable AVX2 instructions",
...	...	@@ -449,6 +486,16 @@ pub const all_features = blk: {
449	486	.description = "CMP/TEST can be fused with conditional branches",
450	487	.dependencies = featureSet(&[_]Feature{}),
451	488	};
	489	result[@intFromEnum(Feature.ccmp)] = .{
	490	.llvm_name = "ccmp",
	491	.description = "Support conditional cmp & test instructions",
	492	.dependencies = featureSet(&[_]Feature{}),
	493	};
	494	result[@intFromEnum(Feature.cf)] = .{
	495	.llvm_name = "cf",
	496	.description = "Support conditional faulting",
	497	.dependencies = featureSet(&[_]Feature{}),
	498	};
452	499	result[@intFromEnum(Feature.cldemote)] = .{
453	500	.llvm_name = "cldemote",
454	501	.description = "Enable Cache Line Demote",
...	...	@@ -496,6 +543,11 @@ pub const all_features = blk: {
496	543	.description = "Support CMPXCHG8B instructions",
497	544	.dependencies = featureSet(&[_]Feature{}),
498	545	};
	546	result[@intFromEnum(Feature.egpr)] = .{
	547	.llvm_name = "egpr",
	548	.description = "Support extended general purpose register",
	549	.dependencies = featureSet(&[_]Feature{}),
	550	};
499	551	result[@intFromEnum(Feature.enqcmd)] = .{
500	552	.llvm_name = "enqcmd",
501	553	.description = "Has ENQCMD instructions",
...	...	@@ -506,6 +558,11 @@ pub const all_features = blk: {
506	558	.description = "REP MOVS/STOS are fast",
507	559	.dependencies = featureSet(&[_]Feature{}),
508	560	};
	561	result[@intFromEnum(Feature.evex512)] = .{
	562	.llvm_name = "evex512",
	563	.description = "Support ZMM and 64-bit mask instructions",
	564	.dependencies = featureSet(&[_]Feature{}),
	565	};
509	566	result[@intFromEnum(Feature.f16c)] = .{
510	567	.llvm_name = "f16c",
511	568	.description = "Support 16-bit floating point conversion instructions",
...	...	@@ -762,6 +819,11 @@ pub const all_features = blk: {
762	819	.description = "Enable MONITORX/MWAITX timer functionality",
763	820	.dependencies = featureSet(&[_]Feature{}),
764	821	};
	822	result[@intFromEnum(Feature.ndd)] = .{
	823	.llvm_name = "ndd",
	824	.description = "Support non-destructive destination",
	825	.dependencies = featureSet(&[_]Feature{}),
	826	};
765	827	result[@intFromEnum(Feature.no_bypass_delay)] = .{
766	828	.llvm_name = "no-bypass-delay",
767	829	.description = "Has no bypass delay when using the 'wrong' domain",
...	...	@@ -814,6 +876,11 @@ pub const all_features = blk: {
814	876	.description = "Support POPCNT instruction",
815	877	.dependencies = featureSet(&[_]Feature{}),
816	878	};
	879	result[@intFromEnum(Feature.ppx)] = .{
	880	.llvm_name = "ppx",
	881	.description = "Support Push-Pop Acceleration",
	882	.dependencies = featureSet(&[_]Feature{}),
	883	};
817	884	result[@intFromEnum(Feature.prefer_128_bit)] = .{
818	885	.llvm_name = "prefer-128-bit",
819	886	.description = "Prefer 128-bit AVX instructions",
...	...	@@ -834,6 +901,16 @@ pub const all_features = blk: {
834	901	.description = "Prefer movmsk over vtest instruction",
835	902	.dependencies = featureSet(&[_]Feature{}),
836	903	};
	904	result[@intFromEnum(Feature.prefer_no_gather)] = .{
	905	.llvm_name = "prefer-no-gather",
	906	.description = "Prefer no gather instructions",
	907	.dependencies = featureSet(&[_]Feature{}),
	908	};
	909	result[@intFromEnum(Feature.prefer_no_scatter)] = .{
	910	.llvm_name = "prefer-no-scatter",
	911	.description = "Prefer no scatter instructions",
	912	.dependencies = featureSet(&[_]Feature{}),
	913	};
837	914	result[@intFromEnum(Feature.prefetchi)] = .{
838	915	.llvm_name = "prefetchi",
839	916	.description = "Prefetch instruction with T0 or T1 Hint",
...	...	@@ -854,6 +931,11 @@ pub const all_features = blk: {
854	931	.description = "Support ptwrite instruction",
855	932	.dependencies = featureSet(&[_]Feature{}),
856	933	};
	934	result[@intFromEnum(Feature.push2pop2)] = .{
	935	.llvm_name = "push2pop2",
	936	.description = "Support PUSH2/POP2 instructions",
	937	.dependencies = featureSet(&[_]Feature{}),
	938	};
857	939	result[@intFromEnum(Feature.raoint)] = .{
858	940	.llvm_name = "raoint",
859	941	.description = "Support RAO-INT instructions",
...	...	@@ -947,7 +1029,7 @@ pub const all_features = blk: {
947	1029	.llvm_name = "sha512",
948	1030	.description = "Support SHA512 instructions",
949	1031	.dependencies = featureSet(&[_]Feature{
950		.avx,
	1032	.avx2,
951	1033	}),
952	1034	};
953	1035	result[@intFromEnum(Feature.shstk)] = .{
...	...	@@ -1011,7 +1093,7 @@ pub const all_features = blk: {
1011	1093	.llvm_name = "sm4",
1012	1094	.description = "Support SM4 instructions",
1013	1095	.dependencies = featureSet(&[_]Feature{
1014		.avx,
	1096	.avx2,
1015	1097	}),
1016	1098	};
1017	1099	result[@intFromEnum(Feature.soft_float)] = .{
...	...	@@ -1106,12 +1188,17 @@ pub const all_features = blk: {
1106	1188	.description = "Use Silvermont specific arithmetic costs",
1107	1189	.dependencies = featureSet(&[_]Feature{}),
1108	1190	};
	1191	result[@intFromEnum(Feature.usermsr)] = .{
	1192	.llvm_name = "usermsr",
	1193	.description = "Support USERMSR instructions",
	1194	.dependencies = featureSet(&[_]Feature{}),
	1195	};
1109	1196	result[@intFromEnum(Feature.vaes)] = .{
1110	1197	.llvm_name = "vaes",
1111	1198	.description = "Promote selected AES instructions to AVX512/AVX registers",
1112	1199	.dependencies = featureSet(&[_]Feature{
1113	1200	.aes,
1114		.avx,
	1201	.avx2,
1115	1202	}),
1116	1203	};
1117	1204	result[@intFromEnum(Feature.vpclmulqdq)] = .{
...	...	@@ -1282,6 +1369,239 @@ pub const cpu = struct {
1282	1369	.x87,
1283	1370	}),
1284	1371	};
	1372	pub const arrowlake = CpuModel{
	1373	.name = "arrowlake",
	1374	.llvm_name = "arrowlake",
	1375	.features = featureSet(&[_]Feature{
	1376	.@"64bit",
	1377	.adx,
	1378	.allow_light_256_bit,
	1379	.avxifma,
	1380	.avxneconvert,
	1381	.avxvnni,
	1382	.avxvnniint8,
	1383	.bmi,
	1384	.bmi2,
	1385	.cldemote,
	1386	.clflushopt,
	1387	.clwb,
	1388	.cmov,
	1389	.cmpccxadd,
	1390	.crc32,
	1391	.cx16,
	1392	.enqcmd,
	1393	.f16c,
	1394	.false_deps_perm,
	1395	.false_deps_popcnt,
	1396	.fast_15bytenop,
	1397	.fast_gather,
	1398	.fast_scalar_fsqrt,
	1399	.fast_shld_rotate,
	1400	.fast_variable_crosslane_shuffle,
	1401	.fast_variable_perlane_shuffle,
	1402	.fast_vector_fsqrt,
	1403	.fma,
	1404	.fsgsbase,
	1405	.fxsr,
	1406	.gfni,
	1407	.hreset,
	1408	.idivq_to_divl,
	1409	.invpcid,
	1410	.lzcnt,
	1411	.macrofusion,
	1412	.mmx,
	1413	.movbe,
	1414	.movdir64b,
	1415	.movdiri,
	1416	.no_bypass_delay_blend,
	1417	.no_bypass_delay_mov,
	1418	.no_bypass_delay_shuffle,
	1419	.nopl,
	1420	.pconfig,
	1421	.pku,
	1422	.popcnt,
	1423	.prefer_movmsk_over_vtest,
	1424	.prfchw,
	1425	.ptwrite,
	1426	.rdpid,
	1427	.rdrnd,
	1428	.rdseed,
	1429	.sahf,
	1430	.serialize,
	1431	.sha,
	1432	.shstk,
	1433	.slow_3ops_lea,
	1434	.tuning_fast_imm_vector_shift,
	1435	.uintr,
	1436	.vaes,
	1437	.vpclmulqdq,
	1438	.vzeroupper,
	1439	.waitpkg,
	1440	.widekl,
	1441	.x87,
	1442	.xsavec,
	1443	.xsaveopt,
	1444	.xsaves,
	1445	}),
	1446	};
	1447	pub const arrowlake_s = CpuModel{
	1448	.name = "arrowlake_s",
	1449	.llvm_name = "arrowlake-s",
	1450	.features = featureSet(&[_]Feature{
	1451	.@"64bit",
	1452	.adx,
	1453	.allow_light_256_bit,
	1454	.avxifma,
	1455	.avxneconvert,
	1456	.avxvnni,
	1457	.avxvnniint16,
	1458	.avxvnniint8,
	1459	.bmi,
	1460	.bmi2,
	1461	.cldemote,
	1462	.clflushopt,
	1463	.clwb,
	1464	.cmov,
	1465	.cmpccxadd,
	1466	.crc32,
	1467	.cx16,
	1468	.enqcmd,
	1469	.f16c,
	1470	.false_deps_perm,
	1471	.false_deps_popcnt,
	1472	.fast_15bytenop,
	1473	.fast_gather,
	1474	.fast_scalar_fsqrt,
	1475	.fast_shld_rotate,
	1476	.fast_variable_crosslane_shuffle,
	1477	.fast_variable_perlane_shuffle,
	1478	.fast_vector_fsqrt,
	1479	.fma,
	1480	.fsgsbase,
	1481	.fxsr,
	1482	.gfni,
	1483	.hreset,
	1484	.idivq_to_divl,
	1485	.invpcid,
	1486	.lzcnt,
	1487	.macrofusion,
	1488	.mmx,
	1489	.movbe,
	1490	.movdir64b,
	1491	.movdiri,
	1492	.no_bypass_delay_blend,
	1493	.no_bypass_delay_mov,
	1494	.no_bypass_delay_shuffle,
	1495	.nopl,
	1496	.pconfig,
	1497	.pku,
	1498	.popcnt,
	1499	.prefer_movmsk_over_vtest,
	1500	.prfchw,
	1501	.ptwrite,
	1502	.rdpid,
	1503	.rdrnd,
	1504	.rdseed,
	1505	.sahf,
	1506	.serialize,
	1507	.sha,
	1508	.sha512,
	1509	.shstk,
	1510	.slow_3ops_lea,
	1511	.sm3,
	1512	.sm4,
	1513	.tuning_fast_imm_vector_shift,
	1514	.uintr,
	1515	.vaes,
	1516	.vpclmulqdq,
	1517	.vzeroupper,
	1518	.waitpkg,
	1519	.widekl,
	1520	.x87,
	1521	.xsavec,
	1522	.xsaveopt,
	1523	.xsaves,
	1524	}),
	1525	};
	1526	pub const arrowlake_s = CpuModel{
	1527	.name = "arrowlake_s",
	1528	.llvm_name = "arrowlake_s",
	1529	.features = featureSet(&[_]Feature{
	1530	.@"64bit",
	1531	.adx,
	1532	.allow_light_256_bit,
	1533	.avxifma,
	1534	.avxneconvert,
	1535	.avxvnni,
	1536	.avxvnniint16,
	1537	.avxvnniint8,
	1538	.bmi,
	1539	.bmi2,
	1540	.cldemote,
	1541	.clflushopt,
	1542	.clwb,
	1543	.cmov,
	1544	.cmpccxadd,
	1545	.crc32,
	1546	.cx16,
	1547	.enqcmd,
	1548	.f16c,
	1549	.false_deps_perm,
	1550	.false_deps_popcnt,
	1551	.fast_15bytenop,
	1552	.fast_gather,
	1553	.fast_scalar_fsqrt,
	1554	.fast_shld_rotate,
	1555	.fast_variable_crosslane_shuffle,
	1556	.fast_variable_perlane_shuffle,
	1557	.fast_vector_fsqrt,
	1558	.fma,
	1559	.fsgsbase,
	1560	.fxsr,
	1561	.gfni,
	1562	.hreset,
	1563	.idivq_to_divl,
	1564	.invpcid,
	1565	.lzcnt,
	1566	.macrofusion,
	1567	.mmx,
	1568	.movbe,
	1569	.movdir64b,
	1570	.movdiri,
	1571	.no_bypass_delay_blend,
	1572	.no_bypass_delay_mov,
	1573	.no_bypass_delay_shuffle,
	1574	.nopl,
	1575	.pconfig,
	1576	.pku,
	1577	.popcnt,
	1578	.prefer_movmsk_over_vtest,
	1579	.prfchw,
	1580	.ptwrite,
	1581	.rdpid,
	1582	.rdrnd,
	1583	.rdseed,
	1584	.sahf,
	1585	.serialize,
	1586	.sha,
	1587	.sha512,
	1588	.shstk,
	1589	.slow_3ops_lea,
	1590	.sm3,
	1591	.sm4,
	1592	.tuning_fast_imm_vector_shift,
	1593	.uintr,
	1594	.vaes,
	1595	.vpclmulqdq,
	1596	.vzeroupper,
	1597	.waitpkg,
	1598	.widekl,
	1599	.x87,
	1600	.xsavec,
	1601	.xsaveopt,
	1602	.xsaves,
	1603	}),
	1604	};
1285	1605	pub const athlon = CpuModel{
1286	1606	.name = "athlon",
1287	1607	.llvm_name = "athlon",
...	...	@@ -1807,16 +2127,77 @@ pub const cpu = struct {
1807	2127	.allow_light_256_bit,
1808	2128	.avx512cd,
1809	2129	.avx512dq,
1810		.avx512ifma,
1811		.avx512vbmi,
	2130	.avx512ifma,
	2131	.avx512vbmi,
	2132	.avx512vl,
	2133	.bmi,
	2134	.bmi2,
	2135	.clflushopt,
	2136	.cmov,
	2137	.crc32,
	2138	.cx16,
	2139	.ermsb,
	2140	.evex512,
	2141	.fast_15bytenop,
	2142	.fast_gather,
	2143	.fast_scalar_fsqrt,
	2144	.fast_shld_rotate,
	2145	.fast_variable_crosslane_shuffle,
	2146	.fast_variable_perlane_shuffle,
	2147	.fast_vector_fsqrt,
	2148	.fsgsbase,
	2149	.fxsr,
	2150	.idivq_to_divl,
	2151	.invpcid,
	2152	.lzcnt,
	2153	.macrofusion,
	2154	.mmx,
	2155	.movbe,
	2156	.no_bypass_delay_blend,
	2157	.no_bypass_delay_mov,
	2158	.no_bypass_delay_shuffle,
	2159	.nopl,
	2160	.pclmul,
	2161	.pku,
	2162	.popcnt,
	2163	.prefer_256_bit,
	2164	.prfchw,
	2165	.rdrnd,
	2166	.rdseed,
	2167	.sahf,
	2168	.sha,
	2169	.slow_3ops_lea,
	2170	.tuning_fast_imm_vector_shift,
	2171	.vzeroupper,
	2172	.x87,
	2173	.xsavec,
	2174	.xsaveopt,
	2175	.xsaves,
	2176	}),
	2177	};
	2178	pub const cascadelake = CpuModel{
	2179	.name = "cascadelake",
	2180	.llvm_name = "cascadelake",
	2181	.features = featureSet(&[_]Feature{
	2182	.@"64bit",
	2183	.adx,
	2184	.aes,
	2185	.allow_light_256_bit,
	2186	.avx512bw,
	2187	.avx512cd,
	2188	.avx512dq,
1812	2189	.avx512vl,
	2190	.avx512vnni,
1813	2191	.bmi,
1814	2192	.bmi2,
1815	2193	.clflushopt,
	2194	.clwb,
1816	2195	.cmov,
1817	2196	.crc32,
1818	2197	.cx16,
1819	2198	.ermsb,
	2199	.evex512,
	2200	.false_deps_popcnt,
1820	2201	.fast_15bytenop,
1821	2202	.fast_gather,
1822	2203	.fast_scalar_fsqrt,
...	...	@@ -1824,6 +2205,7 @@ pub const cpu = struct {
1824	2205	.fast_variable_crosslane_shuffle,
1825	2206	.fast_variable_perlane_shuffle,
1826	2207	.fast_vector_fsqrt,
	2208	.faster_shift_than_shuffle,
1827	2209	.fsgsbase,
1828	2210	.fxsr,
1829	2211	.idivq_to_divl,
...	...	@@ -1844,7 +2226,6 @@ pub const cpu = struct {
1844	2226	.rdrnd,
1845	2227	.rdseed,
1846	2228	.sahf,
1847		.sha,
1848	2229	.slow_3ops_lea,
1849	2230	.tuning_fast_imm_vector_shift,
1850	2231	.vzeroupper,
...	...	@@ -1854,27 +2235,30 @@ pub const cpu = struct {
1854	2235	.xsaves,
1855	2236	}),
1856	2237	};
1857		pub const cascadelake = CpuModel{
1858		.name = "cascadelake",
1859		.llvm_name = "cascadelake",
	2238	pub const clearwaterforest = CpuModel{
	2239	.name = "clearwaterforest",
	2240	.llvm_name = "clearwaterforest",
1860	2241	.features = featureSet(&[_]Feature{
1861	2242	.@"64bit",
1862	2243	.adx,
1863		.aes,
1864	2244	.allow_light_256_bit,
1865		.avx512bw,
1866		.avx512cd,
1867		.avx512dq,
1868		.avx512vl,
1869		.avx512vnni,
	2245	.avxifma,
	2246	.avxneconvert,
	2247	.avxvnni,
	2248	.avxvnniint16,
	2249	.avxvnniint8,
1870	2250	.bmi,
1871	2251	.bmi2,
	2252	.cldemote,
1872	2253	.clflushopt,
1873	2254	.clwb,
1874	2255	.cmov,
	2256	.cmpccxadd,
1875	2257	.crc32,
1876	2258	.cx16,
1877		.ermsb,
	2259	.enqcmd,
	2260	.f16c,
	2261	.false_deps_perm,
1878	2262	.false_deps_popcnt,
1879	2263	.fast_15bytenop,
1880	2264	.fast_gather,
...	...	@@ -1883,30 +2267,49 @@ pub const cpu = struct {
1883	2267	.fast_variable_crosslane_shuffle,
1884	2268	.fast_variable_perlane_shuffle,
1885	2269	.fast_vector_fsqrt,
1886		.faster_shift_than_shuffle,
	2270	.fma,
1887	2271	.fsgsbase,
1888	2272	.fxsr,
	2273	.gfni,
	2274	.hreset,
1889	2275	.idivq_to_divl,
1890	2276	.invpcid,
1891	2277	.lzcnt,
1892	2278	.macrofusion,
1893	2279	.mmx,
1894	2280	.movbe,
	2281	.movdir64b,
	2282	.movdiri,
1895	2283	.no_bypass_delay_blend,
1896	2284	.no_bypass_delay_mov,
1897	2285	.no_bypass_delay_shuffle,
1898	2286	.nopl,
1899		.pclmul,
	2287	.pconfig,
1900	2288	.pku,
1901	2289	.popcnt,
1902		.prefer_256_bit,
	2290	.prefer_movmsk_over_vtest,
	2291	.prefetchi,
1903	2292	.prfchw,
	2293	.ptwrite,
	2294	.rdpid,
1904	2295	.rdrnd,
1905	2296	.rdseed,
1906	2297	.sahf,
	2298	.serialize,
	2299	.sha,
	2300	.sha512,
	2301	.shstk,
1907	2302	.slow_3ops_lea,
	2303	.sm3,
	2304	.sm4,
1908	2305	.tuning_fast_imm_vector_shift,
	2306	.uintr,
	2307	.usermsr,
	2308	.vaes,
	2309	.vpclmulqdq,
1909	2310	.vzeroupper,
	2311	.waitpkg,
	2312	.widekl,
1910	2313	.x87,
1911	2314	.xsavec,
1912	2315	.xsaveopt,
...	...	@@ -1934,6 +2337,7 @@ pub const cpu = struct {
1934	2337	.crc32,
1935	2338	.cx16,
1936	2339	.ermsb,
	2340	.evex512,
1937	2341	.false_deps_popcnt,
1938	2342	.fast_15bytenop,
1939	2343	.fast_gather,
...	...	@@ -2039,6 +2443,7 @@ pub const cpu = struct {
2039	2443	.cx16,
2040	2444	.enqcmd,
2041	2445	.ermsb,
	2446	.evex512,
2042	2447	.false_deps_getmant,
2043	2448	.false_deps_mulc,
2044	2449	.false_deps_mullq,
...	...	@@ -2195,6 +2600,66 @@ pub const cpu = struct {
2195	2600	.xsaves,
2196	2601	}),
2197	2602	};
	2603	pub const gracemont = CpuModel{
	2604	.name = "gracemont",
	2605	.llvm_name = "gracemont",
	2606	.features = featureSet(&[_]Feature{
	2607	.@"64bit",
	2608	.adx,
	2609	.avxvnni,
	2610	.bmi,
	2611	.bmi2,
	2612	.cldemote,
	2613	.clflushopt,
	2614	.clwb,
	2615	.cmov,
	2616	.crc32,
	2617	.cx16,
	2618	.f16c,
	2619	.false_deps_popcnt,
	2620	.fast_15bytenop,
	2621	.fast_scalar_fsqrt,
	2622	.fast_variable_perlane_shuffle,
	2623	.fast_vector_fsqrt,
	2624	.fma,
	2625	.fsgsbase,
	2626	.fxsr,
	2627	.gfni,
	2628	.hreset,
	2629	.idivl_to_divb,
	2630	.idivq_to_divl,
	2631	.invpcid,
	2632	.lzcnt,
	2633	.macrofusion,
	2634	.mmx,
	2635	.movbe,
	2636	.movdir64b,
	2637	.movdiri,
	2638	.nopl,
	2639	.pconfig,
	2640	.pku,
	2641	.popcnt,
	2642	.prfchw,
	2643	.ptwrite,
	2644	.rdpid,
	2645	.rdrnd,
	2646	.rdseed,
	2647	.sahf,
	2648	.serialize,
	2649	.sha,
	2650	.shstk,
	2651	.slow_3ops_lea,
	2652	.vaes,
	2653	.vpclmulqdq,
	2654	.vzeroupper,
	2655	.waitpkg,
	2656	.widekl,
	2657	.x87,
	2658	.xsavec,
	2659	.xsaveopt,
	2660	.xsaves,
	2661	}),
	2662	};
2198	2663	pub const grandridge = CpuModel{
2199	2664	.name = "grandridge",
2200	2665	.llvm_name = "grandridge",
...	...	@@ -2235,7 +2700,6 @@ pub const cpu = struct {
2235	2700	.popcnt,
2236	2701	.prfchw,
2237	2702	.ptwrite,
2238		.raoint,
2239	2703	.rdpid,
2240	2704	.rdrnd,
2241	2705	.rdseed,
...	...	@@ -2289,6 +2753,7 @@ pub const cpu = struct {
2289	2753	.cx16,
2290	2754	.enqcmd,
2291	2755	.ermsb,
	2756	.evex512,
2292	2757	.false_deps_getmant,
2293	2758	.false_deps_mulc,
2294	2759	.false_deps_mullq,
...	...	@@ -2376,6 +2841,7 @@ pub const cpu = struct {
2376	2841	.cx16,
2377	2842	.enqcmd,
2378	2843	.ermsb,
	2844	.evex512,
2379	2845	.false_deps_getmant,
2380	2846	.false_deps_mulc,
2381	2847	.false_deps_mullq,
...	...	@@ -2537,6 +3003,7 @@ pub const cpu = struct {
2537	3003	.crc32,
2538	3004	.cx16,
2539	3005	.ermsb,
	3006	.evex512,
2540	3007	.fast_15bytenop,
2541	3008	.fast_gather,
2542	3009	.fast_scalar_fsqrt,
...	...	@@ -2601,6 +3068,7 @@ pub const cpu = struct {
2601	3068	.crc32,
2602	3069	.cx16,
2603	3070	.ermsb,
	3071	.evex512,
2604	3072	.fast_15bytenop,
2605	3073	.fast_gather,
2606	3074	.fast_scalar_fsqrt,
...	...	@@ -2760,6 +3228,7 @@ pub const cpu = struct {
2760	3228	.cmov,
2761	3229	.crc32,
2762	3230	.cx16,
	3231	.evex512,
2763	3232	.fast_gather,
2764	3233	.fast_movbe,
2765	3234	.fsgsbase,
...	...	@@ -2801,6 +3270,7 @@ pub const cpu = struct {
2801	3270	.cmov,
2802	3271	.crc32,
2803	3272	.cx16,
	3273	.evex512,
2804	3274	.fast_gather,
2805	3275	.fast_movbe,
2806	3276	.fsgsbase,
...	...	@@ -2836,6 +3306,85 @@ pub const cpu = struct {
2836	3306	.vzeroupper,
2837	3307	}),
2838	3308	};
	3309	pub const lunarlake = CpuModel{
	3310	.name = "lunarlake",
	3311	.llvm_name = "lunarlake",
	3312	.features = featureSet(&[_]Feature{
	3313	.@"64bit",
	3314	.adx,
	3315	.allow_light_256_bit,
	3316	.avxifma,
	3317	.avxneconvert,
	3318	.avxvnni,
	3319	.avxvnniint16,
	3320	.avxvnniint8,
	3321	.bmi,
	3322	.bmi2,
	3323	.cldemote,
	3324	.clflushopt,
	3325	.clwb,
	3326	.cmov,
	3327	.cmpccxadd,
	3328	.crc32,
	3329	.cx16,
	3330	.enqcmd,
	3331	.f16c,
	3332	.false_deps_perm,
	3333	.false_deps_popcnt,
	3334	.fast_15bytenop,
	3335	.fast_gather,
	3336	.fast_scalar_fsqrt,
	3337	.fast_shld_rotate,
	3338	.fast_variable_crosslane_shuffle,
	3339	.fast_variable_perlane_shuffle,
	3340	.fast_vector_fsqrt,
	3341	.fma,
	3342	.fsgsbase,
	3343	.fxsr,
	3344	.gfni,
	3345	.hreset,
	3346	.idivq_to_divl,
	3347	.invpcid,
	3348	.lzcnt,
	3349	.macrofusion,
	3350	.mmx,
	3351	.movbe,
	3352	.movdir64b,
	3353	.movdiri,
	3354	.no_bypass_delay_blend,
	3355	.no_bypass_delay_mov,
	3356	.no_bypass_delay_shuffle,
	3357	.nopl,
	3358	.pconfig,
	3359	.pku,
	3360	.popcnt,
	3361	.prefer_movmsk_over_vtest,
	3362	.prfchw,
	3363	.ptwrite,
	3364	.rdpid,
	3365	.rdrnd,
	3366	.rdseed,
	3367	.sahf,
	3368	.serialize,
	3369	.sha,
	3370	.sha512,
	3371	.shstk,
	3372	.slow_3ops_lea,
	3373	.sm3,
	3374	.sm4,
	3375	.tuning_fast_imm_vector_shift,
	3376	.uintr,
	3377	.vaes,
	3378	.vpclmulqdq,
	3379	.vzeroupper,
	3380	.waitpkg,
	3381	.widekl,
	3382	.x87,
	3383	.xsavec,
	3384	.xsaveopt,
	3385	.xsaves,
	3386	}),
	3387	};
2839	3388	pub const meteorlake = CpuModel{
2840	3389	.name = "meteorlake",
2841	3390	.llvm_name = "meteorlake",
...	...	@@ -2979,6 +3528,86 @@ pub const cpu = struct {
2979	3528	.x87,
2980	3529	}),
2981	3530	};
	3531	pub const pantherlake = CpuModel{
	3532	.name = "pantherlake",
	3533	.llvm_name = "pantherlake",
	3534	.features = featureSet(&[_]Feature{
	3535	.@"64bit",
	3536	.adx,
	3537	.allow_light_256_bit,
	3538	.avxifma,
	3539	.avxneconvert,
	3540	.avxvnni,
	3541	.avxvnniint16,
	3542	.avxvnniint8,
	3543	.bmi,
	3544	.bmi2,
	3545	.cldemote,
	3546	.clflushopt,
	3547	.clwb,
	3548	.cmov,
	3549	.cmpccxadd,
	3550	.crc32,
	3551	.cx16,
	3552	.enqcmd,
	3553	.f16c,
	3554	.false_deps_perm,
	3555	.false_deps_popcnt,
	3556	.fast_15bytenop,
	3557	.fast_gather,
	3558	.fast_scalar_fsqrt,
	3559	.fast_shld_rotate,
	3560	.fast_variable_crosslane_shuffle,
	3561	.fast_variable_perlane_shuffle,
	3562	.fast_vector_fsqrt,
	3563	.fma,
	3564	.fsgsbase,
	3565	.fxsr,
	3566	.gfni,
	3567	.hreset,
	3568	.idivq_to_divl,
	3569	.invpcid,
	3570	.lzcnt,
	3571	.macrofusion,
	3572	.mmx,
	3573	.movbe,
	3574	.movdir64b,
	3575	.movdiri,
	3576	.no_bypass_delay_blend,
	3577	.no_bypass_delay_mov,
	3578	.no_bypass_delay_shuffle,
	3579	.nopl,
	3580	.pconfig,
	3581	.pku,
	3582	.popcnt,
	3583	.prefer_movmsk_over_vtest,
	3584	.prefetchi,
	3585	.prfchw,
	3586	.ptwrite,
	3587	.rdpid,
	3588	.rdrnd,
	3589	.rdseed,
	3590	.sahf,
	3591	.serialize,
	3592	.sha,
	3593	.sha512,
	3594	.shstk,
	3595	.slow_3ops_lea,
	3596	.sm3,
	3597	.sm4,
	3598	.tuning_fast_imm_vector_shift,
	3599	.uintr,
	3600	.vaes,
	3601	.vpclmulqdq,
	3602	.vzeroupper,
	3603	.waitpkg,
	3604	.widekl,
	3605	.x87,
	3606	.xsavec,
	3607	.xsaveopt,
	3608	.xsaves,
	3609	}),
	3610	};
2982	3611	pub const penryn = CpuModel{
2983	3612	.name = "penryn",
2984	3613	.llvm_name = "penryn",
...	...	@@ -3211,6 +3840,7 @@ pub const cpu = struct {
3211	3840	.crc32,
3212	3841	.cx16,
3213	3842	.ermsb,
	3843	.evex512,
3214	3844	.fast_15bytenop,
3215	3845	.fast_gather,
3216	3846	.fast_scalar_fsqrt,
...	...	@@ -3309,6 +3939,7 @@ pub const cpu = struct {
3309	3939	.cx16,
3310	3940	.enqcmd,
3311	3941	.ermsb,
	3942	.evex512,
3312	3943	.false_deps_getmant,
3313	3944	.false_deps_mulc,
3314	3945	.false_deps_mullq,
...	...	@@ -3479,6 +4110,7 @@ pub const cpu = struct {
3479	4110	.crc32,
3480	4111	.cx16,
3481	4112	.ermsb,
	4113	.evex512,
3482	4114	.false_deps_popcnt,
3483	4115	.fast_15bytenop,
3484	4116	.fast_gather,
...	...	@@ -3589,6 +4221,7 @@ pub const cpu = struct {
3589	4221	.crc32,
3590	4222	.cx16,
3591	4223	.ermsb,
	4224	.evex512,
3592	4225	.false_deps_popcnt,
3593	4226	.fast_15bytenop,
3594	4227	.fast_gather,
...	...	@@ -3684,6 +4317,7 @@ pub const cpu = struct {
3684	4317	.crc32,
3685	4318	.cx16,
3686	4319	.ermsb,
	4320	.evex512,
3687	4321	.fast_15bytenop,
3688	4322	.fast_gather,
3689	4323	.fast_scalar_fsqrt,
...	...	@@ -3904,6 +4538,7 @@ pub const cpu = struct {
3904	4538	.cmov,
3905	4539	.crc32,
3906	4540	.cx16,
	4541	.evex512,
3907	4542	.false_deps_popcnt,
3908	4543	.fast_15bytenop,
3909	4544	.fast_gather,
...	...	@@ -4056,7 +4691,6 @@ pub const cpu = struct {
4056	4691	.@"64bit",
4057	4692	.adx,
4058	4693	.allow_light_256_bit,
4059		.avx2,
4060	4694	.bmi,
4061	4695	.bmi2,
4062	4696	.branchfusion,
...	...	@@ -4134,6 +4768,7 @@ pub const cpu = struct {
4134	4768	.cmov,
4135	4769	.crc32,
4136	4770	.cx16,
	4771	.evex512,
4137	4772	.fast_15bytenop,
4138	4773	.fast_bextr,
4139	4774	.fast_lzcnt,

tools/update_cpu_features.zig+16

...	...	@@ -183,6 +183,10 @@ const llvm_targets = [_]LlvmTarget{
183	183	.llvm_name = "apple-a16",
184	184	.flatten = true,
185	185	},
	186	.{
	187	.llvm_name = "apple-a17",
	188	.flatten = true,
	189	},
186	190	.{
187	191	.llvm_name = "apple-a7-sysreg",
188	192	.flatten = true,
...	...	@@ -207,6 +211,10 @@ const llvm_targets = [_]LlvmTarget{
207	211	.llvm_name = "cortex-x3",
208	212	.flatten = true,
209	213	},
	214	.{
	215	.llvm_name = "cortex-x4",
	216	.flatten = true,
	217	},
210	218	.{
211	219	.llvm_name = "falkor",
212	220	.flatten = true,
...	...	@@ -257,6 +265,10 @@ const llvm_targets = [_]LlvmTarget{
257	265	.llvm_name = "ampere1",
258	266	.flatten = true,
259	267	},
	268	.{
	269	.llvm_name = "ampere1b",
	270	.flatten = true,
	271	},
260	272	},
261	273	.extra_cpus = &.{
262	274	.{
...	...	@@ -681,6 +693,10 @@ const llvm_targets = [_]LlvmTarget{
681	693	.llvm_name = "armv9.4-a",
682	694	.zig_name = "v9_4a",
683	695	},
	696	.{
	697	.llvm_name = "armv9.5-a",
	698	.zig_name = "v9_5a",
	699	},
684	700	.{
685	701	.llvm_name = "armv9-a",
686	702	.zig_name = "v9a",