| ... | ... | @@ -436,7 +436,6 @@ pub fn cacheLineForCpu(cpu: std.Target.Cpu) u16 { |
| 436 | 436 | // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips.go#L7 |
| 437 | 437 | // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mipsle.go#L7 |
| 438 | 438 | // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_mips64x.go#L9 |
| 439 | | // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_riscv64.go#L7 |
| 440 | 439 | // - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/sparc/include/asm/cache.h#L14 |
| 441 | 440 | .arm, |
| 442 | 441 | .armeb, |
| ... | ... | @@ -446,8 +445,6 @@ pub fn cacheLineForCpu(cpu: std.Target.Cpu) u16 { |
| 446 | 445 | .mipsel, |
| 447 | 446 | .mips64, |
| 448 | 447 | .mips64el, |
| 449 | | .riscv32, |
| 450 | | .riscv64, |
| 451 | 448 | .sparc, |
| 452 | 449 | .sparc64, |
| 453 | 450 | => 32, |
| ... | ... | @@ -471,6 +468,7 @@ pub fn cacheLineForCpu(cpu: std.Target.Cpu) u16 { |
| 471 | 468 | // - https://github.com/golang/go/blob/dda2991c2ea0c5914714469c4defc2562a907230/src/internal/cpu/cpu_x86.go#L9 |
| 472 | 469 | // - https://github.com/golang/go/blob/0a9321ad7f8c91e1b0c7184731257df923977eb9/src/internal/cpu/cpu_loong64.go#L11 |
| 473 | 470 | // - https://github.com/golang/go/blob/3dd58676054223962cd915bb0934d1f9f489d4d2/src/internal/cpu/cpu_wasm.go#L7 |
| 471 | // - https://github.com/golang/go/blob/19e923182e590ae6568c2c714f20f32512aeb3e3/src/internal/cpu/cpu_riscv64.go#L7 |
| 474 | 472 | // - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/xtensa/variants/csp/include/variant/core.h#L209 |
| 475 | 473 | // - https://github.com/torvalds/linux/blob/3a7e02c040b130b5545e4b115aada7bacd80a2b6/arch/csky/Kconfig#L183 |
| 476 | 474 | // - https://www.xmos.com/download/The-XMOS-XS3-Architecture.pdf |