From 9848623e62d75507d94f4e4276c5e5c888d99f5d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= Date: Sun, 21 Jul 2024 14:02:24 +0200 Subject: [PATCH 1/8] std.Target: Remove the `renderscript32`/`renderscript64` arch tags. It's dead: https://developer.android.com/guide/topics/renderscript/migrate --- lib/compiler/aro/aro/target.zig | 6 ------ lib/std/Target.zig | 16 ---------------- src/Type.zig | 2 -- src/Zcu.zig | 2 -- src/codegen/llvm.zig | 6 ------ src/target.zig | 2 -- 6 files changed, 34 deletions(-) diff --git a/lib/compiler/aro/aro/target.zig b/lib/compiler/aro/aro/target.zig index e6dc776e3085c3737e25ccff14fa043b7138943d..83ee4f886097a3dc0fa5f7d10206f39dafb9a087 100644 --- a/lib/compiler/aro/aro/target.zig +++ b/lib/compiler/aro/aro/target.zig @@ -488,7 +488,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target { .shave, .lanai, .wasm32, - .renderscript32, .aarch64_32, .spirv32, .loongarch32, @@ -504,7 +503,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target { .hsail64 => copy.cpu.arch = .hsail, .spir64 => copy.cpu.arch = .spir, .spirv64 => copy.cpu.arch = .spirv32, - .renderscript64 => copy.cpu.arch = .renderscript32, .loongarch64 => copy.cpu.arch = .loongarch32, .mips64 => copy.cpu.arch = .mips, .mips64el => copy.cpu.arch = .mipsel, @@ -550,7 +548,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target { .hsail64, .spir64, .spirv64, - .renderscript64, .loongarch64, .mips64, .mips64el, @@ -574,7 +571,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target { .nvptx => copy.cpu.arch = .nvptx64, .powerpc => copy.cpu.arch = .powerpc64, .powerpcle => copy.cpu.arch = .powerpc64le, - .renderscript32 => copy.cpu.arch = .renderscript64, .riscv32 => copy.cpu.arch = .riscv64, .sparc => copy.cpu.arch = .sparc64, .spir => copy.cpu.arch = .spir64, @@ -651,8 +647,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 { .lanai => "lanai", .wasm32 => "wasm32", .wasm64 => "wasm64", - .renderscript32 => "renderscript32", - .renderscript64 => "renderscript64", .ve => "ve", // Note: spu_2 is not supported in LLVM; this is the Zig arch name .spu_2 => "spu_2", diff --git a/lib/std/Target.zig b/lib/std/Target.zig index 1bf608ffb1b6ba6349c1c7bf0a0eee868cd2d7af..aa800114b550f7ec5622afca2c8589829179dc40 100644 --- a/lib/std/Target.zig +++ b/lib/std/Target.zig @@ -1026,8 +1026,6 @@ pub const Cpu = struct { lanai, wasm32, wasm64, - renderscript32, - renderscript64, ve, spu_2, @@ -1167,7 +1165,6 @@ pub const Cpu = struct { .shave => .NONE, .lanai => .LANAI, .wasm32 => .NONE, - .renderscript32 => .NONE, .aarch64_32 => .AARCH64, .aarch64 => .AARCH64, .aarch64_be => .AARCH64, @@ -1182,7 +1179,6 @@ pub const Cpu = struct { .hsail64 => .NONE, .spir64 => .NONE, .wasm64 => .NONE, - .renderscript64 => .NONE, .amdgcn => .AMDGPU, .bpfel => .BPF, .bpfeb => .BPF, @@ -1231,7 +1227,6 @@ pub const Cpu = struct { .shave => .Unknown, .lanai => .Unknown, .wasm32 => .Unknown, - .renderscript32 => .Unknown, .aarch64_32 => .ARM64, .aarch64 => .ARM64, .aarch64_be => .ARM64, @@ -1246,7 +1241,6 @@ pub const Cpu = struct { .hsail64 => .Unknown, .spir64 => .Unknown, .wasm64 => .Unknown, - .renderscript64 => .Unknown, .amdgcn => .Unknown, .bpfel => .Unknown, .bpfeb => .Unknown, @@ -1299,8 +1293,6 @@ pub const Cpu = struct { .thumb, .spir, .spir64, - .renderscript32, - .renderscript64, .shave, .ve, .spu_2, @@ -1794,8 +1786,6 @@ pub const DynamicLinker = struct { .kalimba, .shave, .lanai, - .renderscript32, - .renderscript64, .ve, .dxil, .loongarch32, @@ -1901,7 +1891,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 { .shave, .lanai, .wasm32, - .renderscript32, .aarch64_32, .spirv32, .loongarch32, @@ -1922,7 +1911,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 { .hsail64, .spir64, .wasm64, - .renderscript64, .amdgcn, .bpfel, .bpfeb, @@ -2426,7 +2414,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 { .spirv32, .kalimba, .shave, - .renderscript32, .ve, .spu_2, .xtensa, @@ -2453,7 +2440,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 { .s390x, .spir64, .spirv64, - .renderscript64, => 8, .aarch64, @@ -2545,7 +2531,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 { .spirv32, .kalimba, .shave, - .renderscript32, .ve, .spu_2, .xtensa, @@ -2579,7 +2564,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 { .s390x, .spir64, .spirv64, - .renderscript64, => 8, .aarch64, diff --git a/src/Type.zig b/src/Type.zig index 6ccd2841a6c1f399bcb6c7d0fef38d22c5b3a77b..80dd3bed40a677066f1fa3d654d491c4e503d3dc 100644 --- a/src/Type.zig +++ b/src/Type.zig @@ -1655,14 +1655,12 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 { .hsail, .spir, .kalimba, - .renderscript32, .spirv, .spirv32, .shave, .amdil64, .hsail64, .spir64, - .renderscript64, .ve, .spirv64, .dxil, diff --git a/src/Zcu.zig b/src/Zcu.zig index 0e43ba59ba05794659e32abf8e5eb10a53a1d0d5..741ca825fd3dd7e6e32a56624c3a4034afc21516 100644 --- a/src/Zcu.zig +++ b/src/Zcu.zig @@ -3263,7 +3263,6 @@ pub fn atomicPtrAlignment( .lanai, .shave, .wasm32, - .renderscript32, .csky, .spirv32, .dxil, @@ -3286,7 +3285,6 @@ pub fn atomicPtrAlignment( .hsail64, .spir64, .wasm64, - .renderscript64, .ve, .spirv64, .loongarch64, diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig index a126897614647e9f09063470d5013ed7d381153c..2835d627f70889a753a248fddac64fc7dda75e3d 100644 --- a/src/codegen/llvm.zig +++ b/src/codegen/llvm.zig @@ -97,8 +97,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 { .lanai => "lanai", .wasm32 => "wasm32", .wasm64 => "wasm64", - .renderscript32 => "renderscript32", - .renderscript64 => "renderscript64", .ve => "ve", .spu_2 => return error.@"LLVM backend does not support SPU Mark II", }; @@ -321,8 +319,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType { .lanai => .lanai, .wasm32 => .wasm32, .wasm64 => .wasm64, - .renderscript32 => .renderscript32, - .renderscript64 => .renderscript64, .ve => .ve, .spu_2 => .UnknownArch, }; @@ -12106,8 +12102,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void { .spirv32, .spirv64, .kalimba, - .renderscript32, - .renderscript64, .dxil, => {}, diff --git a/src/target.zig b/src/target.zig index 23f7b285de8d3d13cd478ee5d37db9540c558623..c69ac6d0bf7117c4bcb1e964ebbb170dea55fa1c 100644 --- a/src/target.zig +++ b/src/target.zig @@ -167,8 +167,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool { .lanai, .wasm32, .wasm64, - .renderscript32, - .renderscript64, .ve, => true, -- 2.54.0 From c825b567b26c475e058e074e5d22af006854fab6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= Date: Sun, 21 Jul 2024 14:04:52 +0200 Subject: [PATCH 2/8] std.Target: Remove the `r600` arch tag. These are quite old GPUs, and it is unlikely that Zig will ever be able to target them. See: https://en.wikipedia.org/wiki/Radeon_HD_2000_series --- lib/compiler/aro/aro/target.zig | 3 --- lib/std/Target.zig | 8 -------- src/Type.zig | 1 - src/Zcu.zig | 1 - src/codegen/llvm.zig | 3 --- src/target.zig | 1 - test/behavior/align.zig | 1 - test/llvm_targets.zig | 1 - 8 files changed, 19 deletions(-) diff --git a/lib/compiler/aro/aro/target.zig b/lib/compiler/aro/aro/target.zig index 83ee4f886097a3dc0fa5f7d10206f39dafb9a087..7c6c879683e21ae48a4a25ab22cc2e2c7cc7f6d6 100644 --- a/lib/compiler/aro/aro/target.zig +++ b/lib/compiler/aro/aro/target.zig @@ -470,7 +470,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target { .mipsel, .powerpc, .powerpcle, - .r600, .riscv32, .sparc, .sparcel, @@ -527,7 +526,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target { .lanai, .m68k, .msp430, - .r600, .shave, .sparcel, .spu_2, @@ -616,7 +614,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 { .powerpcle => "powerpcle", .powerpc64 => "powerpc64", .powerpc64le => "powerpc64le", - .r600 => "r600", .amdgcn => "amdgcn", .riscv32 => "riscv32", .riscv64 => "riscv64", diff --git a/lib/std/Target.zig b/lib/std/Target.zig index aa800114b550f7ec5622afca2c8589829179dc40..d281bcf6dbeebaed0ba76aba24de2a2c680cb7e0 100644 --- a/lib/std/Target.zig +++ b/lib/std/Target.zig @@ -994,7 +994,6 @@ pub const Cpu = struct { powerpcle, powerpc64, powerpc64le, - r600, amdgcn, riscv32, riscv64, @@ -1146,7 +1145,6 @@ pub const Cpu = struct { .mips => .MIPS, .mipsel => .MIPS_RS3_LE, .powerpc, .powerpcle => .PPC, - .r600 => .NONE, .riscv32 => .RISCV, .sparc => .SPARC, .sparcel => .SPARC, @@ -1208,7 +1206,6 @@ pub const Cpu = struct { .mips => .Unknown, .mipsel => .Unknown, .powerpc, .powerpcle => .POWERPC, - .r600 => .Unknown, .riscv32 => .RISCV32, .sparc => .Unknown, .sparcel => .Unknown, @@ -1282,7 +1279,6 @@ pub const Cpu = struct { .tcele, .powerpcle, .powerpc64le, - .r600, .riscv32, .riscv64, .x86, @@ -1772,7 +1768,6 @@ pub const DynamicLinker = struct { .hexagon, .m68k, .msp430, - .r600, .amdgcn, .tce, .tcele, @@ -1874,7 +1869,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 { .mipsel, .powerpc, .powerpcle, - .r600, .riscv32, .sparcel, .tce, @@ -2436,7 +2430,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 { .lanai, .nvptx, .nvptx64, - .r600, .s390x, .spir64, .spirv64, @@ -2560,7 +2553,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 { .lanai, .nvptx, .nvptx64, - .r600, .s390x, .spir64, .spirv64, diff --git a/src/Type.zig b/src/Type.zig index 80dd3bed40a677066f1fa3d654d491c4e503d3dc..bfe9a94d33b7c793010b4c053f13614ec6e44b84 100644 --- a/src/Type.zig +++ b/src/Type.zig @@ -1599,7 +1599,6 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 { .mipsel, .powerpc, .powerpcle, - .r600, .amdgcn, .riscv32, .sparc, diff --git a/src/Zcu.zig b/src/Zcu.zig index 741ca825fd3dd7e6e32a56624c3a4034afc21516..dbece763ec27461ad159886d220700e232cc74ab 100644 --- a/src/Zcu.zig +++ b/src/Zcu.zig @@ -3246,7 +3246,6 @@ pub fn atomicPtrAlignment( .nvptx, .powerpc, .powerpcle, - .r600, .riscv32, .sparc, .sparcel, diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig index 2835d627f70889a753a248fddac64fc7dda75e3d..b56ca01484b96c9249e5f377f70c224ded922c47 100644 --- a/src/codegen/llvm.zig +++ b/src/codegen/llvm.zig @@ -65,7 +65,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 { .powerpcle => "powerpcle", .powerpc64 => "powerpc64", .powerpc64le => "powerpc64le", - .r600 => "r600", .amdgcn => "amdgcn", .riscv32 => "riscv32", .riscv64 => "riscv64", @@ -287,7 +286,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType { .powerpcle => .ppcle, .powerpc64 => .ppc64, .powerpc64le => .ppc64le, - .r600 => .r600, .amdgcn => .amdgcn, .riscv32 => .riscv32, .riscv64 => .riscv64, @@ -12090,7 +12088,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void { // LLVM backends that have no initialization functions. .tce, .tcele, - .r600, .amdil, .amdil64, .hsail, diff --git a/src/target.zig b/src/target.zig index c69ac6d0bf7117c4bcb1e964ebbb170dea55fa1c..19b8320cd829c0e6962134385c703da232b68f3a 100644 --- a/src/target.zig +++ b/src/target.zig @@ -135,7 +135,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool { .powerpcle, .powerpc64, .powerpc64le, - .r600, .amdgcn, .riscv32, .riscv64, diff --git a/test/behavior/align.zig b/test/behavior/align.zig index 1ede6ad433f0ef934e6369c956882a934679ba6e..0b588ce091d8aa476a0a20856bfd4d635721af7b 100644 --- a/test/behavior/align.zig +++ b/test/behavior/align.zig @@ -94,7 +94,6 @@ test "alignment and size of structs with 128-bit fields" { .mipsel, .powerpc, .powerpcle, - .r600, .amdgcn, .riscv32, .sparc, diff --git a/test/llvm_targets.zig b/test/llvm_targets.zig index 31b355a862e73c44bc7459233d1524f9faeff132..07db7ad7826ff158df5306f5663f81aa96e62e52 100644 --- a/test/llvm_targets.zig +++ b/test/llvm_targets.zig @@ -76,7 +76,6 @@ const targets = [_]std.Target.Query{ .{ .cpu_arch = .powerpc64le, .os_tag = .linux, .abi = .gnu }, .{ .cpu_arch = .powerpc64le, .os_tag = .linux, .abi = .musl }, .{ .cpu_arch = .powerpc64le, .os_tag = .linux, .abi = .none }, - //.{ .cpu_arch = .r600, .os_tag = .mesa3d, .abi = .none }, .{ .cpu_arch = .riscv32, .os_tag = .freestanding, .abi = .none }, .{ .cpu_arch = .riscv32, .os_tag = .linux, .abi = .none }, .{ .cpu_arch = .riscv64, .os_tag = .freestanding, .abi = .none }, -- 2.54.0 From 67a052df81dbd40a49ce07b58e854d56b1def03a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= Date: Sun, 21 Jul 2024 14:07:35 +0200 Subject: [PATCH 3/8] std.Target: Remove `amdil`/`amdil64` arch tags. This is really obscure and no one is 100% sure what it is. It seems to be old and unused. My suspicion is that it's just an old term for "AMDGPU" before it was upstreamed to LLVM. See: https://github.com/search?q=repo%3Allvm%2Fllvm-project+amdil&type=code --- lib/compiler/aro/aro/target.zig | 6 ------ lib/std/Target.zig | 16 ---------------- src/Type.zig | 2 -- src/Zcu.zig | 2 -- src/codegen/llvm.zig | 6 ------ src/target.zig | 2 -- 6 files changed, 34 deletions(-) diff --git a/lib/compiler/aro/aro/target.zig b/lib/compiler/aro/aro/target.zig index 7c6c879683e21ae48a4a25ab22cc2e2c7cc7f6d6..8d51fbabfd3590d7cb7e788e8cb4d8d02133aa6f 100644 --- a/lib/compiler/aro/aro/target.zig +++ b/lib/compiler/aro/aro/target.zig @@ -480,7 +480,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target { .x86, .xcore, .nvptx, - .amdil, .hsail, .spir, .kalimba, @@ -496,7 +495,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target { .aarch64 => copy.cpu.arch = .arm, .aarch64_be => copy.cpu.arch = .armeb, - .amdil64 => copy.cpu.arch = .amdil, .nvptx64 => copy.cpu.arch = .nvptx, .wasm64 => copy.cpu.arch = .wasm32, .hsail64 => copy.cpu.arch = .hsail, @@ -540,7 +538,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target { .amdgcn, .bpfeb, .bpfel, - .amdil64, .nvptx64, .wasm64, .hsail64, @@ -559,7 +556,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target { => {}, // Already 64 bit .aarch64_32 => copy.cpu.arch = .aarch64, - .amdil => copy.cpu.arch = .amdil64, .arm => copy.cpu.arch = .aarch64, .armeb => copy.cpu.arch = .aarch64_be, .hsail => copy.cpu.arch = .hsail64, @@ -631,8 +627,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 { .xtensa => "xtensa", .nvptx => "nvptx", .nvptx64 => "nvptx64", - .amdil => "amdil", - .amdil64 => "amdil64", .hsail => "hsail", .hsail64 => "hsail64", .spir => "spir", diff --git a/lib/std/Target.zig b/lib/std/Target.zig index d281bcf6dbeebaed0ba76aba24de2a2c680cb7e0..fedd339b3d6e7a4b087081fd4e5e1191189ed9b6 100644 --- a/lib/std/Target.zig +++ b/lib/std/Target.zig @@ -1011,8 +1011,6 @@ pub const Cpu = struct { xtensa, nvptx, nvptx64, - amdil, - amdil64, hsail, hsail64, spir, @@ -1156,7 +1154,6 @@ pub const Cpu = struct { .xcore => .XCORE, .xtensa => .XTENSA, .nvptx => .NONE, - .amdil => .NONE, .hsail => .NONE, .spir => .NONE, .kalimba => .CSR_KALIMBA, @@ -1173,7 +1170,6 @@ pub const Cpu = struct { .riscv64 => .RISCV, .x86_64 => .X86_64, .nvptx64 => .NONE, - .amdil64 => .NONE, .hsail64 => .NONE, .spir64 => .NONE, .wasm64 => .NONE, @@ -1217,7 +1213,6 @@ pub const Cpu = struct { .xcore => .Unknown, .xtensa => .Unknown, .nvptx => .Unknown, - .amdil => .Unknown, .hsail => .Unknown, .spir => .Unknown, .kalimba => .Unknown, @@ -1234,7 +1229,6 @@ pub const Cpu = struct { .riscv64 => .RISCV64, .x86_64 => .X64, .nvptx64 => .Unknown, - .amdil64 => .Unknown, .hsail64 => .Unknown, .spir64 => .Unknown, .wasm64 => .Unknown, @@ -1261,8 +1255,6 @@ pub const Cpu = struct { .aarch64_32, .aarch64, .amdgcn, - .amdil, - .amdil64, .bpfel, .csky, .xtensa, @@ -1772,8 +1764,6 @@ pub const DynamicLinker = struct { .tce, .tcele, .xcore, - .amdil, - .amdil64, .hsail, .hsail64, .spir, @@ -1878,7 +1868,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 { .x86, .xcore, .nvptx, - .amdil, .hsail, .spir, .kalimba, @@ -1901,7 +1890,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 { .riscv64, .x86_64, .nvptx64, - .amdil64, .hsail64, .spir64, .wasm64, @@ -2402,7 +2390,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 { .loongarch32, .tce, .tcele, - .amdil, .hsail, .spir, .spirv32, @@ -2415,7 +2402,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 { .aarch64_32, .amdgcn, - .amdil64, .bpfel, .bpfeb, .hexagon, @@ -2518,7 +2504,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 { .loongarch32, .tce, .tcele, - .amdil, .hsail, .spir, .spirv32, @@ -2537,7 +2522,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 { .thumbeb, .aarch64_32, .amdgcn, - .amdil64, .bpfel, .bpfeb, .hexagon, diff --git a/src/Type.zig b/src/Type.zig index bfe9a94d33b7c793010b4c053f13614ec6e44b84..093bd2cbbe621331b30759efa0a124266c62fb46 100644 --- a/src/Type.zig +++ b/src/Type.zig @@ -1650,14 +1650,12 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 { .m68k, .tce, .tcele, - .amdil, .hsail, .spir, .kalimba, .spirv, .spirv32, .shave, - .amdil64, .hsail64, .spir64, .ve, diff --git a/src/Zcu.zig b/src/Zcu.zig index dbece763ec27461ad159886d220700e232cc74ab..b3b93507f4d57f7dc5af533c0da707dcc34c407b 100644 --- a/src/Zcu.zig +++ b/src/Zcu.zig @@ -3255,7 +3255,6 @@ pub fn atomicPtrAlignment( .thumbeb, .x86, .xcore, - .amdil, .hsail, .spir, .kalimba, @@ -3280,7 +3279,6 @@ pub fn atomicPtrAlignment( .riscv64, .sparc64, .s390x, - .amdil64, .hsail64, .spir64, .wasm64, diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig index b56ca01484b96c9249e5f377f70c224ded922c47..a4c417c6e678440880f64db21047de2901929a86 100644 --- a/src/codegen/llvm.zig +++ b/src/codegen/llvm.zig @@ -82,8 +82,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 { .xtensa => "xtensa", .nvptx => "nvptx", .nvptx64 => "nvptx64", - .amdil => "amdil", - .amdil64 => "amdil64", .hsail => "hsail", .hsail64 => "hsail64", .spir => "spir", @@ -303,8 +301,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType { .xtensa => .xtensa, .nvptx => .nvptx, .nvptx64 => .nvptx64, - .amdil => .amdil, - .amdil64 => .amdil64, .hsail => .hsail, .hsail64 => .hsail64, .spir => .spir, @@ -12088,8 +12084,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void { // LLVM backends that have no initialization functions. .tce, .tcele, - .amdil, - .amdil64, .hsail, .hsail64, .shave, diff --git a/src/target.zig b/src/target.zig index 19b8320cd829c0e6962134385c703da232b68f3a..3e213df4f606f7428323d9d061828b462e8da860 100644 --- a/src/target.zig +++ b/src/target.zig @@ -152,8 +152,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool { .xtensa, .nvptx, .nvptx64, - .amdil, - .amdil64, .hsail, .hsail64, .spir, -- 2.54.0 From f1e0c35db4167b8cc5a70d2270028287e737fff4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= Date: Sun, 21 Jul 2024 14:10:07 +0200 Subject: [PATCH 4/8] std.Target: Remove `hsail`/`hsail64` arch tags. This seems to just be dead. See: https://github.com/search?q=repo%3Allvm%2Fllvm-project%20hsail&type=code See: https://github.com/HSAFoundation/HSAIL-Tools/commits/master --- lib/compiler/aro/aro/target.zig | 6 ------ lib/std/Target.zig | 16 ---------------- src/Type.zig | 2 -- src/Zcu.zig | 2 -- src/codegen/llvm.zig | 6 ------ src/target.zig | 2 -- 6 files changed, 34 deletions(-) diff --git a/lib/compiler/aro/aro/target.zig b/lib/compiler/aro/aro/target.zig index 8d51fbabfd3590d7cb7e788e8cb4d8d02133aa6f..82dc3af430499ab9c69dfb5de425724283e53734 100644 --- a/lib/compiler/aro/aro/target.zig +++ b/lib/compiler/aro/aro/target.zig @@ -480,7 +480,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target { .x86, .xcore, .nvptx, - .hsail, .spir, .kalimba, .shave, @@ -497,7 +496,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target { .aarch64_be => copy.cpu.arch = .armeb, .nvptx64 => copy.cpu.arch = .nvptx, .wasm64 => copy.cpu.arch = .wasm32, - .hsail64 => copy.cpu.arch = .hsail, .spir64 => copy.cpu.arch = .spir, .spirv64 => copy.cpu.arch = .spirv32, .loongarch64 => copy.cpu.arch = .loongarch32, @@ -540,7 +538,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target { .bpfel, .nvptx64, .wasm64, - .hsail64, .spir64, .spirv64, .loongarch64, @@ -558,7 +555,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target { .aarch64_32 => copy.cpu.arch = .aarch64, .arm => copy.cpu.arch = .aarch64, .armeb => copy.cpu.arch = .aarch64_be, - .hsail => copy.cpu.arch = .hsail64, .loongarch32 => copy.cpu.arch = .loongarch64, .mips => copy.cpu.arch = .mips64, .mipsel => copy.cpu.arch = .mips64el, @@ -627,8 +623,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 { .xtensa => "xtensa", .nvptx => "nvptx", .nvptx64 => "nvptx64", - .hsail => "hsail", - .hsail64 => "hsail64", .spir => "spir", .spir64 => "spir64", .spirv32 => "spirv32", diff --git a/lib/std/Target.zig b/lib/std/Target.zig index fedd339b3d6e7a4b087081fd4e5e1191189ed9b6..c69a730b2e32624a213d4a7dbfa0bd58243b1d08 100644 --- a/lib/std/Target.zig +++ b/lib/std/Target.zig @@ -1011,8 +1011,6 @@ pub const Cpu = struct { xtensa, nvptx, nvptx64, - hsail, - hsail64, spir, spir64, spirv, @@ -1154,7 +1152,6 @@ pub const Cpu = struct { .xcore => .XCORE, .xtensa => .XTENSA, .nvptx => .NONE, - .hsail => .NONE, .spir => .NONE, .kalimba => .CSR_KALIMBA, .shave => .NONE, @@ -1170,7 +1167,6 @@ pub const Cpu = struct { .riscv64 => .RISCV, .x86_64 => .X86_64, .nvptx64 => .NONE, - .hsail64 => .NONE, .spir64 => .NONE, .wasm64 => .NONE, .amdgcn => .AMDGPU, @@ -1213,7 +1209,6 @@ pub const Cpu = struct { .xcore => .Unknown, .xtensa => .Unknown, .nvptx => .Unknown, - .hsail => .Unknown, .spir => .Unknown, .kalimba => .Unknown, .shave => .Unknown, @@ -1229,7 +1224,6 @@ pub const Cpu = struct { .riscv64 => .RISCV64, .x86_64 => .X64, .nvptx64 => .Unknown, - .hsail64 => .Unknown, .spir64 => .Unknown, .wasm64 => .Unknown, .amdgcn => .Unknown, @@ -1259,8 +1253,6 @@ pub const Cpu = struct { .csky, .xtensa, .hexagon, - .hsail, - .hsail64, .kalimba, .mipsel, .mips64el, @@ -1764,8 +1756,6 @@ pub const DynamicLinker = struct { .tce, .tcele, .xcore, - .hsail, - .hsail64, .spir, .spir64, .kalimba, @@ -1868,7 +1858,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 { .x86, .xcore, .nvptx, - .hsail, .spir, .kalimba, .shave, @@ -1890,7 +1879,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 { .riscv64, .x86_64, .nvptx64, - .hsail64, .spir64, .wasm64, .amdgcn, @@ -2390,7 +2378,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 { .loongarch32, .tce, .tcele, - .hsail, .spir, .spirv32, .kalimba, @@ -2405,7 +2392,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 { .bpfel, .bpfeb, .hexagon, - .hsail64, .loongarch64, .m68k, .mips, @@ -2504,7 +2490,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 { .loongarch32, .tce, .tcele, - .hsail, .spir, .spirv32, .kalimba, @@ -2525,7 +2510,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 { .bpfel, .bpfeb, .hexagon, - .hsail64, .x86, .loongarch64, .m68k, diff --git a/src/Type.zig b/src/Type.zig index 093bd2cbbe621331b30759efa0a124266c62fb46..411e2426289449e5262bf774a3b231bdb03060c3 100644 --- a/src/Type.zig +++ b/src/Type.zig @@ -1650,13 +1650,11 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 { .m68k, .tce, .tcele, - .hsail, .spir, .kalimba, .spirv, .spirv32, .shave, - .hsail64, .spir64, .ve, .spirv64, diff --git a/src/Zcu.zig b/src/Zcu.zig index b3b93507f4d57f7dc5af533c0da707dcc34c407b..8d1d2a5130dd3076da0edeef1dd2e86ad636aaac 100644 --- a/src/Zcu.zig +++ b/src/Zcu.zig @@ -3255,7 +3255,6 @@ pub fn atomicPtrAlignment( .thumbeb, .x86, .xcore, - .hsail, .spir, .kalimba, .lanai, @@ -3279,7 +3278,6 @@ pub fn atomicPtrAlignment( .riscv64, .sparc64, .s390x, - .hsail64, .spir64, .wasm64, .ve, diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig index a4c417c6e678440880f64db21047de2901929a86..90a5d4bf62e1815e58d613626c2f78b25dbf00c3 100644 --- a/src/codegen/llvm.zig +++ b/src/codegen/llvm.zig @@ -82,8 +82,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 { .xtensa => "xtensa", .nvptx => "nvptx", .nvptx64 => "nvptx64", - .hsail => "hsail", - .hsail64 => "hsail64", .spir => "spir", .spir64 => "spir64", .spirv => "spirv", @@ -301,8 +299,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType { .xtensa => .xtensa, .nvptx => .nvptx, .nvptx64 => .nvptx64, - .hsail => .hsail, - .hsail64 => .hsail64, .spir => .spir, .spir64 => .spir64, .spirv => .spirv, @@ -12084,8 +12080,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void { // LLVM backends that have no initialization functions. .tce, .tcele, - .hsail, - .hsail64, .shave, .spir, .spir64, diff --git a/src/target.zig b/src/target.zig index 3e213df4f606f7428323d9d061828b462e8da860..dce8cab7b499b556685fa82aef4f6080ab9ad3fe 100644 --- a/src/target.zig +++ b/src/target.zig @@ -152,8 +152,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool { .xtensa, .nvptx, .nvptx64, - .hsail, - .hsail64, .spir, .spir64, .spirv, -- 2.54.0 From 21cc5a20440e41a0f8b53b5eeac4ba5da55b64bf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= Date: Sun, 21 Jul 2024 14:13:37 +0200 Subject: [PATCH 5/8] std.Target: Remove the `shave` arch tag. This was added as an architecture to LLVM's target triple parser and the Clang driver in 2015. No backend ever materialized as far as I can see (same for GCC). In 2016, other code referring to it started using "Myriad" instead. Ultimately, all code related to it that isn't in the target triple parser was removed. It seems to be a real product, just... literally no one seems to know anything about the ISA. I figure after almost a decade with no public ISA documentation to speak of, and no LLVM backend to reference, it's probably safe to assume that we're not going to learn much about this ISA, making it useless for Zig. See: https://github.com/llvm/llvm-project/commit/1b5767f72b5a037ca8f1802d737de97f8d92263d See: https://github.com/llvm/llvm-project/commit/84a7564b28360843ee9afec5d3823c89623eb6a5 See: https://github.com/llvm/llvm-project/commit/8cfe9d8f2ad3a52ba7fd5841d3939aa810536e16 --- lib/compiler/aro/aro/target.zig | 3 --- lib/std/Target.zig | 8 -------- src/Type.zig | 1 - src/Zcu.zig | 1 - src/codegen/llvm.zig | 3 --- src/target.zig | 1 - 6 files changed, 17 deletions(-) diff --git a/lib/compiler/aro/aro/target.zig b/lib/compiler/aro/aro/target.zig index 82dc3af430499ab9c69dfb5de425724283e53734..ed729c14565b2457b558db97c897237133d872ad 100644 --- a/lib/compiler/aro/aro/target.zig +++ b/lib/compiler/aro/aro/target.zig @@ -482,7 +482,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target { .nvptx, .spir, .kalimba, - .shave, .lanai, .wasm32, .aarch64_32, @@ -522,7 +521,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target { .lanai, .m68k, .msp430, - .shave, .sparcel, .spu_2, .tce, @@ -628,7 +626,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 { .spirv32 => "spirv32", .spirv64 => "spirv64", .kalimba => "kalimba", - .shave => "shave", .lanai => "lanai", .wasm32 => "wasm32", .wasm64 => "wasm64", diff --git a/lib/std/Target.zig b/lib/std/Target.zig index c69a730b2e32624a213d4a7dbfa0bd58243b1d08..a545f0d038cfff36531384c90c69f36df469964f 100644 --- a/lib/std/Target.zig +++ b/lib/std/Target.zig @@ -1017,7 +1017,6 @@ pub const Cpu = struct { spirv32, spirv64, kalimba, - shave, lanai, wasm32, wasm64, @@ -1154,7 +1153,6 @@ pub const Cpu = struct { .nvptx => .NONE, .spir => .NONE, .kalimba => .CSR_KALIMBA, - .shave => .NONE, .lanai => .LANAI, .wasm32 => .NONE, .aarch64_32 => .AARCH64, @@ -1211,7 +1209,6 @@ pub const Cpu = struct { .nvptx => .Unknown, .spir => .Unknown, .kalimba => .Unknown, - .shave => .Unknown, .lanai => .Unknown, .wasm32 => .Unknown, .aarch64_32 => .ARM64, @@ -1273,7 +1270,6 @@ pub const Cpu = struct { .thumb, .spir, .spir64, - .shave, .ve, .spu_2, // GPU bitness is opaque. For now, assume little endian. @@ -1759,7 +1755,6 @@ pub const DynamicLinker = struct { .spir, .spir64, .kalimba, - .shave, .lanai, .ve, .dxil, @@ -1860,7 +1855,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 { .nvptx, .spir, .kalimba, - .shave, .lanai, .wasm32, .aarch64_32, @@ -2381,7 +2375,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 { .spir, .spirv32, .kalimba, - .shave, .ve, .spu_2, .xtensa, @@ -2493,7 +2486,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 { .spir, .spirv32, .kalimba, - .shave, .ve, .spu_2, .xtensa, diff --git a/src/Type.zig b/src/Type.zig index 411e2426289449e5262bf774a3b231bdb03060c3..1428d6c15f062f67164e8f73bd2f82603ff118cd 100644 --- a/src/Type.zig +++ b/src/Type.zig @@ -1654,7 +1654,6 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 { .kalimba, .spirv, .spirv32, - .shave, .spir64, .ve, .spirv64, diff --git a/src/Zcu.zig b/src/Zcu.zig index 8d1d2a5130dd3076da0edeef1dd2e86ad636aaac..825da89b147c7ccd4b1847f909f8934d7eca3263 100644 --- a/src/Zcu.zig +++ b/src/Zcu.zig @@ -3258,7 +3258,6 @@ pub fn atomicPtrAlignment( .spir, .kalimba, .lanai, - .shave, .wasm32, .csky, .spirv32, diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig index 90a5d4bf62e1815e58d613626c2f78b25dbf00c3..802141892a4ed247facb0010792b82638ec50eb8 100644 --- a/src/codegen/llvm.zig +++ b/src/codegen/llvm.zig @@ -88,7 +88,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 { .spirv32 => "spirv32", .spirv64 => "spirv64", .kalimba => "kalimba", - .shave => "shave", .lanai => "lanai", .wasm32 => "wasm32", .wasm64 => "wasm64", @@ -305,7 +304,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType { .spirv32 => .spirv32, .spirv64 => .spirv64, .kalimba => .kalimba, - .shave => .shave, .lanai => .lanai, .wasm32 => .wasm32, .wasm64 => .wasm64, @@ -12080,7 +12078,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void { // LLVM backends that have no initialization functions. .tce, .tcele, - .shave, .spir, .spir64, .spirv, diff --git a/src/target.zig b/src/target.zig index dce8cab7b499b556685fa82aef4f6080ab9ad3fe..89e6069e216ad751a10370f4eff3c33e66bc9a49 100644 --- a/src/target.zig +++ b/src/target.zig @@ -158,7 +158,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool { .spirv32, .spirv64, .kalimba, - .shave, .lanai, .wasm32, .wasm64, -- 2.54.0 From db8bc4770c37470e8807c21571d483e3a73f9f69 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= Date: Sun, 21 Jul 2024 14:17:51 +0200 Subject: [PATCH 6/8] std.Target: Remove the `tce`/`tcele` arch tags. There is no obvious reason why this would be relevant for Zig to target. I rather question the value of LLVM even having target triple code for this, too. See: https://blog.llvm.org/2010/06/tce-project-co-design-of-application.html See: https://github.com/cpc/llvmtce --- lib/compiler/aro/aro/target.zig | 12 +----------- lib/std/Target.zig | 28 ---------------------------- src/Type.zig | 2 -- src/Zcu.zig | 2 -- src/codegen/llvm.zig | 6 ------ src/target.zig | 2 -- 6 files changed, 1 insertion(+), 51 deletions(-) diff --git a/lib/compiler/aro/aro/target.zig b/lib/compiler/aro/aro/target.zig index ed729c14565b2457b558db97c897237133d872ad..c822d8d9505d6480f0b6acbcc6cb62cecbeab62b 100644 --- a/lib/compiler/aro/aro/target.zig +++ b/lib/compiler/aro/aro/target.zig @@ -17,8 +17,6 @@ pub fn intMaxType(target: std.Target) Type { .riscv64, .powerpc64, .powerpc64le, - .tce, - .tcele, .ve, => return .{ .specifier = .long }, @@ -54,8 +52,6 @@ pub fn intPtrType(target: std.Target) Type { .riscv32, .xcore, .hexagon, - .tce, - .tcele, .m68k, .spir, .spirv32, @@ -153,7 +149,7 @@ pub fn isTlsSupported(target: std.Target) bool { return supported; } return switch (target.cpu.arch) { - .tce, .tcele, .bpfel, .bpfeb, .msp430, .nvptx, .nvptx64, .x86, .arm, .armeb, .thumb, .thumbeb => false, + .bpfel, .bpfeb, .msp430, .nvptx, .nvptx64, .x86, .arm, .armeb, .thumb, .thumbeb => false, else => true, }; } @@ -473,8 +469,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target { .riscv32, .sparc, .sparcel, - .tce, - .tcele, .thumb, .thumbeb, .x86, @@ -523,8 +517,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target { .msp430, .sparcel, .spu_2, - .tce, - .tcele, .xcore, .xtensa, => return null, @@ -611,8 +603,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 { .sparc64 => "sparc64", .sparcel => "sparcel", .s390x => "s390x", - .tce => "tce", - .tcele => "tcele", .thumb => "thumb", .thumbeb => "thumbeb", .x86 => "i386", diff --git a/lib/std/Target.zig b/lib/std/Target.zig index a545f0d038cfff36531384c90c69f36df469964f..00540505ddadceae204fc34ec81a6d3f59334ac6 100644 --- a/lib/std/Target.zig +++ b/lib/std/Target.zig @@ -1001,8 +1001,6 @@ pub const Cpu = struct { sparc64, sparcel, s390x, - tce, - tcele, thumb, thumbeb, x86, @@ -1143,8 +1141,6 @@ pub const Cpu = struct { .riscv32 => .RISCV, .sparc => .SPARC, .sparcel => .SPARC, - .tce => .NONE, - .tcele => .NONE, .thumb => .ARM, .thumbeb => .ARM, .x86 => .@"386", @@ -1199,8 +1195,6 @@ pub const Cpu = struct { .riscv32 => .RISCV32, .sparc => .Unknown, .sparcel => .Unknown, - .tce => .Unknown, - .tcele => .Unknown, .thumb => .Thumb, .thumbeb => .Thumb, .x86 => .I386, @@ -1257,7 +1251,6 @@ pub const Cpu = struct { .nvptx, .nvptx64, .sparcel, - .tcele, .powerpcle, .powerpc64le, .riscv32, @@ -1293,7 +1286,6 @@ pub const Cpu = struct { .thumbeb, .sparc, .sparc64, - .tce, .lanai, .s390x, => .big, @@ -1749,8 +1741,6 @@ pub const DynamicLinker = struct { .m68k, .msp430, .amdgcn, - .tce, - .tcele, .xcore, .spir, .spir64, @@ -1846,8 +1836,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 { .powerpcle, .riscv32, .sparcel, - .tce, - .tcele, .thumb, .thumbeb, .x86, @@ -2022,12 +2010,6 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 { .long, .ulong, .float, .double, .longdouble => return 32, .longlong, .ulonglong => return 64, }, - .tce, .tcele => switch (c_type) { - .char => return 8, - .short, .ushort => return 16, - .int, .uint, .long, .ulong, .longlong, .ulonglong => return 32, - .float, .double, .longdouble => return 32, - }, .mips64, .mips64el => switch (c_type) { .char => return 8, .short, .ushort => return 16, @@ -2117,12 +2099,6 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 { .long, .ulong, .float, .double, .longdouble => return 32, .longlong, .ulonglong => return 64, }, - .tce, .tcele => switch (c_type) { - .char => return 8, - .short, .ushort => return 16, - .int, .uint, .long, .ulong, .longlong, .ulonglong => return 32, - .float, .double, .longdouble => return 32, - }, .mips64, .mips64el => switch (c_type) { .char => return 8, .short, .ushort => return 16, @@ -2370,8 +2346,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 { .xcore, .dxil, .loongarch32, - .tce, - .tcele, .spir, .spirv32, .kalimba, @@ -2481,8 +2455,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 { .xcore, .dxil, .loongarch32, - .tce, - .tcele, .spir, .spirv32, .kalimba, diff --git a/src/Type.zig b/src/Type.zig index 1428d6c15f062f67164e8f73bd2f82603ff118cd..d3c086477170ec875446f340030953a99ff7de9f 100644 --- a/src/Type.zig +++ b/src/Type.zig @@ -1648,8 +1648,6 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 { .csky, .arc, .m68k, - .tce, - .tcele, .spir, .kalimba, .spirv, diff --git a/src/Zcu.zig b/src/Zcu.zig index 825da89b147c7ccd4b1847f909f8934d7eca3263..3396728eddf248ccbf9ca210b7d81c0ca0abf38e 100644 --- a/src/Zcu.zig +++ b/src/Zcu.zig @@ -3249,8 +3249,6 @@ pub fn atomicPtrAlignment( .riscv32, .sparc, .sparcel, - .tce, - .tcele, .thumb, .thumbeb, .x86, diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig index 802141892a4ed247facb0010792b82638ec50eb8..5185ec3ff3e56c135758c97f1378c0705ec89c7b 100644 --- a/src/codegen/llvm.zig +++ b/src/codegen/llvm.zig @@ -72,8 +72,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 { .sparc64 => "sparc64", .sparcel => "sparcel", .s390x => "s390x", - .tce => "tce", - .tcele => "tcele", .thumb => "thumb", .thumbeb => "thumbeb", .x86 => "i386", @@ -288,8 +286,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType { .sparc64 => .sparcv9, // In LLVM, sparc64 == sparcv9. .sparcel => .sparcel, .s390x => .systemz, - .tce => .tce, - .tcele => .tcele, .thumb => .thumb, .thumbeb => .thumbeb, .x86 => .x86, @@ -12076,8 +12072,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void { }, // LLVM backends that have no initialization functions. - .tce, - .tcele, .spir, .spir64, .spirv, diff --git a/src/target.zig b/src/target.zig index 89e6069e216ad751a10370f4eff3c33e66bc9a49..6ff9e69e614cd3425b567ca23fca57d943ad9aab 100644 --- a/src/target.zig +++ b/src/target.zig @@ -142,8 +142,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool { .sparc64, .sparcel, .s390x, - .tce, - .tcele, .thumb, .thumbeb, .x86, -- 2.54.0 From 84e9aec13f0c0bd5e30286493dfdf9fb7665aaf1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= Date: Sun, 21 Jul 2024 14:33:22 +0200 Subject: [PATCH 7/8] std.Target: Add comments for deliberately omitted/removed LLVM tags. --- lib/std/Target.zig | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/lib/std/Target.zig b/lib/std/Target.zig index 00540505ddadceae204fc34ec81a6d3f59334ac6..55ff3c18fa4e173b3442c76d64e25cbebffada29 100644 --- a/lib/std/Target.zig +++ b/lib/std/Target.zig @@ -63,6 +63,11 @@ pub const Os = struct { illumos, other, + // LLVM tags deliberately omitted: + // - kfreebsd + // - darwin + // - nacl + pub inline fn isDarwin(tag: Tag) bool { return switch (tag) { .ios, .macos, .watchos, .tvos, .visionos => true, @@ -653,6 +658,10 @@ pub const Abi = enum { amplification, ohos, + // LLVM tags deliberately omitted: + // - gnuf64 + // - coreclr + pub fn default(arch: Cpu.Arch, os: Os) Abi { return if (arch.isWasm()) .musl else switch (os.tag) { .freestanding, @@ -1021,6 +1030,18 @@ pub const Cpu = struct { ve, spu_2, + // LLVM tags deliberately omitted: + // - r600 + // - le32 + // - le64 + // - amdil + // - amdil64 + // - hsail + // - hsail64 + // - shave + // - renderscript32 + // - renderscript64 + pub inline fn isX86(arch: Arch) bool { return switch (arch) { .x86, .x86_64 => true, -- 2.54.0 From be9841335e4038798dc40c9b265cd9094336e622 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= Date: Sun, 21 Jul 2024 14:47:14 +0200 Subject: [PATCH 8/8] std.Target.Os: Rename lv2 to ps3. It is very non-obvious that this is what lv2 refers to, and we already use ps4 and ps5 to refer to the later models, so let's just be consistent. --- lib/compiler/aro/aro/target.zig | 2 +- lib/std/Target.zig | 14 +++++++------- src/codegen/llvm.zig | 4 ++-- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/lib/compiler/aro/aro/target.zig b/lib/compiler/aro/aro/target.zig index c822d8d9505d6480f0b6acbcc6cb62cecbeab62b..5541d4f67ec3b61db8f2a345cb629ec627c34f9a 100644 --- a/lib/compiler/aro/aro/target.zig +++ b/lib/compiler/aro/aro/target.zig @@ -634,7 +634,7 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 { .freebsd => "freebsd", .fuchsia => "fuchsia", .linux => "linux", - .lv2 => "lv2", + .ps3 => "lv2", .netbsd => "netbsd", .openbsd => "openbsd", .solaris => "solaris", diff --git a/lib/std/Target.zig b/lib/std/Target.zig index 55ff3c18fa4e173b3442c76d64e25cbebffada29..41e754d2fb50243c4fbad11d1699de20f796fee9 100644 --- a/lib/std/Target.zig +++ b/lib/std/Target.zig @@ -24,7 +24,7 @@ pub const Os = struct { fuchsia, ios, linux, - lv2, + ps3, macos, netbsd, openbsd, @@ -143,7 +143,7 @@ pub const Os = struct { .ananas, .cloudabi, .fuchsia, - .lv2, + .ps3, .zos, .haiku, .minix, @@ -375,7 +375,7 @@ pub const Os = struct { .ananas, .cloudabi, .fuchsia, - .lv2, + .ps3, .zos, .haiku, .minix, @@ -562,7 +562,7 @@ pub const Os = struct { .ananas, .cloudabi, .fuchsia, - .lv2, + .ps3, .zos, .minix, .rtems, @@ -668,7 +668,7 @@ pub const Abi = enum { .ananas, .cloudabi, .dragonfly, - .lv2, + .ps3, .zos, .minix, .rtems, @@ -1805,7 +1805,7 @@ pub const DynamicLinker = struct { .ananas, .cloudabi, .fuchsia, - .lv2, + .ps3, .zos, .minix, .rtems, @@ -2300,7 +2300,7 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 { }, .cloudabi, - .lv2, + .ps3, .zos, .rtems, .aix, diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig index 5185ec3ff3e56c135758c97f1378c0705ec89c7b..58e71c7eda3fac0e52bf70ad3da5ccd9fc45a1a0 100644 --- a/src/codegen/llvm.zig +++ b/src/codegen/llvm.zig @@ -101,7 +101,7 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 { .freebsd => "freebsd", .fuchsia => "fuchsia", .linux => "linux", - .lv2 => "lv2", + .ps3 => "lv2", .netbsd => "netbsd", .openbsd => "openbsd", .solaris, .illumos => "solaris", @@ -221,7 +221,7 @@ pub fn targetOs(os_tag: std.Target.Os.Tag) llvm.OSType { .fuchsia => .Fuchsia, .ios => .IOS, .linux => .Linux, - .lv2 => .Lv2, + .ps3 => .Lv2, .macos => .MacOSX, .netbsd => .NetBSD, .openbsd => .OpenBSD, -- 2.54.0