authorgravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2023-05-08 07:35:31-04:00
committergravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2023-05-08 07:36:20-04:00
log1f5aa7747f5710e281cd2190508ce562a4bfd35f
treeff832710e67a7ac1256ed0ced050db411fd23551
parentecb5feaf94bf49dc4c180f09c170223d6c1898b3

x86_64: finish optimizing mir tag usage

Final tag count is 95.

2 files changed, 266 insertions(+), 466 deletions(-)

src/arch/x86_64/CodeGen.zig+184-184
...@@ -2443,7 +2443,7 @@ fn airFptrunc(self: *Self, inst: Air.Inst.Index) !void {...@@ -2443,7 +2443,7 @@ fn airFptrunc(self: *Self, inst: Air.Inst.Index) !void {
2443 else2443 else
2444 try self.copyToTmpRegister(src_ty, src_mcv);2444 try self.copyToTmpRegister(src_ty, src_mcv);
2445 try self.asmRegisterRegisterImmediate(2445 try self.asmRegisterRegisterImmediate(
2446 .{ ._, .vcvtps2ph },2446 .{ .v_, .cvtps2ph },
2447 dst_reg,2447 dst_reg,
2448 mat_src_reg.to128(),2448 mat_src_reg.to128(),
2449 Immediate.u(0b1_00),2449 Immediate.u(0b1_00),
...@@ -2455,12 +2455,12 @@ fn airFptrunc(self: *Self, inst: Air.Inst.Index) !void {...@@ -2455,12 +2455,12 @@ fn airFptrunc(self: *Self, inst: Air.Inst.Index) !void {
2455 }2455 }
2456 } else if (src_bits == 64 and dst_bits == 32) {2456 } else if (src_bits == 64 and dst_bits == 32) {
2457 if (self.hasFeature(.avx)) if (src_mcv.isMemory()) try self.asmRegisterRegisterMemory(2457 if (self.hasFeature(.avx)) if (src_mcv.isMemory()) try self.asmRegisterRegisterMemory(
2458 .{ ._, .vcvtsd2ss },2458 .{ .v_, .cvtsd2ss },
2459 dst_reg,2459 dst_reg,
2460 dst_reg,2460 dst_reg,
2461 src_mcv.mem(.qword),2461 src_mcv.mem(.qword),
2462 ) else try self.asmRegisterRegisterRegister(2462 ) else try self.asmRegisterRegisterRegister(
2463 .{ ._, .vcvtsd2ss },2463 .{ .v_, .cvtsd2ss },
2464 dst_reg,2464 dst_reg,
2465 dst_reg,2465 dst_reg,
2466 (if (src_mcv.isRegister())2466 (if (src_mcv.isRegister())
...@@ -2506,22 +2506,22 @@ fn airFpext(self: *Self, inst: Air.Inst.Index) !void {...@@ -2506,22 +2506,22 @@ fn airFpext(self: *Self, inst: Air.Inst.Index) !void {
2506 src_mcv.getReg().?2506 src_mcv.getReg().?
2507 else2507 else
2508 try self.copyToTmpRegister(src_ty, src_mcv);2508 try self.copyToTmpRegister(src_ty, src_mcv);
2509 try self.asmRegisterRegister(.{ ._, .vcvtph2ps }, dst_reg, mat_src_reg.to128());2509 try self.asmRegisterRegister(.{ .v_, .cvtph2ps }, dst_reg, mat_src_reg.to128());
2510 switch (dst_bits) {2510 switch (dst_bits) {
2511 32 => {},2511 32 => {},
2512 64 => try self.asmRegisterRegisterRegister(.{ ._, .vcvtss2sd }, dst_reg, dst_reg, dst_reg),2512 64 => try self.asmRegisterRegisterRegister(.{ .v_, .cvtss2sd }, dst_reg, dst_reg, dst_reg),
2513 else => return self.fail("TODO implement airFpext from {} to {}", .{2513 else => return self.fail("TODO implement airFpext from {} to {}", .{
2514 src_ty.fmt(self.bin_file.options.module.?), dst_ty.fmt(self.bin_file.options.module.?),2514 src_ty.fmt(self.bin_file.options.module.?), dst_ty.fmt(self.bin_file.options.module.?),
2515 }),2515 }),
2516 }2516 }
2517 } else if (src_bits == 32 and dst_bits == 64) {2517 } else if (src_bits == 32 and dst_bits == 64) {
2518 if (self.hasFeature(.avx)) if (src_mcv.isMemory()) try self.asmRegisterRegisterMemory(2518 if (self.hasFeature(.avx)) if (src_mcv.isMemory()) try self.asmRegisterRegisterMemory(
2519 .{ ._, .vcvtss2sd },2519 .{ .v_, .cvtss2sd },
2520 dst_reg,2520 dst_reg,
2521 dst_reg,2521 dst_reg,
2522 src_mcv.mem(.dword),2522 src_mcv.mem(.dword),
2523 ) else try self.asmRegisterRegisterRegister(2523 ) else try self.asmRegisterRegisterRegister(
2524 .{ ._, .vcvtss2sd },2524 .{ .v_, .cvtss2sd },
2525 dst_reg,2525 dst_reg,
2526 dst_reg,2526 dst_reg,
2527 (if (src_mcv.isRegister())2527 (if (src_mcv.isRegister())
...@@ -4678,8 +4678,8 @@ fn airFloatSign(self: *Self, inst: Air.Inst.Index) !void {...@@ -4678,8 +4678,8 @@ fn airFloatSign(self: *Self, inst: Air.Inst.Index) !void {
4678 try self.genBinOpMir(switch (ty_bits) {4678 try self.genBinOpMir(switch (ty_bits) {
4679 // No point using an extra prefix byte for *pd which performs the same operation.4679 // No point using an extra prefix byte for *pd which performs the same operation.
4680 16, 32, 64, 128 => switch (tag) {4680 16, 32, 64, 128 => switch (tag) {
4681 .neg => .{ ._, .xorps },4681 .neg => .{ ._ps, .xor },
4682 .fabs => .{ ._, .andnps },4682 .fabs => .{ ._ps, .andn },
4683 else => unreachable,4683 else => unreachable,
4684 },4684 },
4685 80 => return self.fail("TODO implement airFloatSign for {}", .{4685 80 => return self.fail("TODO implement airFloatSign for {}", .{
...@@ -4712,23 +4712,23 @@ fn genRound(self: *Self, ty: Type, dst_reg: Register, src_mcv: MCValue, mode: u4...@@ -4712,23 +4712,23 @@ fn genRound(self: *Self, ty: Type, dst_reg: Register, src_mcv: MCValue, mode: u4
47124712
4713 const mir_tag = if (@as(?Mir.Inst.FixedTag, switch (ty.zigTypeTag()) {4713 const mir_tag = if (@as(?Mir.Inst.FixedTag, switch (ty.zigTypeTag()) {
4714 .Float => switch (ty.floatBits(self.target.*)) {4714 .Float => switch (ty.floatBits(self.target.*)) {
4715 32 => if (self.hasFeature(.avx)) .{ ._, .vroundss } else .{ ._, .roundss },4715 32 => if (self.hasFeature(.avx)) .{ .v_ss, .round } else .{ ._ss, .round },
4716 64 => if (self.hasFeature(.avx)) .{ ._, .vroundsd } else .{ ._, .roundsd },4716 64 => if (self.hasFeature(.avx)) .{ .v_sd, .round } else .{ ._sd, .round },
4717 16, 80, 128 => null,4717 16, 80, 128 => null,
4718 else => unreachable,4718 else => unreachable,
4719 },4719 },
4720 .Vector => switch (ty.childType().zigTypeTag()) {4720 .Vector => switch (ty.childType().zigTypeTag()) {
4721 .Float => switch (ty.childType().floatBits(self.target.*)) {4721 .Float => switch (ty.childType().floatBits(self.target.*)) {
4722 32 => switch (ty.vectorLen()) {4722 32 => switch (ty.vectorLen()) {
4723 1 => if (self.hasFeature(.avx)) .{ ._, .vroundss } else .{ ._, .roundss },4723 1 => if (self.hasFeature(.avx)) .{ .v_ss, .round } else .{ ._ss, .round },
4724 2...4 => if (self.hasFeature(.avx)) .{ ._, .vroundps } else .{ ._, .roundps },4724 2...4 => if (self.hasFeature(.avx)) .{ .v_ps, .round } else .{ ._ps, .round },
4725 5...8 => if (self.hasFeature(.avx)) .{ ._, .vroundps } else null,4725 5...8 => if (self.hasFeature(.avx)) .{ .v_ps, .round } else null,
4726 else => null,4726 else => null,
4727 },4727 },
4728 64 => switch (ty.vectorLen()) {4728 64 => switch (ty.vectorLen()) {
4729 1 => if (self.hasFeature(.avx)) .{ ._, .vroundsd } else .{ ._, .roundsd },4729 1 => if (self.hasFeature(.avx)) .{ .v_sd, .round } else .{ ._sd, .round },
4730 2 => if (self.hasFeature(.avx)) .{ ._, .vroundpd } else .{ ._, .roundpd },4730 2 => if (self.hasFeature(.avx)) .{ .v_pd, .round } else .{ ._pd, .round },
4731 3...4 => if (self.hasFeature(.avx)) .{ ._, .vroundpd } else null,4731 3...4 => if (self.hasFeature(.avx)) .{ .v_pd, .round } else null,
4732 else => null,4732 else => null,
4733 },4733 },
4734 16, 80, 128 => null,4734 16, 80, 128 => null,
...@@ -4743,8 +4743,8 @@ fn genRound(self: *Self, ty: Type, dst_reg: Register, src_mcv: MCValue, mode: u4...@@ -4743,8 +4743,8 @@ fn genRound(self: *Self, ty: Type, dst_reg: Register, src_mcv: MCValue, mode: u4
47434743
4744 const abi_size = @intCast(u32, ty.abiSize(self.target.*));4744 const abi_size = @intCast(u32, ty.abiSize(self.target.*));
4745 const dst_alias = registerAlias(dst_reg, abi_size);4745 const dst_alias = registerAlias(dst_reg, abi_size);
4746 switch (mir_tag[1]) {4746 switch (mir_tag[0]) {
4747 .vroundss, .vroundsd => if (src_mcv.isMemory()) try self.asmRegisterRegisterMemoryImmediate(4747 .v_ss, .v_sd => if (src_mcv.isMemory()) try self.asmRegisterRegisterMemoryImmediate(
4748 mir_tag,4748 mir_tag,
4749 dst_alias,4749 dst_alias,
4750 dst_alias,4750 dst_alias,
...@@ -4799,18 +4799,18 @@ fn airSqrt(self: *Self, inst: Air.Inst.Index) !void {...@@ -4799,18 +4799,18 @@ fn airSqrt(self: *Self, inst: Air.Inst.Index) !void {
4799 src_mcv.getReg().?4799 src_mcv.getReg().?
4800 else4800 else
4801 try self.copyToTmpRegister(ty, src_mcv);4801 try self.copyToTmpRegister(ty, src_mcv);
4802 try self.asmRegisterRegister(.{ ._, .vcvtph2ps }, dst_reg, mat_src_reg.to128());4802 try self.asmRegisterRegister(.{ .v_, .cvtph2ps }, dst_reg, mat_src_reg.to128());
4803 try self.asmRegisterRegisterRegister(.{ ._, .vsqrtss }, dst_reg, dst_reg, dst_reg);4803 try self.asmRegisterRegisterRegister(.{ .v_ss, .sqrt }, dst_reg, dst_reg, dst_reg);
4804 try self.asmRegisterRegisterImmediate(4804 try self.asmRegisterRegisterImmediate(
4805 .{ ._, .vcvtps2ph },4805 .{ .v_, .cvtps2ph },
4806 dst_reg,4806 dst_reg,
4807 dst_reg,4807 dst_reg,
4808 Immediate.u(0b1_00),4808 Immediate.u(0b1_00),
4809 );4809 );
4810 break :result dst_mcv;4810 break :result dst_mcv;
4811 } else null,4811 } else null,
4812 32 => if (self.hasFeature(.avx)) .{ ._, .vsqrtss } else .{ ._, .sqrtss },4812 32 => if (self.hasFeature(.avx)) .{ .v_ss, .sqrt } else .{ ._ss, .sqrt },
4813 64 => if (self.hasFeature(.avx)) .{ ._, .vsqrtsd } else .{ ._, .sqrtsd },4813 64 => if (self.hasFeature(.avx)) .{ .v_sd, .sqrt } else .{ ._sd, .sqrt },
4814 80, 128 => null,4814 80, 128 => null,
4815 else => unreachable,4815 else => unreachable,
4816 },4816 },
...@@ -4819,7 +4819,7 @@ fn airSqrt(self: *Self, inst: Air.Inst.Index) !void {...@@ -4819,7 +4819,7 @@ fn airSqrt(self: *Self, inst: Air.Inst.Index) !void {
4819 16 => if (self.hasFeature(.f16c)) switch (ty.vectorLen()) {4819 16 => if (self.hasFeature(.f16c)) switch (ty.vectorLen()) {
4820 1 => {4820 1 => {
4821 try self.asmRegisterRegister(4821 try self.asmRegisterRegister(
4822 .{ ._, .vcvtph2ps },4822 .{ .v_, .cvtph2ps },
4823 dst_reg,4823 dst_reg,
4824 (if (src_mcv.isRegister())4824 (if (src_mcv.isRegister())
4825 src_mcv.getReg().?4825 src_mcv.getReg().?
...@@ -4827,13 +4827,13 @@ fn airSqrt(self: *Self, inst: Air.Inst.Index) !void {...@@ -4827,13 +4827,13 @@ fn airSqrt(self: *Self, inst: Air.Inst.Index) !void {
4827 try self.copyToTmpRegister(ty, src_mcv)).to128(),4827 try self.copyToTmpRegister(ty, src_mcv)).to128(),
4828 );4828 );
4829 try self.asmRegisterRegisterRegister(4829 try self.asmRegisterRegisterRegister(
4830 .{ ._, .vsqrtss },4830 .{ .v_ss, .sqrt },
4831 dst_reg,4831 dst_reg,
4832 dst_reg,4832 dst_reg,
4833 dst_reg,4833 dst_reg,
4834 );4834 );
4835 try self.asmRegisterRegisterImmediate(4835 try self.asmRegisterRegisterImmediate(
4836 .{ ._, .vcvtps2ph },4836 .{ .v_, .cvtps2ph },
4837 dst_reg,4837 dst_reg,
4838 dst_reg,4838 dst_reg,
4839 Immediate.u(0b1_00),4839 Immediate.u(0b1_00),
...@@ -4843,22 +4843,22 @@ fn airSqrt(self: *Self, inst: Air.Inst.Index) !void {...@@ -4843,22 +4843,22 @@ fn airSqrt(self: *Self, inst: Air.Inst.Index) !void {
4843 2...8 => {4843 2...8 => {
4844 const wide_reg = registerAlias(dst_reg, abi_size * 2);4844 const wide_reg = registerAlias(dst_reg, abi_size * 2);
4845 if (src_mcv.isMemory()) try self.asmRegisterMemory(4845 if (src_mcv.isMemory()) try self.asmRegisterMemory(
4846 .{ ._, .vcvtph2ps },4846 .{ .v_, .cvtph2ps },
4847 wide_reg,4847 wide_reg,
4848 src_mcv.mem(Memory.PtrSize.fromSize(4848 src_mcv.mem(Memory.PtrSize.fromSize(
4849 @intCast(u32, @divExact(wide_reg.bitSize(), 16)),4849 @intCast(u32, @divExact(wide_reg.bitSize(), 16)),
4850 )),4850 )),
4851 ) else try self.asmRegisterRegister(4851 ) else try self.asmRegisterRegister(
4852 .{ ._, .vcvtph2ps },4852 .{ .v_, .cvtph2ps },
4853 wide_reg,4853 wide_reg,
4854 (if (src_mcv.isRegister())4854 (if (src_mcv.isRegister())
4855 src_mcv.getReg().?4855 src_mcv.getReg().?
4856 else4856 else
4857 try self.copyToTmpRegister(ty, src_mcv)).to128(),4857 try self.copyToTmpRegister(ty, src_mcv)).to128(),
4858 );4858 );
4859 try self.asmRegisterRegister(.{ ._, .vsqrtps }, wide_reg, wide_reg);4859 try self.asmRegisterRegister(.{ .v_ps, .sqrt }, wide_reg, wide_reg);
4860 try self.asmRegisterRegisterImmediate(4860 try self.asmRegisterRegisterImmediate(
4861 .{ ._, .vcvtps2ph },4861 .{ .v_, .cvtps2ph },
4862 dst_reg,4862 dst_reg,
4863 wide_reg,4863 wide_reg,
4864 Immediate.u(0b1_00),4864 Immediate.u(0b1_00),
...@@ -4868,15 +4868,15 @@ fn airSqrt(self: *Self, inst: Air.Inst.Index) !void {...@@ -4868,15 +4868,15 @@ fn airSqrt(self: *Self, inst: Air.Inst.Index) !void {
4868 else => null,4868 else => null,
4869 } else null,4869 } else null,
4870 32 => switch (ty.vectorLen()) {4870 32 => switch (ty.vectorLen()) {
4871 1 => if (self.hasFeature(.avx)) .{ ._, .vsqrtss } else .{ ._, .sqrtss },4871 1 => if (self.hasFeature(.avx)) .{ .v_ss, .sqrt } else .{ ._ss, .sqrt },
4872 2...4 => if (self.hasFeature(.avx)) .{ ._, .vsqrtps } else .{ ._, .sqrtps },4872 2...4 => if (self.hasFeature(.avx)) .{ .v_ps, .sqrt } else .{ ._ps, .sqrt },
4873 5...8 => if (self.hasFeature(.avx)) .{ ._, .vsqrtps } else null,4873 5...8 => if (self.hasFeature(.avx)) .{ .v_ps, .sqrt } else null,
4874 else => null,4874 else => null,
4875 },4875 },
4876 64 => switch (ty.vectorLen()) {4876 64 => switch (ty.vectorLen()) {
4877 1 => if (self.hasFeature(.avx)) .{ ._, .vsqrtsd } else .{ ._, .sqrtsd },4877 1 => if (self.hasFeature(.avx)) .{ .v_sd, .sqrt } else .{ ._sd, .sqrt },
4878 2 => if (self.hasFeature(.avx)) .{ ._, .vsqrtpd } else .{ ._, .sqrtpd },4878 2 => if (self.hasFeature(.avx)) .{ .v_pd, .sqrt } else .{ ._pd, .sqrt },
4879 3...4 => if (self.hasFeature(.avx)) .{ ._, .vsqrtpd } else null,4879 3...4 => if (self.hasFeature(.avx)) .{ .v_pd, .sqrt } else null,
4880 else => null,4880 else => null,
4881 },4881 },
4882 80, 128 => null,4882 80, 128 => null,
...@@ -4888,8 +4888,8 @@ fn airSqrt(self: *Self, inst: Air.Inst.Index) !void {...@@ -4888,8 +4888,8 @@ fn airSqrt(self: *Self, inst: Air.Inst.Index) !void {
4888 })) |tag| tag else return self.fail("TODO implement airSqrt for {}", .{4888 })) |tag| tag else return self.fail("TODO implement airSqrt for {}", .{
4889 ty.fmt(self.bin_file.options.module.?),4889 ty.fmt(self.bin_file.options.module.?),
4890 });4890 });
4891 switch (mir_tag[1]) {4891 switch (mir_tag[0]) {
4892 .vsqrtss, .vsqrtsd => if (src_mcv.isMemory()) try self.asmRegisterRegisterMemory(4892 .v_ss, .v_sd => if (src_mcv.isMemory()) try self.asmRegisterRegisterMemory(
4893 mir_tag,4893 mir_tag,
4894 dst_reg,4894 dst_reg,
4895 dst_reg,4895 dst_reg,
...@@ -6325,13 +6325,13 @@ fn genBinOp(...@@ -6325,13 +6325,13 @@ fn genBinOp(
6325 defer self.register_manager.unlockReg(tmp_lock);6325 defer self.register_manager.unlockReg(tmp_lock);
63266326
6327 if (src_mcv.isMemory()) try self.asmRegisterRegisterMemoryImmediate(6327 if (src_mcv.isMemory()) try self.asmRegisterRegisterMemoryImmediate(
6328 .{ ._, .vpinsrw },6328 .{ .vp_w, .insr },
6329 dst_reg,6329 dst_reg,
6330 dst_reg,6330 dst_reg,
6331 src_mcv.mem(.word),6331 src_mcv.mem(.word),
6332 Immediate.u(1),6332 Immediate.u(1),
6333 ) else try self.asmRegisterRegisterRegister(6333 ) else try self.asmRegisterRegisterRegister(
6334 .{ ._, .vpunpcklwd },6334 .{ .vp_, .unpcklwd },
6335 dst_reg,6335 dst_reg,
6336 dst_reg,6336 dst_reg,
6337 (if (src_mcv.isRegister())6337 (if (src_mcv.isRegister())
...@@ -6339,15 +6339,15 @@ fn genBinOp(...@@ -6339,15 +6339,15 @@ fn genBinOp(
6339 else6339 else
6340 try self.copyToTmpRegister(rhs_ty, src_mcv)).to128(),6340 try self.copyToTmpRegister(rhs_ty, src_mcv)).to128(),
6341 );6341 );
6342 try self.asmRegisterRegister(.{ ._, .vcvtph2ps }, dst_reg, dst_reg);6342 try self.asmRegisterRegister(.{ .v_, .cvtph2ps }, dst_reg, dst_reg);
6343 try self.asmRegisterRegister(.{ ._, .vmovshdup }, tmp_reg, dst_reg);6343 try self.asmRegisterRegister(.{ .v_, .movshdup }, tmp_reg, dst_reg);
6344 try self.asmRegisterRegisterRegister(6344 try self.asmRegisterRegisterRegister(
6345 switch (air_tag) {6345 switch (air_tag) {
6346 .add => .{ ._, .vaddss },6346 .add => .{ .v_ss, .add },
6347 .sub => .{ ._, .vsubss },6347 .sub => .{ .v_ss, .sub },
6348 .div_float, .div_trunc, .div_floor, .div_exact => .{ ._, .vdivss },6348 .div_float, .div_trunc, .div_floor, .div_exact => .{ .v_ss, .div },
6349 .max => .{ ._, .vmaxss },6349 .max => .{ .v_ss, .max },
6350 .min => .{ ._, .vmaxss },6350 .min => .{ .v_ss, .max },
6351 else => unreachable,6351 else => unreachable,
6352 },6352 },
6353 dst_reg,6353 dst_reg,
...@@ -6355,7 +6355,7 @@ fn genBinOp(...@@ -6355,7 +6355,7 @@ fn genBinOp(
6355 tmp_reg,6355 tmp_reg,
6356 );6356 );
6357 try self.asmRegisterRegisterImmediate(6357 try self.asmRegisterRegisterImmediate(
6358 .{ ._, .vcvtps2ph },6358 .{ .v_, .cvtps2ph },
6359 dst_reg,6359 dst_reg,
6360 dst_reg,6360 dst_reg,
6361 Immediate.u(0b1_00),6361 Immediate.u(0b1_00),
...@@ -6363,29 +6363,29 @@ fn genBinOp(...@@ -6363,29 +6363,29 @@ fn genBinOp(
6363 return dst_mcv;6363 return dst_mcv;
6364 } else null,6364 } else null,
6365 32 => switch (air_tag) {6365 32 => switch (air_tag) {
6366 .add => if (self.hasFeature(.avx)) .{ ._, .vaddss } else .{ ._, .addss },6366 .add => if (self.hasFeature(.avx)) .{ .v_ss, .add } else .{ ._ss, .add },
6367 .sub => if (self.hasFeature(.avx)) .{ ._, .vsubss } else .{ ._, .subss },6367 .sub => if (self.hasFeature(.avx)) .{ .v_ss, .sub } else .{ ._ss, .sub },
6368 .mul => if (self.hasFeature(.avx)) .{ ._, .vmulss } else .{ ._, .mulss },6368 .mul => if (self.hasFeature(.avx)) .{ .v_ss, .mul } else .{ ._ss, .mul },
6369 .div_float,6369 .div_float,
6370 .div_trunc,6370 .div_trunc,
6371 .div_floor,6371 .div_floor,
6372 .div_exact,6372 .div_exact,
6373 => if (self.hasFeature(.avx)) .{ ._, .vdivss } else .{ ._, .divss },6373 => if (self.hasFeature(.avx)) .{ .v_ss, .div } else .{ ._ss, .div },
6374 .max => if (self.hasFeature(.avx)) .{ ._, .vmaxss } else .{ ._, .maxss },6374 .max => if (self.hasFeature(.avx)) .{ .v_ss, .max } else .{ ._ss, .max },
6375 .min => if (self.hasFeature(.avx)) .{ ._, .vminss } else .{ ._, .minss },6375 .min => if (self.hasFeature(.avx)) .{ .v_ss, .min } else .{ ._ss, .min },
6376 else => unreachable,6376 else => unreachable,
6377 },6377 },
6378 64 => switch (air_tag) {6378 64 => switch (air_tag) {
6379 .add => if (self.hasFeature(.avx)) .{ ._, .vaddsd } else .{ ._, .addsd },6379 .add => if (self.hasFeature(.avx)) .{ .v_sd, .add } else .{ ._sd, .add },
6380 .sub => if (self.hasFeature(.avx)) .{ ._, .vsubsd } else .{ ._, .subsd },6380 .sub => if (self.hasFeature(.avx)) .{ .v_sd, .sub } else .{ ._sd, .sub },
6381 .mul => if (self.hasFeature(.avx)) .{ ._, .vmulsd } else .{ ._, .mulsd },6381 .mul => if (self.hasFeature(.avx)) .{ .v_sd, .mul } else .{ ._sd, .mul },
6382 .div_float,6382 .div_float,
6383 .div_trunc,6383 .div_trunc,
6384 .div_floor,6384 .div_floor,
6385 .div_exact,6385 .div_exact,
6386 => if (self.hasFeature(.avx)) .{ ._, .vdivsd } else .{ ._, .divsd },6386 => if (self.hasFeature(.avx)) .{ .v_sd, .div } else .{ ._sd, .div },
6387 .max => if (self.hasFeature(.avx)) .{ ._, .vmaxsd } else .{ ._, .maxsd },6387 .max => if (self.hasFeature(.avx)) .{ .v_sd, .max } else .{ ._sd, .max },
6388 .min => if (self.hasFeature(.avx)) .{ ._, .vminsd } else .{ ._, .minsd },6388 .min => if (self.hasFeature(.avx)) .{ .v_sd, .min } else .{ ._sd, .min },
6389 else => unreachable,6389 else => unreachable,
6390 },6390 },
6391 80, 128 => null,6391 80, 128 => null,
...@@ -6401,13 +6401,13 @@ fn genBinOp(...@@ -6401,13 +6401,13 @@ fn genBinOp(
6401 defer self.register_manager.unlockReg(tmp_lock);6401 defer self.register_manager.unlockReg(tmp_lock);
64026402
6403 if (src_mcv.isMemory()) try self.asmRegisterRegisterMemoryImmediate(6403 if (src_mcv.isMemory()) try self.asmRegisterRegisterMemoryImmediate(
6404 .{ ._, .vpinsrw },6404 .{ .vp_w, .insr },
6405 dst_reg,6405 dst_reg,
6406 dst_reg,6406 dst_reg,
6407 src_mcv.mem(.word),6407 src_mcv.mem(.word),
6408 Immediate.u(1),6408 Immediate.u(1),
6409 ) else try self.asmRegisterRegisterRegister(6409 ) else try self.asmRegisterRegisterRegister(
6410 .{ ._, .vpunpcklwd },6410 .{ .vp_, .unpcklwd },
6411 dst_reg,6411 dst_reg,
6412 dst_reg,6412 dst_reg,
6413 (if (src_mcv.isRegister())6413 (if (src_mcv.isRegister())
...@@ -6415,15 +6415,15 @@ fn genBinOp(...@@ -6415,15 +6415,15 @@ fn genBinOp(
6415 else6415 else
6416 try self.copyToTmpRegister(rhs_ty, src_mcv)).to128(),6416 try self.copyToTmpRegister(rhs_ty, src_mcv)).to128(),
6417 );6417 );
6418 try self.asmRegisterRegister(.{ ._, .vcvtph2ps }, dst_reg, dst_reg);6418 try self.asmRegisterRegister(.{ .v_, .cvtph2ps }, dst_reg, dst_reg);
6419 try self.asmRegisterRegister(.{ ._, .vmovshdup }, tmp_reg, dst_reg);6419 try self.asmRegisterRegister(.{ .v_, .movshdup }, tmp_reg, dst_reg);
6420 try self.asmRegisterRegisterRegister(6420 try self.asmRegisterRegisterRegister(
6421 switch (air_tag) {6421 switch (air_tag) {
6422 .add => .{ ._, .vaddss },6422 .add => .{ .v_ss, .add },
6423 .sub => .{ ._, .vsubss },6423 .sub => .{ .v_ss, .sub },
6424 .div_float, .div_trunc, .div_floor, .div_exact => .{ ._, .vdivss },6424 .div_float, .div_trunc, .div_floor, .div_exact => .{ .v_ss, .div },
6425 .max => .{ ._, .vmaxss },6425 .max => .{ .v_ss, .max },
6426 .min => .{ ._, .vmaxss },6426 .min => .{ .v_ss, .max },
6427 else => unreachable,6427 else => unreachable,
6428 },6428 },
6429 dst_reg,6429 dst_reg,
...@@ -6431,7 +6431,7 @@ fn genBinOp(...@@ -6431,7 +6431,7 @@ fn genBinOp(
6431 tmp_reg,6431 tmp_reg,
6432 );6432 );
6433 try self.asmRegisterRegisterImmediate(6433 try self.asmRegisterRegisterImmediate(
6434 .{ ._, .vcvtps2ph },6434 .{ .v_, .cvtps2ph },
6435 dst_reg,6435 dst_reg,
6436 dst_reg,6436 dst_reg,
6437 Immediate.u(0b1_00),6437 Immediate.u(0b1_00),
...@@ -6444,12 +6444,12 @@ fn genBinOp(...@@ -6444,12 +6444,12 @@ fn genBinOp(
6444 defer self.register_manager.unlockReg(tmp_lock);6444 defer self.register_manager.unlockReg(tmp_lock);
64456445
6446 if (src_mcv.isMemory()) try self.asmRegisterMemoryImmediate(6446 if (src_mcv.isMemory()) try self.asmRegisterMemoryImmediate(
6447 .{ ._, .vpinsrd },6447 .{ .vp_d, .insr },
6448 dst_reg,6448 dst_reg,
6449 src_mcv.mem(.dword),6449 src_mcv.mem(.dword),
6450 Immediate.u(1),6450 Immediate.u(1),
6451 ) else try self.asmRegisterRegisterRegister(6451 ) else try self.asmRegisterRegisterRegister(
6452 .{ ._, .vunpcklps },6452 .{ .v_ps, .unpckl },
6453 dst_reg,6453 dst_reg,
6454 dst_reg,6454 dst_reg,
6455 (if (src_mcv.isRegister())6455 (if (src_mcv.isRegister())
...@@ -6457,20 +6457,20 @@ fn genBinOp(...@@ -6457,20 +6457,20 @@ fn genBinOp(
6457 else6457 else
6458 try self.copyToTmpRegister(rhs_ty, src_mcv)).to128(),6458 try self.copyToTmpRegister(rhs_ty, src_mcv)).to128(),
6459 );6459 );
6460 try self.asmRegisterRegister(.{ ._, .vcvtph2ps }, dst_reg, dst_reg);6460 try self.asmRegisterRegister(.{ .v_, .cvtph2ps }, dst_reg, dst_reg);
6461 try self.asmRegisterRegisterRegister(6461 try self.asmRegisterRegisterRegister(
6462 .{ ._, .vmovhlps },6462 .{ .v_ps, .movhl },
6463 tmp_reg,6463 tmp_reg,
6464 dst_reg,6464 dst_reg,
6465 dst_reg,6465 dst_reg,
6466 );6466 );
6467 try self.asmRegisterRegisterRegister(6467 try self.asmRegisterRegisterRegister(
6468 switch (air_tag) {6468 switch (air_tag) {
6469 .add => .{ ._, .vaddps },6469 .add => .{ .v_ps, .add },
6470 .sub => .{ ._, .vsubps },6470 .sub => .{ .v_ps, .sub },
6471 .div_float, .div_trunc, .div_floor, .div_exact => .{ ._, .vdivps },6471 .div_float, .div_trunc, .div_floor, .div_exact => .{ .v_ps, .div },
6472 .max => .{ ._, .vmaxps },6472 .max => .{ .v_ps, .max },
6473 .min => .{ ._, .vmaxps },6473 .min => .{ .v_ps, .max },
6474 else => unreachable,6474 else => unreachable,
6475 },6475 },
6476 dst_reg,6476 dst_reg,
...@@ -6478,7 +6478,7 @@ fn genBinOp(...@@ -6478,7 +6478,7 @@ fn genBinOp(
6478 tmp_reg,6478 tmp_reg,
6479 );6479 );
6480 try self.asmRegisterRegisterImmediate(6480 try self.asmRegisterRegisterImmediate(
6481 .{ ._, .vcvtps2ph },6481 .{ .v_, .cvtps2ph },
6482 dst_reg,6482 dst_reg,
6483 dst_reg,6483 dst_reg,
6484 Immediate.u(0b1_00),6484 Immediate.u(0b1_00),
...@@ -6490,13 +6490,13 @@ fn genBinOp(...@@ -6490,13 +6490,13 @@ fn genBinOp(
6490 const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);6490 const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
6491 defer self.register_manager.unlockReg(tmp_lock);6491 defer self.register_manager.unlockReg(tmp_lock);
64926492
6493 try self.asmRegisterRegister(.{ ._, .vcvtph2ps }, dst_reg, dst_reg);6493 try self.asmRegisterRegister(.{ .v_, .cvtph2ps }, dst_reg, dst_reg);
6494 if (src_mcv.isMemory()) try self.asmRegisterMemory(6494 if (src_mcv.isMemory()) try self.asmRegisterMemory(
6495 .{ ._, .vcvtph2ps },6495 .{ .v_, .cvtph2ps },
6496 tmp_reg,6496 tmp_reg,
6497 src_mcv.mem(.qword),6497 src_mcv.mem(.qword),
6498 ) else try self.asmRegisterRegister(6498 ) else try self.asmRegisterRegister(
6499 .{ ._, .vcvtph2ps },6499 .{ .v_, .cvtph2ps },
6500 tmp_reg,6500 tmp_reg,
6501 (if (src_mcv.isRegister())6501 (if (src_mcv.isRegister())
6502 src_mcv.getReg().?6502 src_mcv.getReg().?
...@@ -6505,11 +6505,11 @@ fn genBinOp(...@@ -6505,11 +6505,11 @@ fn genBinOp(
6505 );6505 );
6506 try self.asmRegisterRegisterRegister(6506 try self.asmRegisterRegisterRegister(
6507 switch (air_tag) {6507 switch (air_tag) {
6508 .add => .{ ._, .vaddps },6508 .add => .{ .v_ps, .add },
6509 .sub => .{ ._, .vsubps },6509 .sub => .{ .v_ps, .sub },
6510 .div_float, .div_trunc, .div_floor, .div_exact => .{ ._, .vdivps },6510 .div_float, .div_trunc, .div_floor, .div_exact => .{ .v_ps, .div },
6511 .max => .{ ._, .vmaxps },6511 .max => .{ .v_ps, .max },
6512 .min => .{ ._, .vmaxps },6512 .min => .{ .v_ps, .max },
6513 else => unreachable,6513 else => unreachable,
6514 },6514 },
6515 dst_reg,6515 dst_reg,
...@@ -6517,7 +6517,7 @@ fn genBinOp(...@@ -6517,7 +6517,7 @@ fn genBinOp(
6517 tmp_reg,6517 tmp_reg,
6518 );6518 );
6519 try self.asmRegisterRegisterImmediate(6519 try self.asmRegisterRegisterImmediate(
6520 .{ ._, .vcvtps2ph },6520 .{ .v_, .cvtps2ph },
6521 dst_reg,6521 dst_reg,
6522 dst_reg,6522 dst_reg,
6523 Immediate.u(0b1_00),6523 Immediate.u(0b1_00),
...@@ -6529,13 +6529,13 @@ fn genBinOp(...@@ -6529,13 +6529,13 @@ fn genBinOp(
6529 const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);6529 const tmp_lock = self.register_manager.lockRegAssumeUnused(tmp_reg);
6530 defer self.register_manager.unlockReg(tmp_lock);6530 defer self.register_manager.unlockReg(tmp_lock);
65316531
6532 try self.asmRegisterRegister(.{ ._, .vcvtph2ps }, dst_reg.to256(), dst_reg);6532 try self.asmRegisterRegister(.{ .v_, .cvtph2ps }, dst_reg.to256(), dst_reg);
6533 if (src_mcv.isMemory()) try self.asmRegisterMemory(6533 if (src_mcv.isMemory()) try self.asmRegisterMemory(
6534 .{ ._, .vcvtph2ps },6534 .{ .v_, .cvtph2ps },
6535 tmp_reg,6535 tmp_reg,
6536 src_mcv.mem(.xword),6536 src_mcv.mem(.xword),
6537 ) else try self.asmRegisterRegister(6537 ) else try self.asmRegisterRegister(
6538 .{ ._, .vcvtph2ps },6538 .{ .v_, .cvtph2ps },
6539 tmp_reg,6539 tmp_reg,
6540 (if (src_mcv.isRegister())6540 (if (src_mcv.isRegister())
6541 src_mcv.getReg().?6541 src_mcv.getReg().?
...@@ -6544,11 +6544,11 @@ fn genBinOp(...@@ -6544,11 +6544,11 @@ fn genBinOp(
6544 );6544 );
6545 try self.asmRegisterRegisterRegister(6545 try self.asmRegisterRegisterRegister(
6546 switch (air_tag) {6546 switch (air_tag) {
6547 .add => .{ ._, .vaddps },6547 .add => .{ .v_ps, .add },
6548 .sub => .{ ._, .vsubps },6548 .sub => .{ .v_ps, .sub },
6549 .div_float, .div_trunc, .div_floor, .div_exact => .{ ._, .vdivps },6549 .div_float, .div_trunc, .div_floor, .div_exact => .{ .v_ps, .div },
6550 .max => .{ ._, .vmaxps },6550 .max => .{ .v_ps, .max },
6551 .min => .{ ._, .vmaxps },6551 .min => .{ .v_ps, .max },
6552 else => unreachable,6552 else => unreachable,
6553 },6553 },
6554 dst_reg.to256(),6554 dst_reg.to256(),
...@@ -6556,7 +6556,7 @@ fn genBinOp(...@@ -6556,7 +6556,7 @@ fn genBinOp(
6556 tmp_reg,6556 tmp_reg,
6557 );6557 );
6558 try self.asmRegisterRegisterImmediate(6558 try self.asmRegisterRegisterImmediate(
6559 .{ ._, .vcvtps2ph },6559 .{ .v_, .cvtps2ph },
6560 dst_reg,6560 dst_reg,
6561 dst_reg.to256(),6561 dst_reg.to256(),
6562 Immediate.u(0b1_00),6562 Immediate.u(0b1_00),
...@@ -6567,76 +6567,76 @@ fn genBinOp(...@@ -6567,76 +6567,76 @@ fn genBinOp(
6567 } else null,6567 } else null,
6568 32 => switch (lhs_ty.vectorLen()) {6568 32 => switch (lhs_ty.vectorLen()) {
6569 1 => switch (air_tag) {6569 1 => switch (air_tag) {
6570 .add => if (self.hasFeature(.avx)) .{ ._, .vaddss } else .{ ._, .addss },6570 .add => if (self.hasFeature(.avx)) .{ .v_ss, .add } else .{ ._ss, .add },
6571 .sub => if (self.hasFeature(.avx)) .{ ._, .vsubss } else .{ ._, .subss },6571 .sub => if (self.hasFeature(.avx)) .{ .v_ss, .sub } else .{ ._ss, .sub },
6572 .mul => if (self.hasFeature(.avx)) .{ ._, .vmulss } else .{ ._, .mulss },6572 .mul => if (self.hasFeature(.avx)) .{ .v_ss, .mul } else .{ ._ss, .mul },
6573 .div_float,6573 .div_float,
6574 .div_trunc,6574 .div_trunc,
6575 .div_floor,6575 .div_floor,
6576 .div_exact,6576 .div_exact,
6577 => if (self.hasFeature(.avx)) .{ ._, .vdivss } else .{ ._, .divss },6577 => if (self.hasFeature(.avx)) .{ .v_ss, .div } else .{ ._ss, .div },
6578 .max => if (self.hasFeature(.avx)) .{ ._, .vmaxss } else .{ ._, .maxss },6578 .max => if (self.hasFeature(.avx)) .{ .v_ss, .max } else .{ ._ss, .max },
6579 .min => if (self.hasFeature(.avx)) .{ ._, .vminss } else .{ ._, .minss },6579 .min => if (self.hasFeature(.avx)) .{ .v_ss, .min } else .{ ._ss, .min },
6580 else => unreachable,6580 else => unreachable,
6581 },6581 },
6582 2...4 => switch (air_tag) {6582 2...4 => switch (air_tag) {
6583 .add => if (self.hasFeature(.avx)) .{ ._, .vaddps } else .{ ._, .addps },6583 .add => if (self.hasFeature(.avx)) .{ .v_ps, .add } else .{ ._ps, .add },
6584 .sub => if (self.hasFeature(.avx)) .{ ._, .vsubps } else .{ ._, .subps },6584 .sub => if (self.hasFeature(.avx)) .{ .v_ps, .sub } else .{ ._ps, .sub },
6585 .mul => if (self.hasFeature(.avx)) .{ ._, .vmulps } else .{ ._, .mulps },6585 .mul => if (self.hasFeature(.avx)) .{ .v_ps, .mul } else .{ ._ps, .mul },
6586 .div_float,6586 .div_float,
6587 .div_trunc,6587 .div_trunc,
6588 .div_floor,6588 .div_floor,
6589 .div_exact,6589 .div_exact,
6590 => if (self.hasFeature(.avx)) .{ ._, .vdivps } else .{ ._, .divps },6590 => if (self.hasFeature(.avx)) .{ .v_ps, .div } else .{ ._ps, .div },
6591 .max => if (self.hasFeature(.avx)) .{ ._, .vmaxps } else .{ ._, .maxps },6591 .max => if (self.hasFeature(.avx)) .{ .v_ps, .max } else .{ ._ps, .max },
6592 .min => if (self.hasFeature(.avx)) .{ ._, .vminps } else .{ ._, .minps },6592 .min => if (self.hasFeature(.avx)) .{ .v_ps, .min } else .{ ._ps, .min },
6593 else => unreachable,6593 else => unreachable,
6594 },6594 },
6595 5...8 => if (self.hasFeature(.avx)) switch (air_tag) {6595 5...8 => if (self.hasFeature(.avx)) switch (air_tag) {
6596 .add => .{ ._, .vaddps },6596 .add => .{ .v_ps, .add },
6597 .sub => .{ ._, .vsubps },6597 .sub => .{ .v_ps, .sub },
6598 .mul => .{ ._, .vmulps },6598 .mul => .{ .v_ps, .mul },
6599 .div_float, .div_trunc, .div_floor, .div_exact => .{ ._, .vdivps },6599 .div_float, .div_trunc, .div_floor, .div_exact => .{ .v_ps, .div },
6600 .max => .{ ._, .vmaxps },6600 .max => .{ .v_ps, .max },
6601 .min => .{ ._, .vminps },6601 .min => .{ .v_ps, .min },
6602 else => unreachable,6602 else => unreachable,
6603 } else null,6603 } else null,
6604 else => null,6604 else => null,
6605 },6605 },
6606 64 => switch (lhs_ty.vectorLen()) {6606 64 => switch (lhs_ty.vectorLen()) {
6607 1 => switch (air_tag) {6607 1 => switch (air_tag) {
6608 .add => if (self.hasFeature(.avx)) .{ ._, .vaddsd } else .{ ._, .addsd },6608 .add => if (self.hasFeature(.avx)) .{ .v_sd, .add } else .{ ._sd, .add },
6609 .sub => if (self.hasFeature(.avx)) .{ ._, .vsubsd } else .{ ._, .subsd },6609 .sub => if (self.hasFeature(.avx)) .{ .v_sd, .sub } else .{ ._sd, .sub },
6610 .mul => if (self.hasFeature(.avx)) .{ ._, .vmulsd } else .{ ._, .mulsd },6610 .mul => if (self.hasFeature(.avx)) .{ .v_sd, .mul } else .{ ._sd, .mul },
6611 .div_float,6611 .div_float,
6612 .div_trunc,6612 .div_trunc,
6613 .div_floor,6613 .div_floor,
6614 .div_exact,6614 .div_exact,
6615 => if (self.hasFeature(.avx)) .{ ._, .vdivsd } else .{ ._, .divsd },6615 => if (self.hasFeature(.avx)) .{ .v_sd, .div } else .{ ._sd, .div },
6616 .max => if (self.hasFeature(.avx)) .{ ._, .vmaxsd } else .{ ._, .maxsd },6616 .max => if (self.hasFeature(.avx)) .{ .v_sd, .max } else .{ ._sd, .max },
6617 .min => if (self.hasFeature(.avx)) .{ ._, .vminsd } else .{ ._, .minsd },6617 .min => if (self.hasFeature(.avx)) .{ .v_sd, .min } else .{ ._sd, .min },
6618 else => unreachable,6618 else => unreachable,
6619 },6619 },
6620 2 => switch (air_tag) {6620 2 => switch (air_tag) {
6621 .add => if (self.hasFeature(.avx)) .{ ._, .vaddpd } else .{ ._, .addpd },6621 .add => if (self.hasFeature(.avx)) .{ .v_pd, .add } else .{ ._pd, .add },
6622 .sub => if (self.hasFeature(.avx)) .{ ._, .vsubpd } else .{ ._, .subpd },6622 .sub => if (self.hasFeature(.avx)) .{ .v_pd, .sub } else .{ ._pd, .sub },
6623 .mul => if (self.hasFeature(.avx)) .{ ._, .vmulpd } else .{ ._, .mulpd },6623 .mul => if (self.hasFeature(.avx)) .{ .v_pd, .mul } else .{ ._pd, .mul },
6624 .div_float,6624 .div_float,
6625 .div_trunc,6625 .div_trunc,
6626 .div_floor,6626 .div_floor,
6627 .div_exact,6627 .div_exact,
6628 => if (self.hasFeature(.avx)) .{ ._, .vdivpd } else .{ ._, .divpd },6628 => if (self.hasFeature(.avx)) .{ .v_pd, .div } else .{ ._pd, .div },
6629 .max => if (self.hasFeature(.avx)) .{ ._, .vmaxpd } else .{ ._, .maxpd },6629 .max => if (self.hasFeature(.avx)) .{ .v_pd, .max } else .{ ._pd, .max },
6630 .min => if (self.hasFeature(.avx)) .{ ._, .vminpd } else .{ ._, .minpd },6630 .min => if (self.hasFeature(.avx)) .{ .v_pd, .min } else .{ ._pd, .min },
6631 else => unreachable,6631 else => unreachable,
6632 },6632 },
6633 3...4 => if (self.hasFeature(.avx)) switch (air_tag) {6633 3...4 => if (self.hasFeature(.avx)) switch (air_tag) {
6634 .add => .{ ._, .vaddpd },6634 .add => .{ .v_pd, .add },
6635 .sub => .{ ._, .vsubpd },6635 .sub => .{ .v_pd, .sub },
6636 .mul => .{ ._, .vmulpd },6636 .mul => .{ .v_pd, .mul },
6637 .div_float, .div_trunc, .div_floor, .div_exact => .{ ._, .vdivpd },6637 .div_float, .div_trunc, .div_floor, .div_exact => .{ .v_pd, .div },
6638 .max => .{ ._, .vmaxpd },6638 .max => .{ .v_pd, .max },
6639 .min => .{ ._, .vminpd },6639 .min => .{ .v_pd, .min },
6640 else => unreachable,6640 else => unreachable,
6641 } else null,6641 } else null,
6642 else => null,6642 else => null,
...@@ -7563,13 +7563,13 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {...@@ -7563,13 +7563,13 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
7563 defer self.register_manager.unlockReg(tmp2_lock);7563 defer self.register_manager.unlockReg(tmp2_lock);
75647564
7565 if (src_mcv.isMemory()) try self.asmRegisterRegisterMemoryImmediate(7565 if (src_mcv.isMemory()) try self.asmRegisterRegisterMemoryImmediate(
7566 .{ ._, .vpinsrw },7566 .{ .vp_w, .insr },
7567 tmp1_reg,7567 tmp1_reg,
7568 dst_reg.to128(),7568 dst_reg.to128(),
7569 src_mcv.mem(.word),7569 src_mcv.mem(.word),
7570 Immediate.u(1),7570 Immediate.u(1),
7571 ) else try self.asmRegisterRegisterRegister(7571 ) else try self.asmRegisterRegisterRegister(
7572 .{ ._, .vpunpcklwd },7572 .{ .vp_, .unpcklwd },
7573 tmp1_reg,7573 tmp1_reg,
7574 dst_reg.to128(),7574 dst_reg.to128(),
7575 (if (src_mcv.isRegister())7575 (if (src_mcv.isRegister())
...@@ -7577,20 +7577,20 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {...@@ -7577,20 +7577,20 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
7577 else7577 else
7578 try self.copyToTmpRegister(ty, src_mcv)).to128(),7578 try self.copyToTmpRegister(ty, src_mcv)).to128(),
7579 );7579 );
7580 try self.asmRegisterRegister(.{ ._, .vcvtph2ps }, tmp1_reg, tmp1_reg);7580 try self.asmRegisterRegister(.{ .v_, .cvtph2ps }, tmp1_reg, tmp1_reg);
7581 try self.asmRegisterRegister(.{ ._, .vmovshdup }, tmp2_reg, tmp1_reg);7581 try self.asmRegisterRegister(.{ .v_, .movshdup }, tmp2_reg, tmp1_reg);
7582 try self.genBinOpMir(.{ ._, .ucomiss }, ty, tmp1_mcv, tmp2_mcv);7582 try self.genBinOpMir(.{ ._ss, .ucomi }, ty, tmp1_mcv, tmp2_mcv);
7583 } else return self.fail("TODO implement airCmp for {}", .{7583 } else return self.fail("TODO implement airCmp for {}", .{
7584 ty.fmt(self.bin_file.options.module.?),7584 ty.fmt(self.bin_file.options.module.?),
7585 }),7585 }),
7586 32 => try self.genBinOpMir(7586 32 => try self.genBinOpMir(
7587 .{ ._, .ucomiss },7587 .{ ._ss, .ucomi },
7588 ty,7588 ty,
7589 .{ .register = dst_reg },7589 .{ .register = dst_reg },
7590 src_mcv,7590 src_mcv,
7591 ),7591 ),
7592 64 => try self.genBinOpMir(7592 64 => try self.genBinOpMir(
7593 .{ ._, .ucomisd },7593 .{ ._sd, .ucomi },
7594 ty,7594 ty,
7595 .{ .register = dst_reg },7595 .{ .register = dst_reg },
7596 src_mcv,7596 src_mcv,
...@@ -8573,42 +8573,42 @@ fn movMirTag(self: *Self, ty: Type, aligned: bool) !Mir.Inst.FixedTag {...@@ -8573,42 +8573,42 @@ fn movMirTag(self: *Self, ty: Type, aligned: bool) !Mir.Inst.FixedTag {
8573 else => return .{ ._, .mov },8573 else => return .{ ._, .mov },
8574 .Float => switch (ty.floatBits(self.target.*)) {8574 .Float => switch (ty.floatBits(self.target.*)) {
8575 16 => unreachable, // needs special handling8575 16 => unreachable, // needs special handling
8576 32 => return if (self.hasFeature(.avx)) .{ ._, .vmovss } else .{ ._, .movss },8576 32 => return if (self.hasFeature(.avx)) .{ .v_ss, .mov } else .{ ._ss, .mov },
8577 64 => return if (self.hasFeature(.avx)) .{ ._, .vmovsd } else .{ ._, .movsd },8577 64 => return if (self.hasFeature(.avx)) .{ .v_sd, .mov } else .{ ._sd, .mov },
8578 128 => return if (self.hasFeature(.avx))8578 128 => return if (self.hasFeature(.avx))
8579 if (aligned) .{ ._, .vmovaps } else .{ ._, .vmovups }8579 if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu }
8580 else if (aligned) .{ ._, .movaps } else .{ ._, .movups },8580 else if (aligned) .{ ._ps, .mova } else .{ ._ps, .movu },
8581 else => {},8581 else => {},
8582 },8582 },
8583 .Vector => switch (ty.childType().zigTypeTag()) {8583 .Vector => switch (ty.childType().zigTypeTag()) {
8584 .Float => switch (ty.childType().floatBits(self.target.*)) {8584 .Float => switch (ty.childType().floatBits(self.target.*)) {
8585 16 => switch (ty.vectorLen()) {8585 16 => switch (ty.vectorLen()) {
8586 1 => unreachable, // needs special handling8586 1 => unreachable, // needs special handling
8587 2 => return if (self.hasFeature(.avx)) .{ ._, .vmovss } else .{ ._, .movss },8587 2 => return if (self.hasFeature(.avx)) .{ .v_ss, .mov } else .{ ._ss, .mov },
8588 3...4 => return if (self.hasFeature(.avx)) .{ ._, .vmovsd } else .{ ._, .movsd },8588 3...4 => return if (self.hasFeature(.avx)) .{ .v_sd, .mov } else .{ ._sd, .mov },
8589 5...8 => return if (self.hasFeature(.avx))8589 5...8 => return if (self.hasFeature(.avx))
8590 if (aligned) .{ ._, .vmovaps } else .{ ._, .vmovups }8590 if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu }
8591 else if (aligned) .{ ._, .movaps } else .{ ._, .movups },8591 else if (aligned) .{ ._ps, .mova } else .{ ._ps, .movu },
8592 9...16 => if (self.hasFeature(.avx))8592 9...16 => if (self.hasFeature(.avx))
8593 return if (aligned) .{ ._, .vmovaps } else .{ ._, .vmovups },8593 return if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu },
8594 else => {},8594 else => {},
8595 },8595 },
8596 32 => switch (ty.vectorLen()) {8596 32 => switch (ty.vectorLen()) {
8597 1 => return if (self.hasFeature(.avx)) .{ ._, .vmovss } else .{ ._, .movss },8597 1 => return if (self.hasFeature(.avx)) .{ .v_ss, .mov } else .{ ._ss, .mov },
8598 2...4 => return if (self.hasFeature(.avx))8598 2...4 => return if (self.hasFeature(.avx))
8599 if (aligned) .{ ._, .vmovaps } else .{ ._, .vmovups }8599 if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu }
8600 else if (aligned) .{ ._, .movaps } else .{ ._, .movups },8600 else if (aligned) .{ ._ps, .mova } else .{ ._ps, .movu },
8601 5...8 => if (self.hasFeature(.avx))8601 5...8 => if (self.hasFeature(.avx))
8602 return if (aligned) .{ ._, .vmovaps } else .{ ._, .vmovups },8602 return if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu },
8603 else => {},8603 else => {},
8604 },8604 },
8605 64 => switch (ty.vectorLen()) {8605 64 => switch (ty.vectorLen()) {
8606 1 => return if (self.hasFeature(.avx)) .{ ._, .vmovsd } else .{ ._, .movsd },8606 1 => return if (self.hasFeature(.avx)) .{ .v_sd, .mov } else .{ ._sd, .mov },
8607 2 => return if (self.hasFeature(.avx))8607 2 => return if (self.hasFeature(.avx))
8608 if (aligned) .{ ._, .vmovaps } else .{ ._, .vmovups }8608 if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu }
8609 else if (aligned) .{ ._, .movaps } else .{ ._, .movups },8609 else if (aligned) .{ ._ps, .mova } else .{ ._ps, .movu },
8610 3...4 => if (self.hasFeature(.avx))8610 3...4 => if (self.hasFeature(.avx))
8611 return if (aligned) .{ ._, .vmovaps } else .{ ._, .vmovups },8611 return if (aligned) .{ .v_ps, .mova } else .{ .v_ps, .movu },
8612 else => {},8612 else => {},
8613 },8613 },
8614 else => {},8614 else => {},
...@@ -8724,11 +8724,11 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr...@@ -8724,11 +8724,11 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr
8724 if ((dst_reg.class() == .floating_point) == (src_reg.class() == .floating_point))8724 if ((dst_reg.class() == .floating_point) == (src_reg.class() == .floating_point))
8725 switch (ty.zigTypeTag()) {8725 switch (ty.zigTypeTag()) {
8726 else => .{ ._, .mov },8726 else => .{ ._, .mov },
8727 .Float, .Vector => .{ ._, .movaps },8727 .Float, .Vector => .{ ._ps, .mova },
8728 }8728 }
8729 else switch (abi_size) {8729 else switch (abi_size) {
8730 2 => return try self.asmRegisterRegisterImmediate(8730 2 => return try self.asmRegisterRegisterImmediate(
8731 if (dst_reg.class() == .floating_point) .{ ._, .pinsrw } else .{ ._, .pextrw },8731 if (dst_reg.class() == .floating_point) .{ .p_w, .insr } else .{ .p_w, .extr },
8732 registerAlias(dst_reg, 4),8732 registerAlias(dst_reg, 4),
8733 registerAlias(src_reg, 4),8733 registerAlias(src_reg, 4),
8734 Immediate.u(0),8734 Immediate.u(0),
...@@ -8761,7 +8761,7 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr...@@ -8761,7 +8761,7 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr
8761 });8761 });
8762 if (ty.isRuntimeFloat() and ty.floatBits(self.target.*) == 16)8762 if (ty.isRuntimeFloat() and ty.floatBits(self.target.*) == 16)
8763 try self.asmRegisterMemoryImmediate(8763 try self.asmRegisterMemoryImmediate(
8764 .{ ._, .pinsrw },8764 .{ .p_w, .insr },
8765 registerAlias(dst_reg, abi_size),8765 registerAlias(dst_reg, abi_size),
8766 src_mem,8766 src_mem,
8767 Immediate.u(0),8767 Immediate.u(0),
...@@ -8794,7 +8794,7 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr...@@ -8794,7 +8794,7 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr
8794 });8794 });
8795 return if (ty.isRuntimeFloat() and ty.floatBits(self.target.*) == 16)8795 return if (ty.isRuntimeFloat() and ty.floatBits(self.target.*) == 16)
8796 self.asmRegisterMemoryImmediate(8796 self.asmRegisterMemoryImmediate(
8797 .{ ._, .pinsrw },8797 .{ .p_w, .insr },
8798 registerAlias(dst_reg, abi_size),8798 registerAlias(dst_reg, abi_size),
8799 src_mem,8799 src_mem,
8800 Immediate.u(0),8800 Immediate.u(0),
...@@ -8838,7 +8838,7 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr...@@ -8838,7 +8838,7 @@ fn genSetReg(self: *Self, dst_reg: Register, ty: Type, src_mcv: MCValue) InnerEr
8838 });8838 });
8839 if (ty.isRuntimeFloat() and ty.floatBits(self.target.*) == 16)8839 if (ty.isRuntimeFloat() and ty.floatBits(self.target.*) == 16)
8840 try self.asmRegisterMemoryImmediate(8840 try self.asmRegisterMemoryImmediate(
8841 .{ ._, .pinsrw },8841 .{ .p_w, .insr },
8842 registerAlias(dst_reg, abi_size),8842 registerAlias(dst_reg, abi_size),
8843 src_mem,8843 src_mem,
8844 Immediate.u(0),8844 Immediate.u(0),
...@@ -8952,7 +8952,7 @@ fn genSetMem(self: *Self, base: Memory.Base, disp: i32, ty: Type, src_mcv: MCVal...@@ -8952,7 +8952,7 @@ fn genSetMem(self: *Self, base: Memory.Base, disp: i32, ty: Type, src_mcv: MCVal
8952 );8952 );
8953 if (ty.isRuntimeFloat() and ty.floatBits(self.target.*) == 16)8953 if (ty.isRuntimeFloat() and ty.floatBits(self.target.*) == 16)
8954 try self.asmMemoryRegisterImmediate(8954 try self.asmMemoryRegisterImmediate(
8955 .{ ._, .pextrw },8955 .{ .p_w, .extr },
8956 dst_mem,8956 dst_mem,
8957 src_reg.to128(),8957 src_reg.to128(),
8958 Immediate.u(0),8958 Immediate.u(0),
...@@ -9069,7 +9069,7 @@ fn genInlineMemcpyRegisterRegister(...@@ -9069,7 +9069,7 @@ fn genInlineMemcpyRegisterRegister(
9069 try self.asmMemoryRegister(9069 try self.asmMemoryRegister(
9070 switch (src_reg.class()) {9070 switch (src_reg.class()) {
9071 .general_purpose, .segment => .{ ._, .mov },9071 .general_purpose, .segment => .{ ._, .mov },
9072 .floating_point => .{ ._, .movss },9072 .floating_point => .{ ._ss, .mov },
9073 },9073 },
9074 Memory.sib(Memory.PtrSize.fromSize(abi_size), .{ .base = dst_reg, .disp = -offset }),9074 Memory.sib(Memory.PtrSize.fromSize(abi_size), .{ .base = dst_reg, .disp = -offset }),
9075 registerAlias(src_reg, abi_size),9075 registerAlias(src_reg, abi_size),
...@@ -10197,21 +10197,21 @@ fn airMulAdd(self: *Self, inst: Air.Inst.Index) !void {...@@ -10197,21 +10197,21 @@ fn airMulAdd(self: *Self, inst: Air.Inst.Index) !void {
10197 if (mem.eql(u2, &order, &.{ 1, 3, 2 }) or mem.eql(u2, &order, &.{ 3, 1, 2 }))10197 if (mem.eql(u2, &order, &.{ 1, 3, 2 }) or mem.eql(u2, &order, &.{ 3, 1, 2 }))
10198 switch (ty.zigTypeTag()) {10198 switch (ty.zigTypeTag()) {
10199 .Float => switch (ty.floatBits(self.target.*)) {10199 .Float => switch (ty.floatBits(self.target.*)) {
10200 32 => .{ ._, .vfmadd132ss },10200 32 => .{ .v_ss, .fmadd132 },
10201 64 => .{ ._, .vfmadd132sd },10201 64 => .{ .v_sd, .fmadd132 },
10202 16, 80, 128 => null,10202 16, 80, 128 => null,
10203 else => unreachable,10203 else => unreachable,
10204 },10204 },
10205 .Vector => switch (ty.childType().zigTypeTag()) {10205 .Vector => switch (ty.childType().zigTypeTag()) {
10206 .Float => switch (ty.childType().floatBits(self.target.*)) {10206 .Float => switch (ty.childType().floatBits(self.target.*)) {
10207 32 => switch (ty.vectorLen()) {10207 32 => switch (ty.vectorLen()) {
10208 1 => .{ ._, .vfmadd132ss },10208 1 => .{ .v_ss, .fmadd132 },
10209 2...8 => .{ ._, .vfmadd132ps },10209 2...8 => .{ .v_ps, .fmadd132 },
10210 else => null,10210 else => null,
10211 },10211 },
10212 64 => switch (ty.vectorLen()) {10212 64 => switch (ty.vectorLen()) {
10213 1 => .{ ._, .vfmadd132sd },10213 1 => .{ .v_sd, .fmadd132 },
10214 2...4 => .{ ._, .vfmadd132pd },10214 2...4 => .{ .v_pd, .fmadd132 },
10215 else => null,10215 else => null,
10216 },10216 },
10217 16, 80, 128 => null,10217 16, 80, 128 => null,
...@@ -10224,21 +10224,21 @@ fn airMulAdd(self: *Self, inst: Air.Inst.Index) !void {...@@ -10224,21 +10224,21 @@ fn airMulAdd(self: *Self, inst: Air.Inst.Index) !void {
10224 else if (mem.eql(u2, &order, &.{ 2, 1, 3 }) or mem.eql(u2, &order, &.{ 1, 2, 3 }))10224 else if (mem.eql(u2, &order, &.{ 2, 1, 3 }) or mem.eql(u2, &order, &.{ 1, 2, 3 }))
10225 switch (ty.zigTypeTag()) {10225 switch (ty.zigTypeTag()) {
10226 .Float => switch (ty.floatBits(self.target.*)) {10226 .Float => switch (ty.floatBits(self.target.*)) {
10227 32 => .{ ._, .vfmadd213ss },10227 32 => .{ .v_ss, .fmadd213 },
10228 64 => .{ ._, .vfmadd213sd },10228 64 => .{ .v_sd, .fmadd213 },
10229 16, 80, 128 => null,10229 16, 80, 128 => null,
10230 else => unreachable,10230 else => unreachable,
10231 },10231 },
10232 .Vector => switch (ty.childType().zigTypeTag()) {10232 .Vector => switch (ty.childType().zigTypeTag()) {
10233 .Float => switch (ty.childType().floatBits(self.target.*)) {10233 .Float => switch (ty.childType().floatBits(self.target.*)) {
10234 32 => switch (ty.vectorLen()) {10234 32 => switch (ty.vectorLen()) {
10235 1 => .{ ._, .vfmadd213ss },10235 1 => .{ .v_ss, .fmadd213 },
10236 2...8 => .{ ._, .vfmadd213ps },10236 2...8 => .{ .v_ps, .fmadd213 },
10237 else => null,10237 else => null,
10238 },10238 },
10239 64 => switch (ty.vectorLen()) {10239 64 => switch (ty.vectorLen()) {
10240 1 => .{ ._, .vfmadd213sd },10240 1 => .{ .v_sd, .fmadd213 },
10241 2...4 => .{ ._, .vfmadd213pd },10241 2...4 => .{ .v_pd, .fmadd213 },
10242 else => null,10242 else => null,
10243 },10243 },
10244 16, 80, 128 => null,10244 16, 80, 128 => null,
...@@ -10251,21 +10251,21 @@ fn airMulAdd(self: *Self, inst: Air.Inst.Index) !void {...@@ -10251,21 +10251,21 @@ fn airMulAdd(self: *Self, inst: Air.Inst.Index) !void {
10251 else if (mem.eql(u2, &order, &.{ 2, 3, 1 }) or mem.eql(u2, &order, &.{ 3, 2, 1 }))10251 else if (mem.eql(u2, &order, &.{ 2, 3, 1 }) or mem.eql(u2, &order, &.{ 3, 2, 1 }))
10252 switch (ty.zigTypeTag()) {10252 switch (ty.zigTypeTag()) {
10253 .Float => switch (ty.floatBits(self.target.*)) {10253 .Float => switch (ty.floatBits(self.target.*)) {
10254 32 => .{ ._, .vfmadd231ss },10254 32 => .{ .v_ss, .fmadd231 },
10255 64 => .{ ._, .vfmadd231sd },10255 64 => .{ .v_sd, .fmadd231 },
10256 16, 80, 128 => null,10256 16, 80, 128 => null,
10257 else => unreachable,10257 else => unreachable,
10258 },10258 },
10259 .Vector => switch (ty.childType().zigTypeTag()) {10259 .Vector => switch (ty.childType().zigTypeTag()) {
10260 .Float => switch (ty.childType().floatBits(self.target.*)) {10260 .Float => switch (ty.childType().floatBits(self.target.*)) {
10261 32 => switch (ty.vectorLen()) {10261 32 => switch (ty.vectorLen()) {
10262 1 => .{ ._, .vfmadd231ss },10262 1 => .{ .v_ss, .fmadd231 },
10263 2...8 => .{ ._, .vfmadd231ps },10263 2...8 => .{ .v_ps, .fmadd231 },
10264 else => null,10264 else => null,
10265 },10265 },
10266 64 => switch (ty.vectorLen()) {10266 64 => switch (ty.vectorLen()) {
10267 1 => .{ ._, .vfmadd231sd },10267 1 => .{ .v_sd, .fmadd231 },
10268 2...4 => .{ ._, .vfmadd231pd },10268 2...4 => .{ .v_pd, .fmadd231 },
10269 else => null,10269 else => null,
10270 },10270 },
10271 16, 80, 128 => null,10271 16, 80, 128 => null,
src/arch/x86_64/Mir.zig+82-282
...@@ -278,8 +278,14 @@ pub const Inst = struct {...@@ -278,8 +278,14 @@ pub const Inst = struct {
278 /// Add with carry278 /// Add with carry
279 adc,279 adc,
280 /// Add280 /// Add
281 /// Add packed single-precision floating-point values
282 /// Add scalar single-precision floating-point values
283 /// Add packed double-precision floating-point values
284 /// Add scalar double-precision floating-point values
281 add,285 add,
282 /// Logical and286 /// Logical and
287 /// Bitwise logical and of packed single-precision floating-point values
288 /// Bitwise logical and of packed double-precision floating-point values
283 @"and",289 @"and",
284 /// Bit scan forward290 /// Bit scan forward
285 bsf,291 bsf,
...@@ -304,6 +310,8 @@ pub const Inst = struct {...@@ -304,6 +310,8 @@ pub const Inst = struct {
304 cmov,310 cmov,
305 /// Logical compare311 /// Logical compare
306 /// Compare string312 /// Compare string
313 /// Compare scalar single-precision floating-point values
314 /// Compare scalar double-precision floating-point values
307 cmp,315 cmp,
308 /// Compare and exchange316 /// Compare and exchange
309 /// Compare and exchange bytes317 /// Compare and exchange bytes
...@@ -316,6 +324,10 @@ pub const Inst = struct {...@@ -316,6 +324,10 @@ pub const Inst = struct {
316 cwde,324 cwde,
317 /// Unsigned division325 /// Unsigned division
318 /// Signed division326 /// Signed division
327 /// Divide packed single-precision floating-point values
328 /// Divide scalar single-precision floating-point values
329 /// Divide packed double-precision floating-point values
330 /// Divide scalar double-precision floating-point values
319 div,331 div,
320 ///332 ///
321 int3,333 int3,
...@@ -339,6 +351,8 @@ pub const Inst = struct {...@@ -339,6 +351,8 @@ pub const Inst = struct {
339 mfence,351 mfence,
340 /// Move352 /// Move
341 /// Move data from string to string353 /// Move data from string to string
354 /// Move scalar single-precision floating-point value
355 /// Move scalar double-precision floating-point value
342 /// Move doubleword356 /// Move doubleword
343 /// Move quadword357 /// Move quadword
344 mov,358 mov,
...@@ -350,6 +364,10 @@ pub const Inst = struct {...@@ -350,6 +364,10 @@ pub const Inst = struct {
350 movzx,364 movzx,
351 /// Multiply365 /// Multiply
352 /// Signed multiplication366 /// Signed multiplication
367 /// Multiply packed single-precision floating-point values
368 /// Multiply scalar single-precision floating-point values
369 /// Multiply packed double-precision floating-point values
370 /// Multiply scalar double-precision floating-point values
353 mul,371 mul,
354 /// Two's complement negation372 /// Two's complement negation
355 neg,373 neg,
...@@ -358,6 +376,8 @@ pub const Inst = struct {...@@ -358,6 +376,8 @@ pub const Inst = struct {
358 /// One's complement negation376 /// One's complement negation
359 not,377 not,
360 /// Logical or378 /// Logical or
379 /// Bitwise logical or of packed single-precision floating-point values
380 /// Bitwise logical or of packed double-precision floating-point values
361 @"or",381 @"or",
362 /// Pop382 /// Pop
363 pop,383 pop,
...@@ -390,6 +410,10 @@ pub const Inst = struct {...@@ -390,6 +410,10 @@ pub const Inst = struct {
390 /// Double precision shift right410 /// Double precision shift right
391 sh,411 sh,
392 /// Subtract412 /// Subtract
413 /// Subtract packed single-precision floating-point values
414 /// Subtract scalar single-precision floating-point values
415 /// Subtract packed double-precision floating-point values
416 /// Subtract scalar double-precision floating-point values
393 sub,417 sub,
394 /// Store string418 /// Store string
395 sto,419 sto,
...@@ -406,145 +430,88 @@ pub const Inst = struct {...@@ -406,145 +430,88 @@ pub const Inst = struct {
406 /// Exchange register/memory with register430 /// Exchange register/memory with register
407 xchg,431 xchg,
408 /// Logical exclusive-or432 /// Logical exclusive-or
433 /// Bitwise logical xor of packed single-precision floating-point values
434 /// Bitwise logical xor of packed double-precision floating-point values
409 xor,435 xor,
410436
411 /// Add packed single-precision floating-point values437 /// Bitwise logical and not of packed single-precision floating-point values
412 addps,438 /// Bitwise logical and not of packed double-precision floating-point values
413 /// Add scalar single-precision floating-point values439 andn,
414 addss,
415 /// Bitwise logical and of packed single precision floating-point values
416 andps,
417 /// Bitwise logical and not of packed single precision floating-point values
418 andnps,
419 /// Compare scalar single-precision floating-point values
420 cmpss,
421 /// Convert doubleword integer to scalar single-precision floating-point value440 /// Convert doubleword integer to scalar single-precision floating-point value
422 cvtsi2ss,441 cvtsi2ss,
423 /// Divide packed single-precision floating-point values
424 divps,
425 /// Divide scalar single-precision floating-point values
426 divss,
427 /// Maximum of packed single-precision floating-point values442 /// Maximum of packed single-precision floating-point values
428 maxps,
429 /// Maximum of scalar single-precision floating-point values443 /// Maximum of scalar single-precision floating-point values
430 maxss,444 /// Maximum of packed double-precision floating-point values
445 /// Maximum of scalar double-precision floating-point values
446 max,
431 /// Minimum of packed single-precision floating-point values447 /// Minimum of packed single-precision floating-point values
432 minps,
433 /// Minimum of scalar single-precision floating-point values448 /// Minimum of scalar single-precision floating-point values
434 minss,449 /// Minimum of packed double-precision floating-point values
450 /// Minimum of scalar double-precision floating-point values
451 min,
435 /// Move aligned packed single-precision floating-point values452 /// Move aligned packed single-precision floating-point values
436 movaps,453 /// Move aligned packed double-precision floating-point values
454 mova,
437 /// Move packed single-precision floating-point values high to low455 /// Move packed single-precision floating-point values high to low
438 movhlps,456 movhl,
439 /// Move scalar single-precision floating-point value
440 movss,
441 /// Move unaligned packed single-precision floating-point values457 /// Move unaligned packed single-precision floating-point values
442 movups,458 /// Move unaligned packed double-precision floating-point values
443 /// Multiply packed single-precision floating-point values459 movu,
444 mulps,460 /// Extract byte
445 /// Multiply scalar single-precision floating-point values
446 mulss,
447 /// Bitwise logical or of packed single precision floating-point values
448 orps,
449 /// Extract word461 /// Extract word
450 pextrw,462 /// Extract doubleword
463 /// Extract quadword
464 extr,
465 /// Insert byte
451 /// Insert word466 /// Insert word
452 pinsrw,467 /// Insert doubleword
468 /// Insert quadword
469 insr,
453 /// Square root of packed single-precision floating-point values470 /// Square root of packed single-precision floating-point values
454 sqrtps,
455 /// Square root of scalar single-precision floating-point value471 /// Square root of scalar single-precision floating-point value
456 sqrtss,472 /// Square root of packed double-precision floating-point values
457 /// Subtract packed single-precision floating-point values473 /// Square root of scalar double-precision floating-point value
458 subps,474 sqrt,
459 /// Subtract scalar single-precision floating-point values
460 subss,
461 /// Unordered compare scalar single-precision floating-point values475 /// Unordered compare scalar single-precision floating-point values
462 ucomiss,476 /// Unordered compare scalar double-precision floating-point values
477 ucomi,
463 /// Unpack and interleave high packed single-precision floating-point values478 /// Unpack and interleave high packed single-precision floating-point values
464 unpckhps,479 /// Unpack and interleave high packed double-precision floating-point values
480 unpckh,
465 /// Unpack and interleave low packed single-precision floating-point values481 /// Unpack and interleave low packed single-precision floating-point values
466 unpcklps,482 /// Unpack and interleave low packed double-precision floating-point values
467 /// Bitwise logical xor of packed single precision floating-point values483 unpckl,
468 xorps,
469484
470 /// Add packed double-precision floating-point values
471 addpd,
472 /// Add scalar double-precision floating-point values
473 addsd,
474 /// Bitwise logical and not of packed double precision floating-point values
475 andnpd,
476 /// Bitwise logical and of packed double precision floating-point values
477 andpd,
478 /// Compare scalar double-precision floating-point values
479 cmpsd,
480 /// Convert scalar double-precision floating-point value to scalar single-precision floating-point value485 /// Convert scalar double-precision floating-point value to scalar single-precision floating-point value
481 cvtsd2ss,486 cvtsd2ss,
482 /// Convert doubleword integer to scalar double-precision floating-point value487 /// Convert doubleword integer to scalar double-precision floating-point value
483 cvtsi2sd,488 cvtsi2sd,
484 /// Convert scalar single-precision floating-point value to scalar double-precision floating-point value489 /// Convert scalar single-precision floating-point value to scalar double-precision floating-point value
485 cvtss2sd,490 cvtss2sd,
486 /// Divide packed double-precision floating-point values
487 divpd,
488 /// Divide scalar double-precision floating-point values
489 divsd,
490 /// Maximum of packed double-precision floating-point values
491 maxpd,
492 /// Maximum of scalar double-precision floating-point values
493 maxsd,
494 /// Minimum of packed double-precision floating-point values
495 minpd,
496 /// Minimum of scalar double-precision floating-point values
497 minsd,
498 /// Move scalar double-precision floating-point value
499 movsd,
500 /// Multiply packed double-precision floating-point values
501 mulpd,
502 /// Multiply scalar double-precision floating-point values
503 mulsd,
504 /// Bitwise logical or of packed double precision floating-point values
505 orpd,
506 /// Shuffle packed high words491 /// Shuffle packed high words
507 pshufhw,492 shufh,
508 /// Shuffle packed low words493 /// Shuffle packed low words
509 pshuflw,494 shufl,
510 /// Shift packed data right logical495 /// Shift packed data right logical
511 psrld,
512 /// Shift packed data right logical496 /// Shift packed data right logical
513 psrlq,
514 /// Shift packed data right logical497 /// Shift packed data right logical
515 psrlw,498 srl,
516 /// Unpack high data499 /// Unpack high data
517 punpckhbw,500 unpckhbw,
518 /// Unpack high data501 /// Unpack high data
519 punpckhdq,502 unpckhdq,
520 /// Unpack high data503 /// Unpack high data
521 punpckhqdq,504 unpckhqdq,
522 /// Unpack high data505 /// Unpack high data
523 punpckhwd,506 unpckhwd,
524 /// Unpack low data507 /// Unpack low data
525 punpcklbw,508 unpcklbw,
526 /// Unpack low data509 /// Unpack low data
527 punpckldq,510 unpckldq,
528 /// Unpack low data511 /// Unpack low data
529 punpcklqdq,512 unpcklqdq,
530 /// Unpack low data513 /// Unpack low data
531 punpcklwd,514 unpcklwd,
532 /// Square root of double precision floating-point values
533 sqrtpd,
534 /// Square root of scalar double precision floating-point value
535 sqrtsd,
536 /// Subtract packed double-precision floating-point values
537 subpd,
538 /// Subtract scalar double-precision floating-point values
539 subsd,
540 /// Unordered compare scalar double-precision floating-point values
541 ucomisd,
542 /// Unpack and interleave high packed double-precision floating-point values
543 unpckhpd,
544 /// Unpack and interleave low packed double-precision floating-point values
545 unpcklpd,
546 /// Bitwise logical xor of packed double precision floating-point values
547 xorpd,
548515
549 /// Replicate double floating-point values516 /// Replicate double floating-point values
550 movddup,517 movddup,
...@@ -553,199 +520,32 @@ pub const Inst = struct {...@@ -553,199 +520,32 @@ pub const Inst = struct {
553 /// Replicate single floating-point values520 /// Replicate single floating-point values
554 movsldup,521 movsldup,
555522
556 /// Extract Byte
557 pextrb,
558 /// Extract Doubleword
559 pextrd,
560 /// Extract Quadword
561 pextrq,
562 /// Insert Byte
563 pinsrb,
564 /// Insert Doubleword
565 pinsrd,
566 /// Insert Quadword
567 pinsrq,
568 /// Round packed double-precision floating-point values
569 roundpd,
570 /// Round packed single-precision floating-point values523 /// Round packed single-precision floating-point values
571 roundps,
572 /// Round scalar double-precision floating-point value
573 roundsd,
574 /// Round scalar single-precision floating-point value524 /// Round scalar single-precision floating-point value
575 roundss,
576
577 /// Add packed double-precision floating-point values
578 vaddpd,
579 /// Add packed single-precision floating-point values
580 vaddps,
581 /// Add scalar double-precision floating-point values
582 vaddsd,
583 /// Add scalar single-precision floating-point values
584 vaddss,
585 /// Convert scalar double-precision floating-point value to scalar single-precision floating-point value
586 vcvtsd2ss,
587 /// Convert doubleword integer to scalar double-precision floating-point value
588 vcvtsi2sd,
589 /// Convert doubleword integer to scalar single-precision floating-point value
590 vcvtsi2ss,
591 /// Convert scalar single-precision floating-point value to scalar double-precision floating-point value
592 vcvtss2sd,
593 /// Divide packed double-precision floating-point values
594 vdivpd,
595 /// Divide packed single-precision floating-point values
596 vdivps,
597 /// Divide scalar double-precision floating-point values
598 vdivsd,
599 /// Divide scalar single-precision floating-point values
600 vdivss,
601 /// Maximum of packed double-precision floating-point values
602 vmaxpd,
603 /// Maximum of packed single-precision floating-point values
604 vmaxps,
605 /// Maximum of scalar double-precision floating-point values
606 vmaxsd,
607 /// Maximum of scalar single-precision floating-point values
608 vmaxss,
609 /// Minimum of packed double-precision floating-point values
610 vminpd,
611 /// Minimum of packed single-precision floating-point values
612 vminps,
613 /// Minimum of scalar double-precision floating-point values
614 vminsd,
615 /// Minimum of scalar single-precision floating-point values
616 vminss,
617 /// Move aligned packed double-precision floating-point values
618 vmovapd,
619 /// Move aligned packed single-precision floating-point values
620 vmovaps,
621 /// Move packed single-precision floating-point values high to low
622 vmovhlps,
623 /// Replicate double floating-point values
624 vmovddup,
625 /// Move or merge scalar double-precision floating-point value
626 vmovsd,
627 /// Replicate single floating-point values
628 vmovshdup,
629 /// Replicate single floating-point values
630 vmovsldup,
631 /// Move or merge scalar single-precision floating-point value
632 vmovss,
633 /// Move unaligned packed double-precision floating-point values
634 vmovupd,
635 /// Move unaligned packed single-precision floating-point values
636 vmovups,
637 /// Multiply packed double-precision floating-point values
638 vmulpd,
639 /// Multiply packed single-precision floating-point values
640 vmulps,
641 /// Multiply scalar double-precision floating-point values
642 vmulsd,
643 /// Multiply scalar single-precision floating-point values
644 vmulss,
645 /// Extract Byte
646 vpextrb,
647 /// Extract Doubleword
648 vpextrd,
649 /// Extract Quadword
650 vpextrq,
651 /// Extract word
652 vpextrw,
653 /// Insert Byte
654 vpinsrb,
655 /// Insert Doubleword
656 vpinsrd,
657 /// Insert Quadword
658 vpinsrq,
659 /// Insert word
660 vpinsrw,
661 /// Shuffle packed high words
662 vpshufhw,
663 /// Shuffle packed low words
664 vpshuflw,
665 /// Shift packed data right logical
666 vpsrld,
667 /// Shift packed data right logical
668 vpsrlq,
669 /// Shift packed data right logical
670 vpsrlw,
671 /// Unpack high data
672 vpunpckhbw,
673 /// Unpack high data
674 vpunpckhdq,
675 /// Unpack high data
676 vpunpckhqdq,
677 /// Unpack high data
678 vpunpckhwd,
679 /// Unpack low data
680 vpunpcklbw,
681 /// Unpack low data
682 vpunpckldq,
683 /// Unpack low data
684 vpunpcklqdq,
685 /// Unpack low data
686 vpunpcklwd,
687 /// Round packed double-precision floating-point values525 /// Round packed double-precision floating-point values
688 vroundpd,
689 /// Round packed single-precision floating-point values
690 vroundps,
691 /// Round scalar double-precision floating-point value526 /// Round scalar double-precision floating-point value
692 vroundsd,527 round,
693 /// Round scalar single-precision floating-point value
694 vroundss,
695 /// Square root of packed double-precision floating-point value
696 vsqrtpd,
697 /// Square root of packed single-precision floating-point value
698 vsqrtps,
699 /// Square root of scalar double-precision floating-point value
700 vsqrtsd,
701 /// Square root of scalar single-precision floating-point value
702 vsqrtss,
703 /// Subtract packed double-precision floating-point values
704 vsubpd,
705 /// Subtract packed single-precision floating-point values
706 vsubps,
707 /// Subtract scalar double-precision floating-point values
708 vsubsd,
709 /// Subtract scalar single-precision floating-point values
710 vsubss,
711 /// Unpack and interleave high packed double-precision floating-point values
712 vunpckhpd,
713 /// Unpack and interleave high packed single-precision floating-point values
714 vunpckhps,
715 /// Unpack and interleave low packed double-precision floating-point values
716 vunpcklpd,
717 /// Unpack and interleave low packed single-precision floating-point values
718 vunpcklps,
719528
720 /// Convert 16-bit floating-point values to single-precision floating-point values529 /// Convert 16-bit floating-point values to single-precision floating-point values
721 vcvtph2ps,530 cvtph2ps,
722 /// Convert single-precision floating-point values to 16-bit floating-point values531 /// Convert single-precision floating-point values to 16-bit floating-point values
723 vcvtps2ph,532 cvtps2ph,
724533
725 /// Fused multiply-add of packed double-precision floating-point values
726 vfmadd132pd,
727 /// Fused multiply-add of packed double-precision floating-point values
728 vfmadd213pd,
729 /// Fused multiply-add of packed double-precision floating-point values
730 vfmadd231pd,
731 /// Fused multiply-add of packed single-precision floating-point values
732 vfmadd132ps,
733 /// Fused multiply-add of packed single-precision floating-point values534 /// Fused multiply-add of packed single-precision floating-point values
734 vfmadd213ps,
735 /// Fused multiply-add of packed single-precision floating-point values
736 vfmadd231ps,
737 /// Fused multiply-add of scalar double-precision floating-point values
738 vfmadd132sd,
739 /// Fused multiply-add of scalar double-precision floating-point values
740 vfmadd213sd,
741 /// Fused multiply-add of scalar double-precision floating-point values
742 vfmadd231sd,
743 /// Fused multiply-add of scalar single-precision floating-point values535 /// Fused multiply-add of scalar single-precision floating-point values
744 vfmadd132ss,536 /// Fused multiply-add of packed double-precision floating-point values
537 /// Fused multiply-add of scalar double-precision floating-point values
538 fmadd132,
539 /// Fused multiply-add of packed single-precision floating-point values
745 /// Fused multiply-add of scalar single-precision floating-point values540 /// Fused multiply-add of scalar single-precision floating-point values
746 vfmadd213ss,541 /// Fused multiply-add of packed double-precision floating-point values
542 /// Fused multiply-add of scalar double-precision floating-point values
543 fmadd213,
544 /// Fused multiply-add of packed single-precision floating-point values
747 /// Fused multiply-add of scalar single-precision floating-point values545 /// Fused multiply-add of scalar single-precision floating-point values
748 vfmadd231ss,546 /// Fused multiply-add of packed double-precision floating-point values
547 /// Fused multiply-add of scalar double-precision floating-point values
548 fmadd231,
749549
750 /// A pseudo instruction that requires special lowering.550 /// A pseudo instruction that requires special lowering.
751 /// This should be the only tag in this enum that doesn't551 /// This should be the only tag in this enum that doesn't