authorgravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2023-03-07 20:22:45+01:00
committergravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2023-03-11 20:05:49+01:00
log219c1261a5f46636425be50fdc6e82534bb003a4
treeff067e80e5f08ab16f46d8e142ddd59f6bddfe1f
parent292f91aef2d2ed360f4dbb1f8cf6e22500a682ca

x86_64: all behavior tests passing

4 files changed, 41 insertions(+), 30 deletions(-)

src/arch/x86_64/CodeGen.zig+30-28
......@@ -2785,7 +2785,7 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type
27852785 // introduce new MIR tag specifically for mov [reg + 0], imm
27862786 const payload = try self.addExtra(Mir.ImmPair{
27872787 .dest_off = 0,
2788 .operand = @intCast(u32, imm),
2788 .operand = @truncate(u32, imm),
27892789 });
27902790 _ = try self.addInst(.{
27912791 .tag = .mov_mem_imm,
......@@ -5385,31 +5385,33 @@ fn genSetStackArg(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue) InnerE
53855385 return self.genSetStackArg(ty, stack_offset, .{ .register = reg });
53865386 },
53875387 .immediate => |imm| {
5388 _ = imm;
53885389 switch (abi_size) {
5389 1, 2, 4 => {
5390 // We have a positive stack offset value but we want a twos complement negative
5391 // offset from rbp, which is at the top of the stack frame.
5392 // mov [rbp+offset], immediate
5393 const flags: u2 = switch (abi_size) {
5394 1 => 0b00,
5395 2 => 0b01,
5396 4 => 0b10,
5397 else => unreachable,
5398 };
5399 const payload = try self.addExtra(Mir.ImmPair{
5400 .dest_off = -stack_offset,
5401 .operand = @intCast(u32, imm),
5402 });
5403 _ = try self.addInst(.{
5404 .tag = .mov_mem_imm,
5405 .ops = Mir.Inst.Ops.encode(.{
5406 .reg1 = .rsp,
5407 .flags = flags,
5408 }),
5409 .data = .{ .payload = payload },
5410 });
5411 },
5412 8 => {
5390 // TODO
5391 // 1, 2, 4 => {
5392 // // We have a positive stack offset value but we want a twos complement negative
5393 // // offset from rbp, which is at the top of the stack frame.
5394 // // mov [rbp+offset], immediate
5395 // const flags: u2 = switch (abi_size) {
5396 // 1 => 0b00,
5397 // 2 => 0b01,
5398 // 4 => 0b10,
5399 // else => unreachable,
5400 // };
5401 // const payload = try self.addExtra(Mir.ImmPair{
5402 // .dest_off = -stack_offset,
5403 // .operand = @intCast(u32, imm),
5404 // });
5405 // _ = try self.addInst(.{
5406 // .tag = .mov_mem_imm,
5407 // .ops = Mir.Inst.Ops.encode(.{
5408 // .reg1 = .rsp,
5409 // .flags = flags,
5410 // }),
5411 // .data = .{ .payload = payload },
5412 // });
5413 // },
5414 1, 2, 4, 8 => {
54135415 const reg = try self.copyToTmpRegister(ty, mcv);
54145416 return self.genSetStackArg(ty, stack_offset, MCValue{ .register = reg });
54155417 },
......@@ -5543,7 +5545,7 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue, opts: Inl
55435545 assert(ty.isError());
55445546 const payload = try self.addExtra(Mir.ImmPair{
55455547 .dest_off = -stack_offset,
5546 .operand = @intCast(u32, x_big),
5548 .operand = @truncate(u32, x_big),
55475549 });
55485550 _ = try self.addInst(.{
55495551 .tag = .mov_mem_imm,
......@@ -5557,7 +5559,7 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue, opts: Inl
55575559 1, 2, 4 => {
55585560 const payload = try self.addExtra(Mir.ImmPair{
55595561 .dest_off = -stack_offset,
5560 .operand = @intCast(u32, x_big),
5562 .operand = @truncate(u32, x_big),
55615563 });
55625564 _ = try self.addInst(.{
55635565 .tag = .mov_mem_imm,
......@@ -7020,7 +7022,7 @@ fn truncateRegister(self: *Self, ty: Type, reg: Register) !void {
70207022 .unsigned => {
70217023 const shift = @intCast(u6, max_reg_bit_width - int_info.bits);
70227024 const mask = (~@as(u64, 0)) >> shift;
7023 if (int_info.bits <= 32) {
7025 if (int_info.bits < 32) {
70247026 try self.genBinOpMir(.@"and", Type.usize, .{ .register = reg }, .{ .immediate = mask });
70257027 } else {
70267028 const tmp_reg = try self.copyToTmpRegister(Type.usize, .{ .immediate = mask });
src/arch/x86_64/Emit.zig+6-1
......@@ -612,12 +612,17 @@ fn mirArithMemImm(emit: *Emit, mnemonic: Instruction.Mnemonic, inst: Mir.Inst.In
612612 0b10 => .dword,
613613 0b11 => .qword,
614614 };
615 const imm = switch (ops.flags) {
616 0b00 => @truncate(u8, imm_pair.operand),
617 0b01 => @truncate(u16, imm_pair.operand),
618 0b10, 0b11 => @truncate(u32, imm_pair.operand),
619 };
615620 return emit.encode(mnemonic, .{
616621 .op1 = .{ .mem = Memory.sib(ptr_size, .{
617622 .disp = imm_pair.dest_off,
618623 .base = ops.reg1,
619624 }) },
620 .op2 = .{ .imm = Immediate.u(imm_pair.operand) },
625 .op2 = .{ .imm = Immediate.u(imm) },
621626 });
622627}
623628
src/arch/x86_64/Encoding.zig+4
......@@ -544,6 +544,10 @@ pub const Op = enum {
544544 }
545545 if (op.isImmediate() and target.isImmediate()) {
546546 switch (target) {
547 .imm64 => switch (op) {
548 .unity, .imm8s, .imm8, .imm16s, .imm16, .imm32s, .imm32, .imm64 => return true,
549 else => return op == target,
550 },
547551 .imm32s, .rel32 => switch (op) {
548552 .unity, .imm8s, .imm8, .imm16s, .imm16, .imm32s => return true,
549553 else => return op == target,
src/arch/x86_64/encoder.zig+1-1
......@@ -108,7 +108,7 @@ pub const Instruction = struct {
108108 .op3 = args.op3,
109109 .op4 = args.op4,
110110 })) orelse {
111 std.log.debug("{s} {s} {s} {s} {s}", .{
111 std.log.warn("{s} {s} {s} {s} {s}", .{
112112 @tagName(mnemonic),
113113 @tagName(Encoding.Op.fromOperand(args.op1)),
114114 @tagName(Encoding.Op.fromOperand(args.op2)),