From 21cc5a20440e41a0f8b53b5eeac4ba5da55b64bf Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= <alex@alexrp.com>
Date: Sun, 21 Jul 2024 14:13:37 +0200
Subject: [PATCH] std.Target: Remove the `shave` arch tag.

This was added as an architecture to LLVM's target triple parser and the Clang
driver in 2015. No backend ever materialized as far as I can see (same for GCC).
In 2016, other code referring to it started using "Myriad" instead. Ultimately,
all code related to it that isn't in the target triple parser was removed. It
seems to be a real product, just... literally no one seems to know anything
about the ISA. I figure after almost a decade with no public ISA documentation
to speak of, and no LLVM backend to reference, it's probably safe to assume that
we're not going to learn much about this ISA, making it useless for Zig.

See: https://github.com/llvm/llvm-project/commit/1b5767f72b5a037ca8f1802d737de97f8d92263d
See: https://github.com/llvm/llvm-project/commit/84a7564b28360843ee9afec5d3823c89623eb6a5
See: https://github.com/llvm/llvm-project/commit/8cfe9d8f2ad3a52ba7fd5841d3939aa810536e16
---
 lib/compiler/aro/aro/target.zig | 3 ---
 lib/std/Target.zig              | 8 --------
 src/Type.zig                    | 1 -
 src/Zcu.zig                     | 1 -
 src/codegen/llvm.zig            | 3 ---
 src/target.zig                  | 1 -
 6 files changed, 17 deletions(-)

diff --git a/lib/compiler/aro/aro/target.zig b/lib/compiler/aro/aro/target.zig
index 82dc3af430499ab9c69dfb5de425724283e53734..ed729c14565b2457b558db97c897237133d872ad 100644
--- a/lib/compiler/aro/aro/target.zig
+++ b/lib/compiler/aro/aro/target.zig
@@ -482,7 +482,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
         .nvptx,
         .spir,
         .kalimba,
-        .shave,
         .lanai,
         .wasm32,
         .aarch64_32,
@@ -522,7 +521,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
         .lanai,
         .m68k,
         .msp430,
-        .shave,
         .sparcel,
         .spu_2,
         .tce,
@@ -628,7 +626,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
         .spirv32 => "spirv32",
         .spirv64 => "spirv64",
         .kalimba => "kalimba",
-        .shave => "shave",
         .lanai => "lanai",
         .wasm32 => "wasm32",
         .wasm64 => "wasm64",
diff --git a/lib/std/Target.zig b/lib/std/Target.zig
index c69a730b2e32624a213d4a7dbfa0bd58243b1d08..a545f0d038cfff36531384c90c69f36df469964f 100644
--- a/lib/std/Target.zig
+++ b/lib/std/Target.zig
@@ -1017,7 +1017,6 @@ pub const Cpu = struct {
         spirv32,
         spirv64,
         kalimba,
-        shave,
         lanai,
         wasm32,
         wasm64,
@@ -1154,7 +1153,6 @@ pub const Cpu = struct {
                 .nvptx => .NONE,
                 .spir => .NONE,
                 .kalimba => .CSR_KALIMBA,
-                .shave => .NONE,
                 .lanai => .LANAI,
                 .wasm32 => .NONE,
                 .aarch64_32 => .AARCH64,
@@ -1211,7 +1209,6 @@ pub const Cpu = struct {
                 .nvptx => .Unknown,
                 .spir => .Unknown,
                 .kalimba => .Unknown,
-                .shave => .Unknown,
                 .lanai => .Unknown,
                 .wasm32 => .Unknown,
                 .aarch64_32 => .ARM64,
@@ -1273,7 +1270,6 @@ pub const Cpu = struct {
                 .thumb,
                 .spir,
                 .spir64,
-                .shave,
                 .ve,
                 .spu_2,
                 // GPU bitness is opaque. For now, assume little endian.
@@ -1759,7 +1755,6 @@ pub const DynamicLinker = struct {
                 .spir,
                 .spir64,
                 .kalimba,
-                .shave,
                 .lanai,
                 .ve,
                 .dxil,
@@ -1860,7 +1855,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
         .nvptx,
         .spir,
         .kalimba,
-        .shave,
         .lanai,
         .wasm32,
         .aarch64_32,
@@ -2381,7 +2375,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
             .spir,
             .spirv32,
             .kalimba,
-            .shave,
             .ve,
             .spu_2,
             .xtensa,
@@ -2493,7 +2486,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
             .spir,
             .spirv32,
             .kalimba,
-            .shave,
             .ve,
             .spu_2,
             .xtensa,
diff --git a/src/Type.zig b/src/Type.zig
index 411e2426289449e5262bf774a3b231bdb03060c3..1428d6c15f062f67164e8f73bd2f82603ff118cd 100644
--- a/src/Type.zig
+++ b/src/Type.zig
@@ -1654,7 +1654,6 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 {
         .kalimba,
         .spirv,
         .spirv32,
-        .shave,
         .spir64,
         .ve,
         .spirv64,
diff --git a/src/Zcu.zig b/src/Zcu.zig
index 8d1d2a5130dd3076da0edeef1dd2e86ad636aaac..825da89b147c7ccd4b1847f909f8934d7eca3263 100644
--- a/src/Zcu.zig
+++ b/src/Zcu.zig
@@ -3258,7 +3258,6 @@ pub fn atomicPtrAlignment(
         .spir,
         .kalimba,
         .lanai,
-        .shave,
         .wasm32,
         .csky,
         .spirv32,
diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig
index 90a5d4bf62e1815e58d613626c2f78b25dbf00c3..802141892a4ed247facb0010792b82638ec50eb8 100644
--- a/src/codegen/llvm.zig
+++ b/src/codegen/llvm.zig
@@ -88,7 +88,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
         .spirv32 => "spirv32",
         .spirv64 => "spirv64",
         .kalimba => "kalimba",
-        .shave => "shave",
         .lanai => "lanai",
         .wasm32 => "wasm32",
         .wasm64 => "wasm64",
@@ -305,7 +304,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {
         .spirv32 => .spirv32,
         .spirv64 => .spirv64,
         .kalimba => .kalimba,
-        .shave => .shave,
         .lanai => .lanai,
         .wasm32 => .wasm32,
         .wasm64 => .wasm64,
@@ -12080,7 +12078,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
         // LLVM backends that have no initialization functions.
         .tce,
         .tcele,
-        .shave,
         .spir,
         .spir64,
         .spirv,
diff --git a/src/target.zig b/src/target.zig
index dce8cab7b499b556685fa82aef4f6080ab9ad3fe..89e6069e216ad751a10370f4eff3c33e66bc9a49 100644
--- a/src/target.zig
+++ b/src/target.zig
@@ -158,7 +158,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
         .spirv32,
         .spirv64,
         .kalimba,
-        .shave,
         .lanai,
         .wasm32,
         .wasm64,
-- 
2.54.0