diff --git a/lib/std/zig/system/arm.zig b/lib/std/zig/system/arm.zig index a02e6167da0d717647332d56944d377af7381c61..697688b113cde9ccc56b5afff57abb6f88aa297b 100644 --- a/lib/std/zig/system/arm.zig +++ b/lib/std/zig/system/arm.zig @@ -279,6 +279,33 @@ pub const aarch64 = struct { return cpu; } + /// Input array should consist of readouts from 12 system registers such that: + /// 0 -> ID_AA64PFR0_EL1 + /// 1 -> ID_AA64PFR1_EL1 + /// 2 -> ID_AA64DFR0_EL1 + /// 3 -> ID_AA64DFR1_EL1 + /// 4 -> ID_AA64AFR0_EL1 + /// 5 -> ID_AA64AFR1_EL1 + /// 6 -> ID_AA64ISAR0_EL1 + /// 7 -> ID_AA64ISAR1_EL1 + /// 8 -> ID_AA64MMFR0_EL1 + /// 9 -> ID_AA64MMFR1_EL1 + /// 10 -> ID_AA64MMFR2_EL1 + pub fn detectNativeFeatures(arch: Target.Cpu.Arch, model: *const Target.Cpu.Model, registers: [11]u64) Target.Cpu { + var cpu: Target.Cpu = .{ + .arch = arch, + .model = model, + .features = model.features, + }; + + detectNativeCpuFeatures(&cpu, registers[0..]); + addInstructionFusions(&cpu); + + cpu.features.populateDependencies(cpu.arch.allFeaturesList()); + + return cpu; + } + /// Takes readout of MIDR_EL1 register as input. fn detectNativeCoreInfo(midr: u64) CoreInfo { var info = CoreInfo{ diff --git a/lib/std/zig/system/openbsd.zig b/lib/std/zig/system/openbsd.zig index 3b4fe7649f69bc936c5333aded849911a1218dbc..6549cd906055ab09243290288c17793cc7e779e1 100644 --- a/lib/std/zig/system/openbsd.zig +++ b/lib/std/zig/system/openbsd.zig @@ -22,6 +22,77 @@ fn hwModelName(buf: [:0]u8) ?[:0]const u8 { } const aarch64 = struct { + const models = .{ + .{ "Ampere AmpereOne AC03", &std.Target.aarch64.cpu.ampere1 }, + .{ "Ampere AmpereOne AC04", &std.Target.aarch64.cpu.ampere1a }, + .{ "Apple Icestorm Max", &std.Target.aarch64.cpu.apple_m1 }, + .{ "Apple Icestorm Pro", &std.Target.aarch64.cpu.apple_m1 }, + .{ "Apple Icestorm", &std.Target.aarch64.cpu.apple_m1 }, + .{ "Apple Firestorm Max", &std.Target.aarch64.cpu.apple_m1 }, + .{ "Apple Firestorm Pro", &std.Target.aarch64.cpu.apple_m1 }, + .{ "Apple Firestorm", &std.Target.aarch64.cpu.apple_m1 }, + .{ "Apple Blizzard Max", &std.Target.aarch64.cpu.apple_m2 }, + .{ "Apple Blizzard Pro", &std.Target.aarch64.cpu.apple_m2 }, + .{ "Apple Blizzard", &std.Target.aarch64.cpu.apple_m2 }, + .{ "Apple Avalanche Max", &std.Target.aarch64.cpu.apple_m2 }, + .{ "Apple Avalanche Pro", &std.Target.aarch64.cpu.apple_m2 }, + .{ "Apple Avalanche", &std.Target.aarch64.cpu.apple_m2 }, + .{ "Applied Micro X-Gene", &std.Target.aarch64.cpu.xgene1 }, + // TODO: Add these with LLVM 23. + // .{ "ARM C1-Nano", &std.Target.aarch64.cpu.c1_nano }, + // .{ "ARM C1-Pro", &std.Target.aarch64.cpu.c1_pro }, + // .{ "ARM C1-Ultra", &std.Target.aarch64.cpu.c1_ultra }, + // .{ "ARM C1-Premium", &std.Target.aarch64.cpu.c1_premium }, + .{ "ARM Cortex-A320", &std.Target.aarch64.cpu.cortex_a320 }, + .{ "ARM Cortex-A34", &std.Target.aarch64.cpu.cortex_a34 }, + .{ "ARM Cortex-A35", &std.Target.aarch64.cpu.cortex_a35 }, + .{ "ARM Cortex-A510", &std.Target.aarch64.cpu.cortex_a510 }, + .{ "ARM Cortex-A520AE", &std.Target.aarch64.cpu.cortex_a520ae }, + .{ "ARM Cortex-A520", &std.Target.aarch64.cpu.cortex_a520 }, + .{ "ARM Cortex-A53", &std.Target.aarch64.cpu.cortex_a53 }, + .{ "ARM Cortex-A55", &std.Target.aarch64.cpu.cortex_a55 }, + .{ "ARM Cortex-A57", &std.Target.aarch64.cpu.cortex_a57 }, + .{ "ARM Cortex-A65AE", &std.Target.aarch64.cpu.cortex_a65ae }, + .{ "ARM Cortex-A65", &std.Target.aarch64.cpu.cortex_a65 }, + .{ "ARM Cortex-A710", &std.Target.aarch64.cpu.cortex_a710 }, + .{ "ARM Cortex-A715", &std.Target.aarch64.cpu.cortex_a715 }, + .{ "ARM Cortex-A720AE", &std.Target.aarch64.cpu.cortex_a720ae }, + .{ "ARM Cortex-A720", &std.Target.aarch64.cpu.cortex_a720 }, + .{ "ARM Cortex-A725", &std.Target.aarch64.cpu.cortex_a725 }, + .{ "ARM Cortex-A72", &std.Target.aarch64.cpu.cortex_a72 }, + .{ "ARM Cortex-A73", &std.Target.aarch64.cpu.cortex_a73 }, + .{ "ARM Cortex-A75", &std.Target.aarch64.cpu.cortex_a75 }, + .{ "ARM Cortex-A76AE", &std.Target.aarch64.cpu.cortex_a76ae }, + .{ "ARM Cortex-A76", &std.Target.aarch64.cpu.cortex_a76 }, + .{ "ARM Cortex-A77", &std.Target.aarch64.cpu.cortex_a77 }, + .{ "ARM Cortex-A78AE", &std.Target.aarch64.cpu.cortex_a78ae }, + .{ "ARM Cortex-A78C", &std.Target.aarch64.cpu.cortex_a78c }, + .{ "ARM Cortex-A78", &std.Target.aarch64.cpu.cortex_a78 }, + .{ "ARM Cortex-X1C", &std.Target.aarch64.cpu.cortex_x1c }, + .{ "ARM Cortex-X1", &std.Target.aarch64.cpu.cortex_x1 }, + .{ "ARM Cortex-X2", &std.Target.aarch64.cpu.cortex_x2 }, + .{ "ARM Cortex-X3", &std.Target.aarch64.cpu.cortex_x3 }, + .{ "ARM Cortex-X4", &std.Target.aarch64.cpu.cortex_x4 }, + .{ "ARM Cortex-X925", &std.Target.aarch64.cpu.cortex_x925 }, + .{ "ARM Neoverse E1", &std.Target.aarch64.cpu.neoverse_e1 }, + .{ "ARM Neoverse N1", &std.Target.aarch64.cpu.neoverse_n1 }, + .{ "ARM Neoverse N2", &std.Target.aarch64.cpu.neoverse_n2 }, + .{ "ARM Neoverse N3", &std.Target.aarch64.cpu.neoverse_n3 }, + .{ "ARM Neoverse V1", &std.Target.aarch64.cpu.neoverse_v1 }, + .{ "ARM Neoverse V2", &std.Target.aarch64.cpu.neoverse_v2 }, + .{ "ARM Neoverse V3AE", &std.Target.aarch64.cpu.neoverse_v3ae }, + .{ "ARM Neoverse V3", &std.Target.aarch64.cpu.neoverse_v3 }, + .{ "Cavium ThunderX T81", &std.Target.aarch64.cpu.thunderxt81 }, + .{ "Cavium ThunderX T83", &std.Target.aarch64.cpu.thunderxt83 }, + .{ "Cavium ThunderX T88", &std.Target.aarch64.cpu.thunderxt88 }, + .{ "Cavium ThunderX2 T99", &std.Target.aarch64.cpu.thunderx2t99 }, + .{ "Microsoft Azure Cobalt 100", &std.Target.aarch64.cpu.cobalt_100 }, + .{ "NVIDIA Olympus", &std.Target.aarch64.cpu.olympus }, + .{ "Qualcomm Kryo 400 Gold", &std.Target.aarch64.cpu.cortex_a76 }, + .{ "Qualcomm Kryo 400 Silver", &std.Target.aarch64.cpu.cortex_a55 }, + .{ "Qualcomm Oryon", &std.Target.aarch64.cpu.oryon_1 }, + }; + fn sysctlReg(key: c_int) ?u64 { const mib: [2]c_int = [_]c_int{ std.c.CTL.MACHDEP, @@ -42,8 +113,18 @@ const aarch64 = struct { } fn detectNativeCpuAndFeatures(arch: std.Target.Cpu.Arch) ?std.Target.Cpu { - const registers = [12]u64{ - 0, // MIDR_EL1 + const model: *const std.Target.Cpu.Model = blk: { + var buf: [64:0]u8 = undefined; + const name = hwModelName(&buf) orelse return null; + + inline for (models) |pair| { + if (std.mem.startsWith(u8, name, pair[0])) break :blk pair[1]; + } + + break :blk .generic(arch); + }; + + const registers = [11]u64{ sysctlReg(std.c.CPU.AA64PFR0) orelse return null, sysctlReg(std.c.CPU.AA64PFR1) orelse return null, 0, // ID_AA64DFR0_EL1 @@ -57,7 +138,7 @@ const aarch64 = struct { sysctlReg(std.c.CPU.ID_AA64MMFR2) orelse return null, }; - return @import("arm.zig").aarch64.detectNativeCpuAndFeatures(arch, registers); + return @import("arm.zig").aarch64.detectNativeFeatures(arch, model, registers); } };