diff --git a/lib/std/debug/SelfInfo/MachO.zig b/lib/std/debug/SelfInfo/MachO.zig index 59b9a524b01d4f68d5b8854d1b64d70bbb4fba9f..f68572d1ca07fab3f0a9249f1bdf42c85ba9ee2e 100644 --- a/lib/std/debug/SelfInfo/MachO.zig +++ b/lib/std/debug/SelfInfo/MachO.zig @@ -426,10 +426,10 @@ fn unwindFrameInner(si: *SelfInfo, io: Io, context: *UnwindContext) !usize { var reg_addr = fp - @sizeOf(usize); inline for (@typeInfo(@TypeOf(frame.x_reg_pairs)).@"struct".field_names, 0..) |field_name, i| { if (@field(frame.x_reg_pairs, field_name) != 0) { - (try dwarfRegNative(&context.cpu_state, 19 + i)).* = @as(*const usize, @ptrFromInt(reg_addr)).*; - reg_addr += @sizeOf(usize); - (try dwarfRegNative(&context.cpu_state, 20 + i)).* = @as(*const usize, @ptrFromInt(reg_addr)).*; - reg_addr += @sizeOf(usize); + (try dwarfRegNative(&context.cpu_state, 19 + i * 2)).* = @as(*const usize, @ptrFromInt(reg_addr)).*; + reg_addr -= @sizeOf(usize); + (try dwarfRegNative(&context.cpu_state, 20 + i * 2)).* = @as(*const usize, @ptrFromInt(reg_addr)).*; + reg_addr -= @sizeOf(usize); } } @@ -437,7 +437,7 @@ fn unwindFrameInner(si: *SelfInfo, io: Io, context: *UnwindContext) !usize { // vector registers in the AArch64 `cpu_context` anyway, so there's no reason to // fail a legitimate unwind just because we're asked to restore the registers here. // If some weird/broken unwind info tells us to read them later, we will fail then. - reg_addr += 16 * @as(usize, @popCount(@as(u4, @bitCast(frame.d_reg_pairs)))); + reg_addr -= 16 * @as(usize, @popCount(@as(u4, @bitCast(frame.d_reg_pairs)))); const new_ip = @as(*const usize, @ptrFromInt(ip_ptr)).*; const new_fp = @as(*const usize, @ptrFromInt(fp)).*;