| ... | ... | @@ -1850,11 +1850,33 @@ fn asmRegisterMemoryImmediate( |
| 1850 | 1850 | m: Memory, |
| 1851 | 1851 | imm: Immediate, |
| 1852 | 1852 | ) !void { |
| 1853 | | if (switch (imm) { |
| 1853 | if (reg.size() == .qword and tag[1] == .mul) { |
| 1854 | // imul does not support imm16 for RMI r64, r/m64 |
| 1855 | const payload = try self.addExtra(Mir.Imm32{ .imm = switch (imm) { |
| 1856 | .signed => |s| @bitCast(s), |
| 1857 | .unsigned => |u| @as(u32, @intCast(u)), |
| 1858 | .nav, .uav, .lazy_sym, .extern_func => unreachable, |
| 1859 | } }); |
| 1860 | assert(payload + 1 == try self.addExtra(Mir.Memory.encode(m))); |
| 1861 | _ = try self.addInst(.{ |
| 1862 | .tag = tag[1], |
| 1863 | .ops = switch (imm) { |
| 1864 | .signed => .rmi_s, |
| 1865 | .unsigned => .rmi_u, |
| 1866 | .nav, .uav, .lazy_sym, .extern_func => unreachable, |
| 1867 | }, |
| 1868 | .data = .{ .rx = .{ |
| 1869 | .fixes = tag[0], |
| 1870 | .r1 = reg, |
| 1871 | .payload = payload, |
| 1872 | } }, |
| 1873 | }); |
| 1874 | } else if (switch (imm) { |
| 1854 | 1875 | .signed => |s| if (std.math.cast(i16, s)) |x| @as(u16, @bitCast(x)) else null, |
| 1855 | 1876 | .unsigned => |u| std.math.cast(u16, u), |
| 1856 | 1877 | .nav, .uav, .lazy_sym, .extern_func => unreachable, |
| 1857 | 1878 | }) |small_imm| { |
| 1879 | // This is only valid for imul RMI r16, r/m16 |
| 1858 | 1880 | _ = try self.addInst(.{ |
| 1859 | 1881 | .tag = tag[1], |
| 1860 | 1882 | .ops = .rmi, |
Mathieu Suen <mathieusuen@yahoo.fr> 2026-02-16 10:29:26+01:00
Matthew Lugg <mlugg@mlugg.co.uk> 2026-04-10 23:23:33+02:00
src