authorgravatar for david@vortan.devDavid Rubin <david@vortan.dev> 2025-11-27 17:43:15-08:00
committergravatar for sinon@vortan.devDavid Rubin <sinon@vortan.dev> 2026-06-24 02:12:43-05:00
log2e1b1728505c20ee38d2bd757148e572e4d95f74
tree45f606e9ff24ca96c5be43d282ea1f6ca95f30aa
parent874b6e39db08f66bb0f702d2177b91535b2a8a02

codegen: fix x86-64 backend crc32 inline asm

3 files changed, 6 insertions(+), 2 deletions(-)

lib/std/hash/crc.zig+1-1
...@@ -14,7 +14,7 @@ test {...@@ -14,7 +14,7 @@ test {
14 _ = @import("crc/test.zig");14 _ = @import("crc/test.zig");
15}15}
1616
17pub const Crc32Iscsi = switch (builtin.cpu.hasAll(.x86, &.{ .@"64bit", .crc32 }) and builtin.zig_backend == .stage2_llvm) {17pub const Crc32Iscsi = switch (builtin.cpu.hasAll(.x86, &.{ .@"64bit", .crc32 })) {
18 true => @import("crc/Crc32c.zig"),18 true => @import("crc/Crc32c.zig"),
19 else => Crc(u32, .{19 else => Crc(u32, .{
20 .polynomial = 0x1edc6f41,20 .polynomial = 0x1edc6f41,
src/codegen/x86_64/CodeGen.zig+4
...@@ -178018,6 +178018,10 @@ fn airAsm(self: *CodeGen, inst: Air.Inst.Index) !void {...@@ -178018,6 +178018,10 @@ fn airAsm(self: *CodeGen, inst: Air.Inst.Index) !void {
178018 fixed_mnem_size: {178018 fixed_mnem_size: {
178019 const fixed_mnem_size: Memory.Size = switch (mnem_tag) {178019 const fixed_mnem_size: Memory.Size = switch (mnem_tag) {
178020 .clflush => .byte,178020 .clflush => .byte,
178021 .crc32 => {
178022 mnem_size.op_has_size.unset(1);
178023 break :fixed_mnem_size;
178024 },
178021 .fldcw, .fnstcw, .fstcw, .fnstsw, .fstsw => .word,178025 .fldcw, .fnstcw, .fstcw, .fnstsw, .fstsw => .word,
178022 .fldenv, .fnstenv, .fstenv => .none,178026 .fldenv, .fnstenv, .fstenv => .none,
178023 .frstor, .fsave, .fnsave, .fxrstor, .fxrstor64, .fxsave, .fxsave64 => .none,178027 .frstor, .fsave, .fnsave, .fxrstor, .fxrstor64, .fxsave, .fxsave64 => .none,
tools/update_crc_catalog.zig+1-1
...@@ -53,7 +53,7 @@ fn @"i like cheese"(arena: std.mem.Allocator, io: Io, args: []const []const u8)...@@ -53,7 +53,7 @@ fn @"i like cheese"(arena: std.mem.Allocator, io: Io, args: []const []const u8)
53 \\ _ = @import("crc/test.zig");53 \\ _ = @import("crc/test.zig");
54 \\}54 \\}
55 \\55 \\
56 \\pub const Crc32Iscsi = switch (builtin.cpu.hasAll(.x86, &.{ .@"64bit", .crc32 }) and builtin.zig_backend == .stage2_llvm) {56 \\pub const Crc32Iscsi = switch (builtin.cpu.hasAll(.x86, &.{ .@"64bit", .crc32 })) {
57 \\ true => @import("crc/Crc32c.zig"),57 \\ true => @import("crc/Crc32c.zig"),
58 \\ else => Crc(u32, .{58 \\ else => Crc(u32, .{
59 \\ .polynomial = 0x1edc6f41,59 \\ .polynomial = 0x1edc6f41,