| ... | ... | @@ -6,6 +6,7 @@ |
| 6 | 6 | //! * aarch64 |
| 7 | 7 | //! * arm |
| 8 | 8 | //! * i386 |
| 9 | //! * hexagon |
| 9 | 10 | //! * loongarch64 |
| 10 | 11 | //! * mips |
| 11 | 12 | //! * mips64 |
| ... | ... | @@ -27,6 +28,7 @@ |
| 27 | 28 | //! - `-DARCH_aarch64` |
| 28 | 29 | //! - `-DARCH_arm` |
| 29 | 30 | //! - `-DARCH_i386` |
| 31 | //! - `-DARCH_hexagon` |
| 30 | 32 | //! - `-DARCH_loongarch64` |
| 31 | 33 | //! - `-DARCH_mips` |
| 32 | 34 | //! - `-DARCH_mips64` |
| ... | ... | @@ -41,6 +43,7 @@ |
| 41 | 43 | //! * One of the following, corresponding to the CPU architecture family: |
| 42 | 44 | //! - `-DFAMILY_aarch64` |
| 43 | 45 | //! - `-DFAMILY_arm` |
| 46 | //! - `-DFAMILY_hexagon` |
| 44 | 47 | //! - `-DFAMILY_loongarch` |
| 45 | 48 | //! - `-DFAMILY_mips` |
| 46 | 49 | //! - `-DFAMILY_powerpc` |
| ... | ... | @@ -63,6 +66,7 @@ const Arch = enum { |
| 63 | 66 | aarch64, |
| 64 | 67 | arm, |
| 65 | 68 | i386, |
| 69 | hexagon, |
| 66 | 70 | loongarch64, |
| 67 | 71 | mips, |
| 68 | 72 | mips64, |
| ... | ... | @@ -77,6 +81,7 @@ const Arch = enum { |
| 77 | 81 | pub fn ptrSize(arch: Arch) u16 { |
| 78 | 82 | return switch (arch) { |
| 79 | 83 | .arm, |
| 84 | .hexagon, |
| 80 | 85 | .i386, |
| 81 | 86 | .mips, |
| 82 | 87 | .mipsn32, |
| ... | ... | @@ -112,6 +117,7 @@ const Arch = enum { |
| 112 | 117 | .aarch64 => .aarch64, |
| 113 | 118 | .arm => .arm, |
| 114 | 119 | .i386, .x86_64 => .x86, |
| 120 | .hexagon => .hexagon, |
| 115 | 121 | .loongarch64 => .loongarch, |
| 116 | 122 | .mips, .mips64, .mipsn32 => .mips, |
| 117 | 123 | .powerpc, .powerpc64 => .powerpc, |
| ... | ... | @@ -124,6 +130,7 @@ const Arch = enum { |
| 124 | 130 | const Family = enum { |
| 125 | 131 | aarch64, |
| 126 | 132 | arm, |
| 133 | hexagon, |
| 127 | 134 | loongarch, |
| 128 | 135 | mips, |
| 129 | 136 | powerpc, |