Commit 32ab930f1d39c374265ae14f1de9d837dcd7f650 | zig

author	Jacob Young <jacobly@ziglang.org> 2023-05-05 01:32:39-04:00
committer	Jacob Young <jacobly@ziglang.org> 2023-05-08 07:36:19-04:00
log	32ab930f1d39c374265ae14f1de9d837dcd7f650
tree	de2c98994005aff92160f41b1b62a013613b8902
parent	1a261917ce41efb49fe41ea0c6d9083212c17797

x86_64: implement f16 conversions when supported

7 files changed, 1151 insertions(+), 927 deletions(-)

src
- arch
  - x86_64
    CodeGen.zig
    Encoding.zig
    Lower.zig
    Mir.zig
    encoder.zig
    encodings.zig
test
- behavior
  - vector.zig

src/arch/x86_64/CodeGen.zig+49-17

 @@ -2172,12 +2172,9 @@ fn airRetPtr(self: *Self, inst: Air.Inst.Index) !void {
 fn airFptrunc(self: *Self, inst: Air.Inst.Index) !void {
     const ty_op = self.air.instructions.items(.data)[inst].ty_op;
     const dst_ty = self.air.typeOfIndex(inst);
+    const dst_bits = dst_ty.floatBits(self.target.*);
     const src_ty = self.air.typeOf(ty_op.operand);
-    if (dst_ty.floatBits(self.target.*) != 32 or src_ty.floatBits(self.target.*) != 64 or
+    const src_bits = src_ty.floatBits(self.target.*);
-        !Target.x86.featureSetHas(self.target.cpu.features, .sse2))
-        return self.fail("TODO implement airFptrunc from {} to {}", .{
-            src_ty.fmt(self.bin_file.options.module.?), dst_ty.fmt(self.bin_file.options.module.?),
-        });
     const src_mcv = try self.resolveInst(ty_op.operand);
     const dst_mcv = if (src_mcv.isRegister() and self.reuseOperand(inst, ty_op.operand, 0, src_mcv))
 @@ -2187,19 +2184,32 @@ fn airFptrunc(self: *Self, inst: Air.Inst.Index) !void {
     const dst_lock = self.register_manager.lockReg(dst_mcv.register);
     defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);
-    try self.genBinOpMir(.cvtsd2ss, src_ty, dst_mcv, src_mcv);
+    if (src_bits == 32 and dst_bits == 16 and self.hasFeature(.f16c))
+        try self.asmRegisterRegisterImmediate(
+            .vcvtps2ph,
+            dst_mcv.register,
+            if (src_mcv.isRegister()) src_mcv.getReg().? else src_reg: {
+                const src_reg = dst_mcv.register;
+                try self.genSetReg(src_reg, src_ty, src_mcv);
+                break :src_reg src_reg;
+            },
+            Immediate.u(0b1_00),
+        )
+    else if (src_bits == 64 and dst_bits == 32)
+        try self.genBinOpMir(.cvtsd2ss, src_ty, dst_mcv, src_mcv)
+    else
+        return self.fail("TODO implement airFptrunc from {} to {}", .{
+            src_ty.fmt(self.bin_file.options.module.?), dst_ty.fmt(self.bin_file.options.module.?),
+        });
     return self.finishAir(inst, dst_mcv, .{ ty_op.operand, .none, .none });
 }
 fn airFpext(self: *Self, inst: Air.Inst.Index) !void {
     const ty_op = self.air.instructions.items(.data)[inst].ty_op;
     const dst_ty = self.air.typeOfIndex(inst);
+    const dst_bits = dst_ty.floatBits(self.target.*);
     const src_ty = self.air.typeOf(ty_op.operand);
-    if (dst_ty.floatBits(self.target.*) != 64 or src_ty.floatBits(self.target.*) != 32 or
+    const src_bits = src_ty.floatBits(self.target.*);
-        !Target.x86.featureSetHas(self.target.cpu.features, .sse2))
-        return self.fail("TODO implement airFpext from {} to {}", .{
-            src_ty.fmt(self.bin_file.options.module.?), dst_ty.fmt(self.bin_file.options.module.?),
-        });
     const src_mcv = try self.resolveInst(ty_op.operand);
     const dst_mcv = if (src_mcv.isRegister() and self.reuseOperand(inst, ty_op.operand, 0, src_mcv))
 @@ -2209,7 +2219,19 @@ fn airFpext(self: *Self, inst: Air.Inst.Index) !void {
     const dst_lock = self.register_manager.lockReg(dst_mcv.register);
     defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);
-    try self.genBinOpMir(.cvtss2sd, src_ty, dst_mcv, src_mcv);
+    try self.genBinOpMir(
+        if (src_bits == 16 and dst_bits == 32 and self.hasFeature(.f16c))
+            .vcvtph2ps
+        else if (src_bits == 32 and dst_bits == 64)
+            .cvtss2sd
+        else
+            return self.fail("TODO implement airFpext from {} to {}", .{
+                src_ty.fmt(self.bin_file.options.module.?), dst_ty.fmt(self.bin_file.options.module.?),
+            }),
+        src_ty,
+        dst_mcv,
+        src_mcv,
+    );
     return self.finishAir(inst, dst_mcv, .{ ty_op.operand, .none, .none });
 }
 @@ -3802,7 +3824,7 @@ fn airClz(self: *Self, inst: Air.Inst.Index) !void {
         defer self.register_manager.unlockReg(dst_lock);
         const src_bits = src_ty.bitSize(self.target.*);
-        if (Target.x86.featureSetHas(self.target.cpu.features, .lzcnt)) {
+        if (self.hasFeature(.lzcnt)) {
             if (src_bits <= 64) {
                 try self.genBinOpMir(.lzcnt, src_ty, dst_mcv, mat_src_mcv);
 @@ -3888,7 +3910,7 @@ fn airCtz(self: *Self, inst: Air.Inst.Index) !void {
         const dst_lock = self.register_manager.lockReg(dst_reg);
         defer if (dst_lock) |lock| self.register_manager.unlockReg(lock);
-        if (Target.x86.featureSetHas(self.target.cpu.features, .bmi)) {
+        if (self.hasFeature(.bmi)) {
             if (src_bits <= 64) {
                 const extra_bits = self.regExtraBits(src_ty);
                 const masked_mcv = if (extra_bits > 0) masked: {
 @@ -3956,7 +3978,7 @@ fn airPopcount(self: *Self, inst: Air.Inst.Index) !void {
         const src_abi_size = @intCast(u32, src_ty.abiSize(self.target.*));
         const src_mcv = try self.resolveInst(ty_op.operand);
-        if (Target.x86.featureSetHas(self.target.cpu.features, .popcnt)) {
+        if (self.hasFeature(.popcnt)) {
             const mat_src_mcv = switch (src_mcv) {
                 .immediate => MCValue{ .register = try self.copyToTmpRegister(src_ty, src_mcv) },
                 else => src_mcv,
 @@ -4309,7 +4331,7 @@ fn airRound(self: *Self, inst: Air.Inst.Index, mode: Immediate) !void {
     const un_op = self.air.instructions.items(.data)[inst].un_op;
     const ty = self.air.typeOf(un_op);
-    if (!Target.x86.featureSetHas(self.target.cpu.features, .sse4_1))
+    if (!self.hasFeature(.sse4_1))
         return self.fail("TODO implement airRound without sse4_1 feature", .{});
     const src_mcv = try self.resolveInst(un_op);
 @@ -5712,7 +5734,7 @@ fn genBinOp(
                 => {},
                 .div_trunc,
                 .div_floor,
-                => if (Target.x86.featureSetHas(self.target.cpu.features, .sse4_1)) {
+                => if (self.hasFeature(.sse4_1)) {
                     const abi_size = @intCast(u32, lhs_ty.abiSize(self.target.*));
                     const dst_alias = registerAlias(dst_mcv.register, abi_size);
                     try self.asmRegisterRegisterImmediate(switch (lhs_ty.floatBits(self.target.*)) {
 @@ -9593,3 +9615,13 @@ fn regBitSize(self: *Self, ty: Type) u64 {
 fn regExtraBits(self: *Self, ty: Type) u64 {
     return self.regBitSize(ty) - ty.bitSize(self.target.*);
 }
+fn hasFeature(self: *Self, feature: Target.x86.Feature) bool {
+    return Target.x86.featureSetHas(self.target.cpu.features, feature);
+}
+fn hasAnyFeatures(self: *Self, features: anytype) bool {
+    return Target.x86.featureSetHasAny(self.target.cpu.features, features);
+}
+fn hasAllFeatures(self: *Self, features: anytype) bool {
+    return Target.x86.featureSetHasAll(self.target.cpu.features, features);
+}

src/arch/x86_64/Encoding.zig+72-23

 @@ -23,6 +23,7 @@ const Data = struct {
     opc: [7]u8,
     modrm_ext: u3,
     mode: Mode,
+    feature: Feature,
 };
 pub fn findByMnemonic(
 @@ -58,7 +59,7 @@ pub fn findByMnemonic(
     next: for (mnemonic_to_encodings_map[@enumToInt(mnemonic)]) |data| {
         switch (data.mode) {
             .rex => if (!rex_required) continue,
-            .long, .sse_long, .sse2_long => {},
+            .long => {},
             else => if (rex_required) continue,
         }
         for (input_ops, data.ops) |input_op, data_op|
 @@ -136,22 +137,20 @@ pub fn modRmExt(encoding: Encoding) u3 {
 }
 pub fn operandBitSize(encoding: Encoding) u64 {
-    switch (encoding.data.mode) {
+    return switch (encoding.data.mode) {
-        .short => return 16,
+        .short => 16,
-        .long, .sse_long, .sse2_long => return 64,
+        .long => 64,
-        else => {},
+        else => switch (encoding.data.op_en) {
-    }
+            .np => switch (encoding.data.ops[0]) {
-    const bit_size: u64 = switch (encoding.data.op_en) {
+                .o16 => 16,
-        .np => switch (encoding.data.ops[0]) {
+                .o32 => 32,
-            .o16 => 16,
+                .o64 => 64,
-            .o32 => 32,
+                else => 32,
-            .o64 => 64,
+            },
-            else => 32,
+            .td => encoding.data.ops[1].bitSize(),
+            else => encoding.data.ops[0].bitSize(),
         },
-        .td => encoding.data.ops[1].bitSize(),
-        else => encoding.data.ops[0].bitSize(),
     };
-    return bit_size;
 }
 pub fn format(
 @@ -162,12 +161,50 @@ pub fn format(
 ) !void {
     _ = options;
     _ = fmt;
+    var opc = encoding.opcode();
     switch (encoding.data.mode) {
-        .long, .sse_long, .sse2_long => try writer.writeAll("REX.W + "),
         else => {},
+        .long => try writer.writeAll("REX.W + "),
+        .vex_128, .vex_128_long, .vex_256, .vex_256_long => {
+            try writer.writeAll("VEX.");
+            switch (encoding.data.mode) {
+                .vex_128, .vex_128_long => try writer.writeAll("128"),
+                .vex_256, .vex_256_long => try writer.writeAll("256"),
+                else => unreachable,
+            }
+            switch (opc[0]) {
+                else => {},
+                0x66, 0xf3, 0xf2 => {
+                    try writer.print(".{X:0>2}", .{opc[0]});
+                    opc = opc[1..];
+                },
+            }
+            try writer.print(".{X:0>2}", .{opc[0]});
+            opc = opc[1..];
+            switch (opc[0]) {
+                else => {},
+                0x38, 0x3A => {
+                    try writer.print("{X:0>2}", .{opc[0]});
+                    opc = opc[1..];
+                },
+            }
+            try writer.writeByte('.');
+            try writer.writeAll(switch (encoding.data.mode) {
+                .vex_128, .vex_256 => "W0",
+                .vex_128_long, .vex_256_long => "W1",
+                else => unreachable,
+            });
+            try writer.writeByte(' ');
+        },
     }
-    for (encoding.opcode()) |byte| {
+    for (opc) |byte| {
         try writer.print("{x:0>2} ", .{byte});
     }
 @@ -184,15 +221,16 @@ pub fn format(
             try writer.print("+{s} ", .{tag});
         },
         .m, .mi, .m1, .mc => try writer.print("/{d} ", .{encoding.modRmExt()}),
-        .mr, .rm, .rmi, .mri, .mrc => try writer.writeAll("/r "),
+        .mr, .rm, .rmi, .mri, .mrc, .rrm, .rrmi => try writer.writeAll("/r "),
     }
     switch (encoding.data.op_en) {
-        .i, .d, .zi, .oi, .mi, .rmi, .mri => {
+        .i, .d, .zi, .oi, .mi, .rmi, .mri, .rrmi => {
             const op = switch (encoding.data.op_en) {
                 .i, .d => encoding.data.ops[0],
                 .zi, .oi, .mi => encoding.data.ops[1],
                 .rmi, .mri => encoding.data.ops[2],
+                .rrmi => encoding.data.ops[3],
                 else => unreachable,
             };
             const tag = switch (op) {
 @@ -207,7 +245,7 @@ pub fn format(
             };
             try writer.print("{s} ", .{tag});
         },
-        .np, .fd, .td, .o, .m, .m1, .mc, .mr, .rm, .mrc => {},
+        .np, .fd, .td, .o, .m, .m1, .mc, .mr, .rm, .mrc, .rrm => {},
     }
     try writer.print("{s} ", .{@tagName(encoding.mnemonic)});
 @@ -305,6 +343,8 @@ pub const Mnemonic = enum {
     // SSE4.1
     roundss,
     roundsd,
+    // F16C
+    vcvtph2ps, vcvtps2ph,
     // zig fmt: on
 };
 @@ -317,6 +357,7 @@ pub const OpEn = enum {
     fd, td,
     m1, mc, mi, mr, rm,
     rmi, mri, mrc,
+    rrm, rrmi,
     // zig fmt: on
 };
 @@ -549,14 +590,21 @@ pub const Op = enum {
 pub const Mode = enum {
     none,
     short,
-    fpu,
     rex,
     long,
+    vex_128,
+    vex_128_long,
+    vex_256,
+    vex_256_long,
+};
+pub const Feature = enum {
+    none,
+    f16c,
     sse,
-    sse_long,
     sse2,
-    sse2_long,
     sse4_1,
+    x87,
 };
 fn estimateInstructionLength(prefix: Prefix, encoding: Encoding, ops: []const Operand) usize {
 @@ -593,6 +641,7 @@ const mnemonic_to_encodings_map = init: {
             .opc = undefined,
             .modrm_ext = entry[4],
             .mode = entry[5],
+            .feature = entry[6],
         };
         // TODO: use `@memcpy` for these. When I did that, I got a false positive
         // compile error for this copy happening at compile time.

src/arch/x86_64/Lower.zig+3

 @@ -133,6 +133,9 @@ pub fn lowerMir(lower: *Lower, inst: Mir.Inst) Error![]const Instruction {
         .subsd,
         .ucomisd,
         .xorpd,
+        .vcvtph2ps,
+        .vcvtps2ph,
         => try lower.mirGeneric(inst),
         .cmps,

src/arch/x86_64/Mir.zig+5

 @@ -247,6 +247,11 @@ pub const Inst = struct {
         /// Bitwise logical xor of packed double precision floating-point values
         xorpd,
+        /// Convert 16-bit floating-point values to single-precision floating-point values
+        vcvtph2ps,
+        /// Convert single-precision floating-point values to 16-bit floating-point values
+        vcvtps2ph,
         /// Compare string operands
         cmps,
         /// Load string

src/arch/x86_64/encoder.zig+144-16

...	@@ -209,10 +209,19 @@ pub const Instruction = struct {	...	@@ -209,10 +209,19 @@ pub const Instruction = struct {
209	const enc = inst.encoding;	209	const enc = inst.encoding;
210	const data = enc.data;	210	const data = enc.data;
211		211
212	try inst.encodeLegacyPrefixes(encoder);	212	switch (data.mode) {
213	try inst.encodeMandatoryPrefix(encoder);	213	.none, .short, .rex, .long => {
214	try inst.encodeRexPrefix(encoder);	214	try inst.encodeLegacyPrefixes(encoder);
215	try inst.encodeOpcode(encoder);	215	try inst.encodeMandatoryPrefix(encoder);
		216	try inst.encodeRexPrefix(encoder);
		217	try inst.encodeOpcode(encoder);
		218	},
		219	.vex_128, .vex_128_long, .vex_256, .vex_256_long => {
		220	try inst.encodeVexPrefix(encoder);
		221	const opc = inst.encoding.opcode();
		222	try encoder.opcode_1byte(opc[opc.len - 1]);
		223	},
		224	}
216		225
217	switch (data.op_en) {	226	switch (data.op_en) {
218	.np, .o => {},	227	.np, .o => {},
...	@@ -309,6 +318,7 @@ pub const Instruction = struct {	...	@@ -309,6 +318,7 @@ pub const Instruction = struct {
309	}	318	}
310	else	319	else
311	null,	320	null,
		321	.rrm, .rrmi => unreachable,
312	};	322	};
313	if (segment_override) \|seg\| {	323	if (segment_override) \|seg\| {
314	legacy.setSegmentOverride(seg);	324	legacy.setSegmentOverride(seg);
...	@@ -322,10 +332,7 @@ pub const Instruction = struct {	...	@@ -322,10 +332,7 @@ pub const Instruction = struct {
322		332
323	var rex = Rex{};	333	var rex = Rex{};
324	rex.present = inst.encoding.data.mode == .rex;	334	rex.present = inst.encoding.data.mode == .rex;
325	switch (inst.encoding.data.mode) {	335	rex.w = inst.encoding.data.mode == .long;
326	.long, .sse_long, .sse2_long => rex.w = true,
327	else => {},
328	}
329		336
330	switch (op_en) {	337	switch (op_en) {
331	.np, .i, .zi, .fd, .td, .d => {},	338	.np, .i, .zi, .fd, .td, .d => {},
...	@@ -346,11 +353,76 @@ pub const Instruction = struct {	...	@@ -346,11 +353,76 @@ pub const Instruction = struct {
346	rex.b = b_x_op.isBaseExtended();	353	rex.b = b_x_op.isBaseExtended();
347	rex.x = b_x_op.isIndexExtended();	354	rex.x = b_x_op.isIndexExtended();
348	},	355	},
		356	.rrm, .rrmi => unreachable,
349	}	357	}
350		358
351	try encoder.rex(rex);	359	try encoder.rex(rex);
352	}	360	}
353		361
		362	fn encodeVexPrefix(inst: Instruction, encoder: anytype) !void {
		363	const op_en = inst.encoding.data.op_en;
		364	const opc = inst.encoding.opcode();
		365	const mand_pre = inst.encoding.mandatoryPrefix();
		366
		367	var vex = Vex{};
		368
		369	vex.w = switch (inst.encoding.data.mode) {
		370	.vex_128, .vex_256 => false,
		371	.vex_128_long, .vex_256_long => true,
		372	else => unreachable,
		373	};
		374
		375	switch (op_en) {
		376	.np, .i, .zi, .fd, .td, .d => {},
		377	.o, .oi => vex.b = inst.ops[0].reg.isExtended(),
		378	.m, .mi, .m1, .mc, .mr, .rm, .rmi, .mri, .mrc, .rrm, .rrmi => {
		379	const r_op = switch (op_en) {
		380	.rm, .rmi, .rrm, .rrmi => inst.ops[0],
		381	.mr, .mri, .mrc => inst.ops[1],
		382	else => .none,
		383	};
		384	vex.r = r_op.isBaseExtended();
		385
		386	const b_x_op = switch (op_en) {
		387	.rm, .rmi => inst.ops[1],
		388	.m, .mi, .m1, .mc, .mr, .mri, .mrc => inst.ops[0],
		389	.rrm, .rrmi => inst.ops[2],
		390	else => unreachable,
		391	};
		392	vex.b = b_x_op.isBaseExtended();
		393	vex.x = b_x_op.isIndexExtended();
		394	},
		395	}
		396
		397	vex.l = switch (inst.encoding.data.mode) {
		398	.vex_128, .vex_128_long => false,
		399	.vex_256, .vex_256_long => true,
		400	else => unreachable,
		401	};
		402
		403	vex.p = if (mand_pre) \|mand\| switch (mand) {
		404	0x66 => .@"66",
		405	0xf2 => .f2,
		406	0xf3 => .f3,
		407	else => unreachable,
		408	} else .none;
		409
		410	const leading: usize = if (mand_pre) \|_\| 1 else 0;
		411	assert(opc[leading] == 0x0f);
		412	vex.m = switch (opc[leading + 1]) {
		413	else => .@"0f",
		414	0x38 => .@"0f38",
		415	0x3a => .@"0f3a",
		416	};
		417
		418	switch (op_en) {
		419	else => {},
		420	.rrm, .rrmi => vex.v = inst.ops[1].reg,
		421	}
		422
		423	try encoder.vex(vex);
		424	}
		425
354	fn encodeMandatoryPrefix(inst: Instruction, encoder: anytype) !void {	426	fn encodeMandatoryPrefix(inst: Instruction, encoder: anytype) !void {
355	const prefix = inst.encoding.mandatoryPrefix() orelse return;	427	const prefix = inst.encoding.mandatoryPrefix() orelse return;
356	try encoder.opcode_1byte(prefix);	428	try encoder.opcode_1byte(prefix);
...	@@ -562,17 +634,48 @@ fn Encoder(comptime T: type, comptime opts: Options) type {	...	@@ -562,17 +634,48 @@ fn Encoder(comptime T: type, comptime opts: Options) type {
562	/// or one of reg, index, r/m, base, or opcode-reg might be extended.	634	/// or one of reg, index, r/m, base, or opcode-reg might be extended.
563	///	635	///
564	/// See struct `Rex` for a description of each field.	636	/// See struct `Rex` for a description of each field.
565	pub fn rex(self: Self, byte: Rex) !void {	637	pub fn rex(self: Self, fields: Rex) !void {
566	if (!byte.present and !byte.isSet()) return;	638	if (!fields.present and !fields.isSet()) return;
		639
		640	var byte: u8 = 0b0100_0000;
567		641
568	var value: u8 = 0b0100_0000;	642	if (fields.w) byte \|= 0b1000;
		643	if (fields.r) byte \|= 0b0100;
		644	if (fields.x) byte \|= 0b0010;
		645	if (fields.b) byte \|= 0b0001;
569		646
570	if (byte.w) value \|= 0b1000;	647	try self.writer.writeByte(byte);
571	if (byte.r) value \|= 0b0100;	648	}
572	if (byte.x) value \|= 0b0010;
573	if (byte.b) value \|= 0b0001;
574		649
575	try self.writer.writeByte(value);	650	/// Encodes a VEX prefix given all the fields
		651	///
		652	/// See struct `Vex` for a description of each field.
		653	pub fn vex(self: Self, fields: Vex) !void {
		654	if (fields.is3Byte()) {
		655	try self.writer.writeByte(0b1100_0100);
		656
		657	try self.writer.writeByte(
		658	@as(u8, ~@boolToInt(fields.r)) << 7 \|
		659	@as(u8, ~@boolToInt(fields.x)) << 6 \|
		660	@as(u8, ~@boolToInt(fields.b)) << 5 \|
		661	@as(u8, @enumToInt(fields.m)) << 0,
		662	);
		663
		664	try self.writer.writeByte(
		665	@as(u8, @boolToInt(fields.w)) << 7 \|
		666	@as(u8, ~fields.v.enc()) << 3 \|
		667	@as(u8, @boolToInt(fields.l)) << 2 \|
		668	@as(u8, @enumToInt(fields.p)) << 0,
		669	);
		670	} else {
		671	try self.writer.writeByte(0b1100_0101);
		672	try self.writer.writeByte(
		673	@as(u8, ~@boolToInt(fields.r)) << 7 \|
		674	@as(u8, ~fields.v.enc()) << 3 \|
		675	@as(u8, @boolToInt(fields.l)) << 2 \|
		676	@as(u8, @enumToInt(fields.p)) << 0,
		677	);
		678	}
576	}	679	}
577		680
578	// ------	681	// ------
...	@@ -848,6 +951,31 @@ pub const Rex = struct {	...	@@ -848,6 +951,31 @@ pub const Rex = struct {
848	}	951	}
849	};	952	};
850		953
		954	pub const Vex = struct {
		955	w: bool = false,
		956	r: bool = false,
		957	x: bool = false,
		958	b: bool = false,
		959	l: bool = false,
		960	p: enum(u2) {
		961	none = 0b00,
		962	@"66" = 0b01,
		963	f3 = 0b10,
		964	f2 = 0b11,
		965	} = .none,
		966	m: enum(u5) {
		967	@"0f" = 0b0_0001,
		968	@"0f38" = 0b0_0010,
		969	@"0f3a" = 0b0_0011,
		970	_,
		971	} = .@"0f",
		972	v: Register = .ymm0,
		973
		974	pub fn is3Byte(vex: Vex) bool {
		975	return vex.w or vex.x or vex.b or vex.m != .@"0f";
		976	}
		977	};
		978
851	// Tests	979	// Tests
852	fn expectEqualHexStrings(expected: []const u8, given: []const u8, assembly: []const u8) !void {	980	fn expectEqualHexStrings(expected: []const u8, given: []const u8, assembly: []const u8) !void {
853	assert(expected.len > 0);	981	assert(expected.len > 0);

src/arch/x86_64/encodings.zig+876-870

test/behavior/vector.zig+2-1

...	@@ -168,7 +168,8 @@ test "array to vector" {	...	@@ -168,7 +168,8 @@ test "array to vector" {
168		168
169	test "array to vector with element type coercion" {	169	test "array to vector with element type coercion" {
170	if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO	170	if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
171	if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO	171	if (builtin.zig_backend == .stage2_x86_64 and
		172	!comptime std.Target.x86.featureSetHas(builtin.cpu.features, .f16c)) return error.SkipZigTest; // TODO
172	if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO	173	if (builtin.zig_backend == .stage2_aarch64) return error.SkipZigTest; // TODO
173	if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO	174	if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
174	if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO	175	if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO

...	@@ -3,933 +3,939 @@ const Mnemonic = Encoding.Mnemonic;	...	@@ -3,933 +3,939 @@ const Mnemonic = Encoding.Mnemonic;
3	const OpEn = Encoding.OpEn;	3	const OpEn = Encoding.OpEn;
4	const Op = Encoding.Op;	4	const Op = Encoding.Op;
5	const Mode = Encoding.Mode;	5	const Mode = Encoding.Mode;
		6	const Feature = Encoding.Feature;
6		7
7	const modrm_ext = u3;	8	const modrm_ext = u3;
8		9
9	pub const Entry = struct { Mnemonic, OpEn, []const Op, []const u8, modrm_ext, Mode };	10	pub const Entry = struct { Mnemonic, OpEn, []const Op, []const u8, modrm_ext, Mode, Feature };
10		11
11	// TODO move this into a .zon file when Zig is capable of importing .zon files	12	// TODO move this into a .zon file when Zig is capable of importing .zon files
12	// zig fmt: off	13	// zig fmt: off
13	pub const table = [_]Entry{	14	pub const table = [_]Entry{
14	// General-purpose	15	// General-purpose
15	.{ .adc, .zi, &.{ .al, .imm8 }, &.{ 0x14 }, 0, .none },	16	.{ .adc, .zi, &.{ .al, .imm8 }, &.{ 0x14 }, 0, .none, .none },
16	.{ .adc, .zi, &.{ .ax, .imm16 }, &.{ 0x15 }, 0, .none },	17	.{ .adc, .zi, &.{ .ax, .imm16 }, &.{ 0x15 }, 0, .none, .none },
17	.{ .adc, .zi, &.{ .eax, .imm32 }, &.{ 0x15 }, 0, .none },	18	.{ .adc, .zi, &.{ .eax, .imm32 }, &.{ 0x15 }, 0, .none, .none },
18	.{ .adc, .zi, &.{ .rax, .imm32s }, &.{ 0x15 }, 0, .long },	19	.{ .adc, .zi, &.{ .rax, .imm32s }, &.{ 0x15 }, 0, .long, .none },
19	.{ .adc, .mi, &.{ .rm8, .imm8 }, &.{ 0x80 }, 2, .none },	20	.{ .adc, .mi, &.{ .rm8, .imm8 }, &.{ 0x80 }, 2, .none, .none },
20	.{ .adc, .mi, &.{ .rm8, .imm8 }, &.{ 0x80 }, 2, .rex },	21	.{ .adc, .mi, &.{ .rm8, .imm8 }, &.{ 0x80 }, 2, .rex, .none },
21	.{ .adc, .mi, &.{ .rm16, .imm16 }, &.{ 0x81 }, 2, .none },	22	.{ .adc, .mi, &.{ .rm16, .imm16 }, &.{ 0x81 }, 2, .none, .none },
22	.{ .adc, .mi, &.{ .rm32, .imm32 }, &.{ 0x81 }, 2, .none },	23	.{ .adc, .mi, &.{ .rm32, .imm32 }, &.{ 0x81 }, 2, .none, .none },
23	.{ .adc, .mi, &.{ .rm64, .imm32s }, &.{ 0x81 }, 2, .long },	24	.{ .adc, .mi, &.{ .rm64, .imm32s }, &.{ 0x81 }, 2, .long, .none },
24	.{ .adc, .mi, &.{ .rm16, .imm8s }, &.{ 0x83 }, 2, .none },	25	.{ .adc, .mi, &.{ .rm16, .imm8s }, &.{ 0x83 }, 2, .none, .none },
25	.{ .adc, .mi, &.{ .rm32, .imm8s }, &.{ 0x83 }, 2, .none },	26	.{ .adc, .mi, &.{ .rm32, .imm8s }, &.{ 0x83 }, 2, .none, .none },
26	.{ .adc, .mi, &.{ .rm64, .imm8s }, &.{ 0x83 }, 2, .long },	27	.{ .adc, .mi, &.{ .rm64, .imm8s }, &.{ 0x83 }, 2, .long, .none },
27	.{ .adc, .mr, &.{ .rm8, .r8 }, &.{ 0x10 }, 0, .none },	28	.{ .adc, .mr, &.{ .rm8, .r8 }, &.{ 0x10 }, 0, .none, .none },
28	.{ .adc, .mr, &.{ .rm8, .r8 }, &.{ 0x10 }, 0, .rex },	29	.{ .adc, .mr, &.{ .rm8, .r8 }, &.{ 0x10 }, 0, .rex, .none },
29	.{ .adc, .mr, &.{ .rm16, .r16 }, &.{ 0x11 }, 0, .none },	30	.{ .adc, .mr, &.{ .rm16, .r16 }, &.{ 0x11 }, 0, .none, .none },
30	.{ .adc, .mr, &.{ .rm32, .r32 }, &.{ 0x11 }, 0, .none },	31	.{ .adc, .mr, &.{ .rm32, .r32 }, &.{ 0x11 }, 0, .none, .none },
31	.{ .adc, .mr, &.{ .rm64, .r64 }, &.{ 0x11 }, 0, .long },	32	.{ .adc, .mr, &.{ .rm64, .r64 }, &.{ 0x11 }, 0, .long, .none },
32	.{ .adc, .rm, &.{ .r8, .rm8 }, &.{ 0x12 }, 0, .none },	33	.{ .adc, .rm, &.{ .r8, .rm8 }, &.{ 0x12 }, 0, .none, .none },
33	.{ .adc, .rm, &.{ .r8, .rm8 }, &.{ 0x12 }, 0, .rex },	34	.{ .adc, .rm, &.{ .r8, .rm8 }, &.{ 0x12 }, 0, .rex, .none },
34	.{ .adc, .rm, &.{ .r16, .rm16 }, &.{ 0x13 }, 0, .none },	35	.{ .adc, .rm, &.{ .r16, .rm16 }, &.{ 0x13 }, 0, .none, .none },
35	.{ .adc, .rm, &.{ .r32, .rm32 }, &.{ 0x13 }, 0, .none },	36	.{ .adc, .rm, &.{ .r32, .rm32 }, &.{ 0x13 }, 0, .none, .none },
36	.{ .adc, .rm, &.{ .r64, .rm64 }, &.{ 0x13 }, 0, .long },	37	.{ .adc, .rm, &.{ .r64, .rm64 }, &.{ 0x13 }, 0, .long, .none },
37		38
38	.{ .add, .zi, &.{ .al, .imm8 }, &.{ 0x04 }, 0, .none },	39	.{ .add, .zi, &.{ .al, .imm8 }, &.{ 0x04 }, 0, .none, .none },
39	.{ .add, .zi, &.{ .ax, .imm16 }, &.{ 0x05 }, 0, .none },	40	.{ .add, .zi, &.{ .ax, .imm16 }, &.{ 0x05 }, 0, .none, .none },
40	.{ .add, .zi, &.{ .eax, .imm32 }, &.{ 0x05 }, 0, .none },	41	.{ .add, .zi, &.{ .eax, .imm32 }, &.{ 0x05 }, 0, .none, .none },