diff --git a/lib/compiler_rt/hexagon.zig b/lib/compiler_rt/hexagon.zig
index 2a4b8b75f7d0e961a853225bab3bbd135bf4665a..43b4584400f25982932034298e8d6b13a7c6e972 100644
--- a/lib/compiler_rt/hexagon.zig
+++ b/lib/compiler_rt/hexagon.zig
@@ -1759,6 +1759,584 @@ fn __hexagon_sqrtdf2() align(32) callconv(.naked) noreturn {
     );
 }
 
+fn __qf_convert_hf_to_b_rne() align(32) callconv(.naked) noreturn {
+    asm volatile (
+        \\ //V0 and V1 have input
+        \\ //First rnd, replaces  V0.h=V0.hf
+        \\ //Convert input vector to half word
+        \\ {
+        \\   R1=#0x3800 //+.5
+        \\   R2=#0xB800 //-.5
+        \\   V7.h=V0.hf //Convert and truncate half precision
+        \\  }
+        \\ {
+        \\   V6=#0
+        \\   R3=#0x00010001
+        \\   R4=#0x37FF
+        \\  }
+        \\ {
+        \\   V10=vsplat(R3)
+        \\   V12.h=vsplat(R4)
+        \\   V15.hf=V7.h //Convert truncated back to hf
+        \\  }
+        \\ {
+        \\   V23.h=vsplat(R1) //V3 = +.5
+        \\   V24.h=vsplat(R2) //V4 = -.5
+        \\   V5.qf16=vsub(V0.hf,V15.hf) //Sub truncated value from original value
+        \\   R0=#0x7FFF //Mask off sign bit of IEEE-754
+        \\  }
+        \\ {
+        \\   Q0=vcmp.gt(V0.hf,V6.hf) // hf value is pos (hf > 0)
+        \\   V5.hf=V5.qf16 //V5 is the fractional of original value
+        \\   V22.h=vsplat(R0) //Splat R0 to Mask off sign bit
+        \\  }
+        \\ {
+        \\   V15=vmux(Q0,V23,V24) //If input is pos value, use +.5. If neg value, use -.5 (Q in prev packet)
+        \\   V2=vand(V22,V5) //V2=abs(frac)
+        \\   V13=vand(V0,V22) //V13 = abs(input)
+        \\  }
+        \\ {
+        \\   Q1=vcmp.eq(V2.h,V23.h) // frac == .5 (0x3800)
+        \\   V15=vsplat(R3) //V1=1
+        \\   V4.qf16=vadd(V0.hf,V15.hf) // Add +.5 or -.5 to V0
+        \\   Q3=vcmp.eq(V13.h,V12.h) //Q3 = if(input == abs(.4998))
+        \\  }
+        \\ {
+        \\   V11=vand(V7,V10) //Mask off all the lower bits
+        \\   V3.h = vadd(V15.h,V15.h) //V3 is 2
+        \\  }
+        \\ {
+        \\   Q2=vcmp.eq(V11.h,V10.h) //Is input value odd if halfword equals 0x1
+        \\   V4.hf=V4.qf16 //hf value after add/sub .5
+        \\  }
+        \\ {
+        \\   Q1=and(Q1,!Q2) //Is frac .5 and input is even
+        \\   if (Q0) V15.h-=V3.h //If input is pos, sub 2 so V1 is -1
+        \\   V4=vmux(Q3,V6,V4)
+        \\  }
+        \\ {
+        \\   V4.h=V4.hf //Truncate, V4 has converted value
+        \\   V15=vmux(Q1,V15,V6) //If frac == .5 and input is even, use +1/-1. Else 0
+        \\  }
+        \\ {
+        \\   //Second rnd, replaces  V1.h=V1.hf //Convert input vector to half word
+        \\   V7.h=V1.hf //Convert and truncate half precision
+        \\  }
+        \\ {
+        \\   V16.h = vadd(V4.h,V15.h) //Add +1/-1 or 0. V4 has the result
+        \\   V1.hf=V7.h //Convert truncated back to hf
+        \\  }
+        \\ {
+        \\   V5.qf16=vsub(V0.hf,V1.hf) //Sub truncated value from original value
+        \\   R0=#0x7FFF //Mask off sign bit of IEEE-754
+        \\  }
+        \\ {
+        \\   Q0=vcmp.gt(V0.hf,V6.hf) // hf value is pos (hf > 0)
+        \\   V5.hf=V5.qf16 //V5 is the fractional of original value
+        \\  }
+        \\ {
+        \\   V1=vmux(Q0,V23,V24) //If input is pos value, use +.5. If neg value, use -.5 (Q in prev packet)
+        \\   V2=vand(V22,V5) //V2=abs(frac)
+        \\   V13=vand(V0,V22) //V13 = abs(input)
+        \\  }
+        \\ {
+        \\   Q1=vcmp.eq(V2.h,V23.h) // frac == .5 (0x3800)
+        \\   V1=vsplat(R3) //V1=1
+        \\   V4.qf16=vadd(V0.hf,V1.hf) // Add +.5 or -.5 to V0
+        \\   Q3=vcmp.eq(V13.h,V12.h) //Q3 = if(input == abs(.4998))
+        \\  }
+        \\ {
+        \\   V11=vand(V7,V10) //Mask off all the lower bits
+        \\   V3.h = vadd(V1.h,V1.h) //V3 is 2
+        \\  }
+        \\ {
+        \\   Q2=vcmp.eq(V11.h,V10.h) //Is input value odd if halfword equals 0x1
+        \\   V4.hf=V4.qf16 //hf value after add/sub .5
+        \\  }
+        \\ {
+        \\   Q1=and(Q1,!Q2) //Is frac .5 and input is even
+        \\   if (Q0) V1.h-=V3.h //If input is pos, sub 2 so V1 is -1
+        \\   V4=vmux(Q3,V6,V4)
+        \\  }
+        \\ {
+        \\   V4.h=V4.hf //Truncate, V4 has converted value
+        \\   V1=vmux(Q1,V1,V6) //If frac == .5 and input is even, use +1/-1. Else 0
+        \\  }
+        \\ {
+        \\   V17.h = vadd(V4.h,V1.h) //Add +1/-1 or 0. V4 has the result
+        \\  }
+        \\ {
+        \\   V0.b = vpack(V17.h,V16.h):sat
+        \\  }
+        \\ {
+        \\   V0.h=vshuff(V0.h)
+        \\   jumpr R31
+        \\  }
+    );
+}
+
+fn __qf_convert_hf_to_h_rne() align(32) callconv(.naked) noreturn {
+    asm volatile (
+        \\ {
+        \\   R1=#0x3800 //+.5
+        \\   R2=#0xB800 //-.5
+        \\   V7.h=V0.hf //Convert and truncate half precision
+        \\  }
+        \\ {
+        \\   V6=#0
+        \\   R3=#0x00010001
+        \\   R4=#0x37FF
+        \\  }
+        \\ {
+        \\   V10=vsplat(R3)
+        \\   V12.h=vsplat(R4)
+        \\   V1.hf=V7.h //Convert truncated back to hf
+        \\  }
+        \\ {
+        \\   V3.h=vsplat(R1) //V3 = +.5
+        \\   V4.h=vsplat(R2) //V4 = -.5
+        \\   V5.qf16=vsub(V0.hf,V1.hf) //Sub truncated value from original value
+        \\   R0=#0x7FFF //Mask off sign bit of IEEE-754
+        \\  }
+        \\ {
+        \\   Q0=vcmp.gt(V0.hf,V6.hf) // hf value is pos (hf > 0)
+        \\   V5.hf=V5.qf16 //V5 is the fractional of original value
+        \\   V2.h=vsplat(R0) //Splat R0 to Mask off sign bit
+        \\  }
+        \\ {
+        \\   V1=vmux(Q0,V3,V4) //If input is pos value, use +.5. If neg value, use -.5 (Q in prev packet)
+        \\   V2=vand(V2,V5) //V2=abs(frac)
+        \\   V13=vand(V0,V2) //V13 = abs(input)
+        \\  }
+        \\ {
+        \\   Q1=vcmp.eq(V2.h,V3.h) // frac == .5 (0x3800)
+        \\   V1=vsplat(R3) //V1=1
+        \\   V4.qf16=vadd(V0.hf,V1.hf) // Add +.5 or -.5 to V0
+        \\   Q3=vcmp.eq(V13.h,V12.h) //Q3 = if(input == abs(.4998))
+        \\  }
+        \\ {
+        \\   V11=vand(V7,V10) //Mask off all the lower bits
+        \\   V3.h = vadd(V1.h,V1.h) //V3 is 2
+        \\  }
+        \\ {
+        \\   Q2=vcmp.eq(V11.h,V10.h) //Is input value odd if halfword equals 0x1
+        \\   V4.hf=V4.qf16 //hf value after add/sub .5
+        \\  }
+        \\ {
+        \\   Q1=and(Q1,!Q2) //Is frac .5 and input is even
+        \\   if (Q0) V1.h-=V3.h //If input is pos, sub 2 so V1 is -1
+        \\   V4=vmux(Q3,V6,V4)
+        \\  }
+        \\ {
+        \\   V4.h=V4.hf //Truncate, V4 has converted value
+        \\   V1=vmux(Q1,V1,V6) //If frac == .5 and input is even, use +1/-1. Else 0
+        \\  }
+        \\ {
+        \\   V0.h = vadd(V4.h,V1.h) //Add +1/-1 or 0. V4 has the result
+        \\   jumpr LR
+        \\  }
+    );
+}
+
+fn __qf_convert_hf_to_ub_rne() align(32) callconv(.naked) noreturn {
+    asm volatile (
+        \\ //V0 and V1 have input
+        \\ //First rnd, replaces  V0.h=V0.hf
+        \\ //Convert input vector to half word
+        \\ {
+        \\   R1=#0x3800 //+.5
+        \\   R2=#0xB800 //-.5
+        \\   V7.h=V0.hf //Convert and truncate half precision
+        \\  }
+        \\ {
+        \\   V6=#0
+        \\   R3=#0x00010001
+        \\   R4=#0x37FF
+        \\  }
+        \\ {
+        \\   V10=vsplat(R3)
+        \\   V12.h=vsplat(R4)
+        \\   V15.hf=V7.h //Convert truncated back to hf
+        \\  }
+        \\ {
+        \\   V23.h=vsplat(R1) //V3 = +.5
+        \\   V24.h=vsplat(R2) //V4 = -.5
+        \\   V5.qf16=vsub(V0.hf,V15.hf) //Sub truncated value from original value
+        \\   R0=#0x7FFF //Mask off sign bit of IEEE-754
+        \\  }
+        \\ {
+        \\   Q0=vcmp.gt(V0.hf,V6.hf) // hf value is pos (hf > 0)
+        \\   V5.hf=V5.qf16 //V5 is the fractional of original value
+        \\   V22.h=vsplat(R0) //Splat R0 to Mask off sign bit
+        \\  }
+        \\ {
+        \\   V15=vmux(Q0,V23,V24) //If input is pos value, use +.5. If neg value, use -.5 (Q in prev packet)
+        \\   V2=vand(V22,V5) //V2=abs(frac)
+        \\   V13=vand(V0,V22) //V13 = abs(input)
+        \\  }
+        \\ {
+        \\   Q1=vcmp.eq(V2.h,V23.h) // frac == .5 (0x3800)
+        \\   V15=vsplat(R3) //V1=1
+        \\   V4.qf16=vadd(V0.hf,V15.hf) // Add +.5 or -.5 to V0
+        \\   Q3=vcmp.eq(V13.h,V12.h) //Q3 = if(input == abs(.4998))
+        \\  }
+        \\ {
+        \\   V11=vand(V7,V10) //Mask off all the lower bits
+        \\   V3.h = vadd(V15.h,V15.h) //V3 is 2
+        \\  }
+        \\ {
+        \\   Q2=vcmp.eq(V11.h,V10.h) //Is input value odd if halfword equals 0x1
+        \\   V4.hf=V4.qf16 //hf value after add/sub .5
+        \\  }
+        \\ {
+        \\   Q1=and(Q1,!Q2) //Is frac .5 and input is even
+        \\   if (Q0) V15.h-=V3.h //If input is pos, sub 2 so V1 is -1
+        \\   V4=vmux(Q3,V6,V4)
+        \\  }
+        \\ {
+        \\   V4.h=V4.hf //Truncate, V4 has converted value
+        \\   V15=vmux(Q1,V15,V6) //If frac == .5 and input is even, use +1/-1. Else 0
+        \\  }
+        \\ {
+        \\   //Second rnd, replaces  V1.h=V1.hf //Convert input vector to half word
+        \\   V7.h=V1.hf //Convert and truncate half precision
+        \\  }
+        \\ {
+        \\   V16.h = vadd(V4.h,V15.h) //Add +1/-1 or 0. V4 has the result
+        \\   V1.hf=V7.h //Convert truncated back to hf
+        \\  }
+        \\ {
+        \\   V5.qf16=vsub(V0.hf,V1.hf) //Sub truncated value from original value
+        \\   R0=#0x7FFF //Mask off sign bit of IEEE-754
+        \\  }
+        \\ {
+        \\   Q0=vcmp.gt(V0.hf,V6.hf) // hf value is pos (hf > 0)
+        \\   V5.hf=V5.qf16 //V5 is the fractional of original value
+        \\  }
+        \\ {
+        \\   V1=vmux(Q0,V23,V24) //If input is pos value, use +.5. If neg value, use -.5 (Q in prev packet)
+        \\   V2=vand(V22,V5) //V2=abs(frac)
+        \\   V13=vand(V0,V22) //V13 = abs(input)
+        \\  }
+        \\ {
+        \\   Q1=vcmp.eq(V2.h,V23.h) // frac == .5 (0x3800)
+        \\   V1=vsplat(R3) //V1=1
+        \\   V4.qf16=vadd(V0.hf,V1.hf) // Add +.5 or -.5 to V0
+        \\   Q3=vcmp.eq(V13.h,V12.h) //Q3 = if(input == abs(.4998))
+        \\  }
+        \\ {
+        \\   V11=vand(V7,V10) //Mask off all the lower bits
+        \\   V3.h = vadd(V1.h,V1.h) //V3 is 2
+        \\  }
+        \\ {
+        \\   Q2=vcmp.eq(V11.h,V10.h) //Is input value odd if halfword equals 0x1
+        \\   V4.hf=V4.qf16 //hf value after add/sub .5
+        \\  }
+        \\ {
+        \\   Q1=and(Q1,!Q2) //Is frac .5 and input is even
+        \\   if (Q0) V1.h-=V3.h //If input is pos, sub 2 so V1 is -1
+        \\   V4=vmux(Q3,V6,V4)
+        \\  }
+        \\ {
+        \\   V4.h=V4.hf //Truncate, V4 has converted value
+        \\   V1=vmux(Q1,V1,V6) //If frac == .5 and input is even, use +1/-1. Else 0
+        \\  }
+        \\ {
+        \\   V17.h = vadd(V4.h,V1.h) //Add +1/-1 or 0. V4 has the result
+        \\  }
+        \\ {
+        \\   V0.ub = vpack(V17.h,V16.h):sat
+        \\  }
+        \\ {
+        \\   V0.h=vshuff(V0.h)
+        \\   jumpr LR
+        \\  }
+    );
+}
+
+fn __qf_convert_hf_to_uh_rne() align(32) callconv(.naked) noreturn {
+    asm volatile (
+        \\ {
+        \\   R20=#0x38003800 //.5
+        \\   R21=#0x77FF //Number right before 2^15
+        \\   R22=#1
+        \\   R23=#0x7BFF //num right under Inf
+        \\  }
+        \\ {
+        \\   V21=#0
+        \\   V23.qf16=vmpy(V0.hf,R20.hf) //Multiply .5
+        \\  }
+        \\ //First rnd, replaces  V22.h=V0.hf
+        \\ //Convert input vector to half word
+        \\ {
+        \\   R1=#0x3800 //+.5
+        \\   R2=#0xB800 //-.5
+        \\   V7.h=V0.hf //Convert and truncate half precision
+        \\  }
+        \\ {
+        \\   V6=#0
+        \\   R3=#0x00010001
+        \\   R4=#0x37FF
+        \\  }
+        \\ {
+        \\   V10=vsplat(R3)
+        \\   V12.h=vsplat(R4)
+        \\   V1.hf=V7.h //Convert truncated back to hf
+        \\  }
+        \\ {
+        \\   V26.h=vsplat(R1) //V3 = +.5
+        \\   V27.h=vsplat(R2) //V4 = -.5
+        \\   V5.qf16=vsub(V0.hf,V1.hf) //Sub truncated value from original value
+        \\   R0=#0x7FFF //Mask off sign bit of IEEE-754
+        \\  }
+        \\ {
+        \\   Q0=vcmp.gt(V0.hf,V6.hf) // hf value is pos (hf > 0)
+        \\   V5.hf=V5.qf16 //V5 is the fractional of original value
+        \\   V25.h=vsplat(R0) //Splat R0 to Mask off sign bit
+        \\  }
+        \\ {
+        \\   V1=vmux(Q0,V26,V27) //If input is pos value, use +.5. If neg value, use -.5 (Q in prev packet)
+        \\   V2=vand(V25,V5) //V2=abs(frac)
+        \\   V13=vand(V0,V25) //V13 = abs(input)
+        \\  }
+        \\ {
+        \\   Q1=vcmp.eq(V2.h,V26.h) // frac == .5 (0x3800)
+        \\   V1=vsplat(R3) //V1=1
+        \\   V4.qf16=vadd(V0.hf,V1.hf) // Add +.5 or -.5 to V0
+        \\   Q3=vcmp.eq(V13.h,V12.h) //Q3 = if(input == abs(.4998))
+        \\  }
+        \\ {
+        \\   V11=vand(V7,V10) //Mask off all the lower bits
+        \\   V3.h = vadd(V1.h,V1.h) //V3 is 2
+        \\  }
+        \\ {
+        \\   Q2=vcmp.eq(V11.h,V10.h) //Is input value odd if halfword equals 0x1
+        \\   V4.hf=V4.qf16 //hf value after add/sub .5
+        \\  }
+        \\ {
+        \\   Q1=and(Q1,!Q2) //Is frac .5 and input is even
+        \\   if (Q0) V1.h-=V3.h //If input is pos, sub 2 so V1 is -1
+        \\   V4=vmux(Q3,V6,V4)
+        \\  }
+        \\ {
+        \\   V4.h=V4.hf //Truncate, V4 has converted value
+        \\   V1=vmux(Q1,V1,V6) //If frac == .5 and input is even, use +1/-1. Else 0
+        \\  }
+        \\ {
+        \\   V22.h = vadd(V4.h,V1.h) //Add +1/-1 or 0. V4 has the result
+        \\  }
+        \\ {
+        \\   V23.hf=V23.qf16 //Convert multiply back to hf
+        \\   V21.h=vmax(V21.h,V22.h) //Filter out anything lower than 0
+        \\  }
+        \\ {
+        \\   V22.h=vsplat(R21)  //Splat overflow value for compare
+        \\ //Second rnd, replaces  V23.h=V23.hf
+        \\ //Convert input vector to half word
+        \\   V7.h=V23.hf //Convert and truncate half precision
+        \\  }
+        \\ {
+        \\   V1.hf=V7.h //Convert truncated back to hf
+        \\  }
+        \\ {
+        \\   V5.qf16=vsub(V23.hf,V1.hf) //Sub truncated value from original value
+        \\  }
+        \\ {
+        \\   Q0=vcmp.gt(V23.hf,V6.hf) // hf value is pos (hf > 0)
+        \\   V5.hf=V5.qf16 //V5 is the fractional of original value
+        \\  }
+        \\ {
+        \\   V1=vmux(Q0,V26,V27) //If input is pos value, use +.5. If neg value, use -.5 (Q in prev packet)
+        \\   V2=vand(V25,V5) //V2=abs(frac)
+        \\   V13=vand(V23,V25) //V13 = abs(input)
+        \\  }
+        \\ {
+        \\   Q1=vcmp.eq(V2.h,V26.h) // frac == .5 (0x3800)
+        \\   V1=vsplat(R3) //V1=1
+        \\   V4.qf16=vadd(V23.hf,V1.hf) // Add +.5 or -.5 to V0
+        \\   Q3=vcmp.eq(V13.h,V12.h) //Q3 = if(input == abs(.4998))
+        \\  }
+        \\ {
+        \\   V11=vand(V7,V10) //Mask off all the lower bits
+        \\   V3.h = vadd(V1.h,V1.h) //V3 is 2
+        \\  }
+        \\ {
+        \\   Q2=vcmp.eq(V11.h,V10.h) //Is input value odd if halfword equals 0x1
+        \\   V4.hf=V4.qf16 //hf value after add/sub .5
+        \\  }
+        \\ {
+        \\   Q1=and(Q1,!Q2) //Is frac .5 and input is even
+        \\   if (Q0) V1.h-=V3.h //If input is pos, sub 2 so V1 is -1
+        \\   V4=vmux(Q3,V6,V4)
+        \\  }
+        \\ {
+        \\   V4.h=V4.hf //Truncate, V4 has converted value
+        \\   V1=vmux(Q1,V1,V6) //If frac == .5 and input is even, use +1/-1. Else 0
+        \\  }
+        \\ {
+        \\   V23.h = vadd(V4.h,V1.h) //Add +1/-1 or 0. V4 has the result
+        \\  }
+        \\ {
+        \\   Q1=vcmp.gt(V22.hf,V0.hf) //Q1 is if value doesn't overflow on hf=h convert (V0 is input, V2 is right before 2^15)
+        \\   V23.h=vasl(V23.h,R22)  //Left shift converted value
+        \\   V24.h=vsplat(R23)  //Splat inf
+        \\  }
+        \\ {
+        \\   Q1|=vcmp.gt(V0.uh,V24.uh) //Q1 is value is < inf/nan
+        \\  }
+        \\ {
+        \\   V0=vmux(Q1,V21,V23) //If value is not overflow or input is Inf, set to converted input. Else, set to overflow
+        \\   jumpr LR
+        \\  }
+    );
+}
+
+fn __qf_fast_convert_hf_to_b_rne() align(32) callconv(.naked) noreturn {
+    asm volatile (
+        \\ //V0.hf and V1.hf has value to be converted
+        \\ {
+        \\   R1=#0x3800 //+.5
+        \\   R2=#0xB800 //-.5
+        \\   V2=#0
+        \\  }
+        \\ {
+        \\   Q0=vcmp.gt(V0.hf,V2.hf) // hf value is pos (hf > 0)
+        \\   Q1=vcmp.gt(V1.hf,V2.hf) // hf value is pos (hf > 0)
+        \\   V2.h=vsplat(R1) //V1 = +.5
+        \\   V3.h=vsplat(R2) //V2 = -.5
+        \\  }
+        \\ {
+        \\   V2=vmux(Q0,V2,V3) //If pos value, use +.5. If neg value, use -.5
+        \\   V3=vmux(Q1,V2,V3) //If pos value, use +.5. If neg value, use -.5
+        \\  }
+        \\ {
+        \\   V4.qf16=vadd(V0.hf,V2.hf) // Add +.5 or -.5 to V0
+        \\  }
+        \\ {
+        \\   V5.qf16=vadd(V1.hf,V3.hf) // Add +.5 or -.5 to V1
+        \\  }
+        \\ {
+        \\   V4.hf=V4.qf16
+        \\  }
+        \\ {
+        \\   V5.hf=V5.qf16
+        \\  }
+        \\ {
+        \\   V4.h=V4.hf //Truncate, V4 has converted value
+        \\  }
+        \\ {
+        \\   V5.h=V5.hf //Truncate, V5 has converted value
+        \\  }
+        \\ {
+        \\   V0.ub = vpack(V4.h,V5.h):sat
+        \\  }
+        \\ {
+        \\   V0.h = vshuff(V0.h)
+        \\   jumpr LR
+        \\  }
+    );
+}
+
+fn __qf_fast_convert_hf_to_h_rne() align(32) callconv(.naked) noreturn {
+    asm volatile (
+        \\ //V0.hf has value to be converted
+        \\ {
+        \\   R1=#0x3800 //+.5
+        \\   R2=#0xB800 //-.5
+        \\   V1=#0
+        \\  }
+        \\ {
+        \\   Q0=vcmp.gt(V0.hf,V1.hf) // hf value is pos (hf > 0)
+        \\   V1.h=vsplat(R1) //V1 = +.5
+        \\   V2.h=vsplat(R2) //V2 = -.5
+        \\  }
+        \\ {
+        \\   V1=vmux(Q0,V1,V2) //If pos value, use +.5. If neg value, use -.5
+        \\  }
+        \\ {
+        \\   V4.qf16=vadd(V0.hf,V1.hf) // Add +.5 or -.5 to V0
+        \\  }
+        \\ {
+        \\   V4.hf=V4.qf16
+        \\  }
+        \\ {
+        \\   V0.h=V4.hf //Truncate, V4 has converted value
+        \\   jumpr LR
+        \\  }
+    );
+}
+
+fn __qf_fast_convert_hf_to_ub_rne() align(32) callconv(.naked) noreturn {
+    asm volatile (
+        \\ //V0.hf and V1.hf have value to be converted
+        \\ {
+        \\   R1=#0x3800 //+.5
+        \\   V3=#0
+        \\  }
+        \\ {
+        \\   Q0=vcmp.gt(V0.hf,V3.hf) // hf value is pos (hf > 0)
+        \\   Q1=vcmp.gt(V1.hf,V3.hf) // hf value is pos (hf > 0)
+        \\   V2.h=vsplat(R1) //V1 = +.5
+        \\  }
+        \\ {
+        \\   V4.qf16=vadd(V0.hf,V2.hf) // Add +.5
+        \\  }
+        \\ {
+        \\   V5.qf16=vadd(V1.hf,V2.hf) // Add +.5
+        \\  }
+        \\ {
+        \\   V4.hf=V4.qf16
+        \\  }
+        \\ {
+        \\   V5.hf=V5.qf16
+        \\  }
+        \\ {
+        \\   V4.h=V4.hf //Truncate, V4 has converted value
+        \\  }
+        \\ {
+        \\   V5.h=V5.hf //Truncate, V5 has converted value
+        \\  }
+        \\ {
+        \\   V4=vmux(Q0,V4,V3) //If original pos value, use converted. Else 0
+        \\   V5=vmux(Q0,V5,V3) //If original pos value, use converted. Else 0
+        \\  }
+        \\ {
+        \\   V0.ub = vpack(V4.h,V5.h):sat
+        \\  }
+        \\ {
+        \\   V0.h = vshuff(V0.h)
+        \\   jumpr LR
+        \\  }
+    );
+}
+
+fn __qf_fast_convert_hf_to_uh_rne() align(32) callconv(.naked) noreturn {
+    asm volatile (
+        \\ //V0.hf has value to be converted
+        \\ {
+        \\   R1=#0x3800 //+.5
+        \\   V3=#0
+        \\  }
+        \\ {
+        \\   Q0=vcmp.gt(V0.hf,V3.hf) // hf value is pos (hf > 0)
+        \\   V1.h=vsplat(R1) //V1 = +.5
+        \\  }
+        \\ {
+        \\   V4.qf16=vadd(V0.hf,V1.hf) // Add +.5
+        \\  }
+        \\ {
+        \\   V4.hf=V4.qf16
+        \\  }
+        \\ {
+        \\   V4.h=V4.hf //Truncate, V4 has converted value
+        \\  }
+        \\ {
+        \\   V0=vmux(Q0,V4,V3) //If original pos value, use converted. Else 0
+        \\   jumpr LR
+        \\  }
+    );
+}
+
 comptime {
     if (builtin.cpu.arch == .hexagon) {
         symbol(&__hexagon_adddf3, "__hexagon_adddf3");
@@ -1785,5 +2363,15 @@ comptime {
         symbol(&__hexagon_modsi3, "__hexagon_modsi3");
         symbol(&__hexagon_memcpy_likely_aligned_min32bytes_mult8bytes, "__hexagon_memcpy_likely_aligned_min32bytes_mult8bytes");
         symbol(&__hexagon_udivsi3, "__hexagon_udivsi3");
+        if (builtin.cpu.has(.hexagon, .hvxv79)) {
+            symbol(&__qf_convert_hf_to_b_rne, "__qf_convert_hf_to_b_rne");
+            symbol(&__qf_fast_convert_hf_to_b_rne, "__qf_fast_convert_hf_to_b_rne");
+            symbol(&__qf_convert_hf_to_h_rne, "__qf_convert_hf_to_h_rne");
+            symbol(&__qf_fast_convert_hf_to_h_rne, "__qf_fast_convert_hf_to_h_rne");
+            symbol(&__qf_convert_hf_to_ub_rne, "__qf_convert_hf_to_ub_rne");
+            symbol(&__qf_fast_convert_hf_to_ub_rne, "__qf_fast_convert_hf_to_ub_rne");
+            symbol(&__qf_convert_hf_to_uh_rne, "__qf_convert_hf_to_uh_rne");
+            symbol(&__qf_fast_convert_hf_to_uh_rne, "__qf_fast_convert_hf_to_uh_rne");
+        }
     }
 }