From 3ed40b114020ff774279a5af993851d74da64b52 Mon Sep 17 00:00:00 2001 From: Andrew Kelley Date: Fri, 11 Aug 2023 16:15:19 -0700 Subject: [PATCH] update CPU features to LLVM 17 release/17.x branch, commit 8f4dd44097c9ae25dd203d5ac87f3b48f854bba8 --- lib/std/target/aarch64.zig | 53 ++++ lib/std/target/amdgpu.zig | 250 +++++++++++++++--- lib/std/target/arm.zig | 20 +- lib/std/target/avr.zig | 17 +- lib/std/target/bpf.zig | 4 +- lib/std/target/csky.zig | 20 +- lib/std/target/loongarch.zig | 17 ++ lib/std/target/m68k.zig | 15 ++ lib/std/target/nvptx.zig | 106 +++++--- lib/std/target/riscv.zig | 427 +++++++++++++++++++++++++++++-- lib/std/target/x86.zig | 469 ++++++++++++++++++++++------------ tools/update_cpu_features.zig | 39 +++ 12 files changed, 1142 insertions(+), 295 deletions(-) diff --git a/lib/std/target/aarch64.zig b/lib/std/target/aarch64.zig index e20448102d0bd2d94af180ee4893028191104fe3..011cb20aefbced7e2f787921de5d01e6d85f0b85 100644 --- a/lib/std/target/aarch64.zig +++ b/lib/std/target/aarch64.zig @@ -37,6 +37,7 @@ pub const Feature = enum { ccdp, ccidx, ccpp, + chk, clrbhb, cmp_bcc_fusion, complxnum, @@ -68,12 +69,14 @@ pub const Feature = enum { fptoint, fullfp16, fuse_address, + fuse_addsub_2reg_const1, fuse_adrp_add, fuse_aes, fuse_arith_logic, fuse_crypto_eor, fuse_csel, fuse_literals, + gcs, harden_sls_blr, harden_sls_nocomdat, harden_sls_retbr, @@ -96,6 +99,7 @@ pub const Feature = enum { nmi, no_bti_at_return_twice, no_neg_immediates, + no_sve_fp_ld1r, no_zcz_fp, nv, outline_atomics, @@ -173,6 +177,7 @@ pub const Feature = enum { tpidr_el1, tpidr_el2, tpidr_el3, + tpidrro_el0, tracev8_4, trbe, uaops, @@ -233,6 +238,7 @@ pub const all_features = blk: { .fuse_adrp_add, .fuse_aes, .fuse_literals, + .predictable_select_expensive, }), }; result[@intFromEnum(Feature.a710)] = .{ @@ -244,6 +250,7 @@ pub const all_features = blk: { .fuse_adrp_add, .fuse_aes, .lsl_fast, + .predictable_select_expensive, .use_postra_scheduler, }), }; @@ -255,6 +262,7 @@ pub const all_features = blk: { .fuse_adrp_add, .fuse_aes, .lsl_fast, + .predictable_select_expensive, }), }; result[@intFromEnum(Feature.a78)] = .{ @@ -266,6 +274,7 @@ pub const all_features = blk: { .fuse_adrp_add, .fuse_aes, .lsl_fast, + .predictable_select_expensive, .use_postra_scheduler, }), }; @@ -278,6 +287,7 @@ pub const all_features = blk: { .fuse_adrp_add, .fuse_aes, .lsl_fast, + .predictable_select_expensive, .use_postra_scheduler, }), }; @@ -415,6 +425,11 @@ pub const all_features = blk: { .description = "Enable v8.2 data Cache Clean to Point of Persistence (FEAT_DPB)", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.chk)] = .{ + .llvm_name = "chk", + .description = "Enable Armv8.0-A Check Feature Status Extension (FEAT_CHK)", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.clrbhb)] = .{ .llvm_name = "clrbhb", .description = "Enable Clear BHB instruction (FEAT_CLRBHB)", @@ -591,6 +606,11 @@ pub const all_features = blk: { .description = "CPU fuses address generation and memory operations", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.fuse_addsub_2reg_const1)] = .{ + .llvm_name = "fuse-addsub-2reg-const1", + .description = "CPU fuses (a + b + 1) and (a - b - 1)", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.fuse_adrp_add)] = .{ .llvm_name = "fuse-adrp-add", .description = "CPU fuses adrp+add operations", @@ -621,6 +641,13 @@ pub const all_features = blk: { .description = "CPU fuses literal generation operations", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.gcs)] = .{ + .llvm_name = "gcs", + .description = "Enable Armv9.4-A Guarded Call Stack Extension", + .dependencies = featureSet(&[_]Feature{ + .chk, + }), + }; result[@intFromEnum(Feature.harden_sls_blr)] = .{ .llvm_name = "harden-sls-blr", .description = "Harden against straight line speculation across BLR instructions", @@ -741,6 +768,11 @@ pub const all_features = blk: { .description = "Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.no_sve_fp_ld1r)] = .{ + .llvm_name = "no-sve-fp-ld1r", + .description = "Avoid using LD1RX instructions for FP", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.no_zcz_fp)] = .{ .llvm_name = "no-zcz-fp", .description = "Has no zero-cycle zeroing instructions for FP registers", @@ -1171,6 +1203,11 @@ pub const all_features = blk: { .description = "Permit use of TPIDR_EL3 for the TLS base", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.tpidrro_el0)] = .{ + .llvm_name = "tpidrro-el0", + .description = "Permit use of TPIDRRO_EL0 for the TLS base", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.tracev8_4)] = .{ .llvm_name = "tracev8.4", .description = "Enable v8.4-A Trace extension (FEAT_TRF)", @@ -1311,6 +1348,7 @@ pub const all_features = blk: { .llvm_name = "v8.9a", .description = "Support ARM v8.9a instructions", .dependencies = featureSet(&[_]Feature{ + .chk, .clrbhb, .cssc, .prfm_slc_target, @@ -1974,6 +2012,7 @@ pub const cpu = struct { .lsl_fast, .mte, .perfmon, + .predictable_select_expensive, .spe, .sve2_bitperm, .use_postra_scheduler, @@ -1991,6 +2030,7 @@ pub const cpu = struct { .fuse_aes, .fuse_literals, .perfmon, + .predictable_select_expensive, .v8a, }), }; @@ -2004,6 +2044,7 @@ pub const cpu = struct { .fuse_adrp_add, .fuse_aes, .perfmon, + .predictable_select_expensive, .v8a, }), }; @@ -2018,6 +2059,7 @@ pub const cpu = struct { .fuse_adrp_add, .fuse_aes, .perfmon, + .predictable_select_expensive, .rcpc, .v8_2a, }), @@ -2063,6 +2105,7 @@ pub const cpu = struct { .fuse_aes, .lsl_fast, .perfmon, + .predictable_select_expensive, .rcpc, .ssbs, .v8_2a, @@ -2126,6 +2169,7 @@ pub const cpu = struct { .fuse_aes, .lsl_fast, .perfmon, + .predictable_select_expensive, .rcpc, .spe, .ssbs, @@ -2149,6 +2193,7 @@ pub const cpu = struct { .lsl_fast, .pauth, .perfmon, + .predictable_select_expensive, .rcpc_immo, .spe, .ssbs, @@ -2171,6 +2216,7 @@ pub const cpu = struct { .lsl_fast, .mte, .perfmon, + .predictable_select_expensive, .sve2_bitperm, .use_postra_scheduler, .v9a, @@ -2190,6 +2236,7 @@ pub const cpu = struct { .lsl_fast, .mte, .perfmon, + .predictable_select_expensive, .spe, .sve2_bitperm, .use_postra_scheduler, @@ -2383,6 +2430,7 @@ pub const cpu = struct { .i8mm, .lsl_fast, .perfmon, + .predictable_select_expensive, .rand, .spe, .ssbs, @@ -2419,6 +2467,7 @@ pub const cpu = struct { .fuse_aes, .lsl_fast, .perfmon, + .predictable_select_expensive, .rcpc, .spe, .ssbs, @@ -2440,6 +2489,7 @@ pub const cpu = struct { .lsl_fast, .mte, .perfmon, + .predictable_select_expensive, .sve2_bitperm, .use_postra_scheduler, .v8_5a, @@ -2458,7 +2508,9 @@ pub const cpu = struct { .fuse_aes, .i8mm, .lsl_fast, + .no_sve_fp_ld1r, .perfmon, + .predictable_select_expensive, .rand, .spe, .ssbs, @@ -2480,6 +2532,7 @@ pub const cpu = struct { .lsl_fast, .mte, .perfmon, + .predictable_select_expensive, .rand, .spe, .sve2_bitperm, diff --git a/lib/std/target/amdgpu.zig b/lib/std/target/amdgpu.zig index 4fc47c8d729d694022119d27f49a5d4e9395aded..012f652088a0d74236e640d15e3490cdd4abaa89 100644 --- a/lib/std/target/amdgpu.zig +++ b/lib/std/target/amdgpu.zig @@ -10,14 +10,20 @@ pub const Feature = enum { add_no_carry_insts, aperture_regs, architected_flat_scratch, + architected_sgprs, + atomic_buffer_global_pk_add_f16_insts, + atomic_buffer_global_pk_add_f16_no_rtn_insts, + atomic_ds_pk_add_16_insts, atomic_fadd_no_rtn_insts, atomic_fadd_rtn_insts, - atomic_pk_fadd_no_rtn_insts, + atomic_flat_pk_add_16_insts, + atomic_global_pk_add_bf16_inst, auto_waitcnt_before_barrier, back_off_barrier, ci_insts, cumode, dl_insts, + dot10_insts, dot1_insts, dot2_insts, dot3_insts, @@ -46,6 +52,7 @@ pub const Feature = enum { fma_mix_insts, fmacf64_inst, fmaf, + force_store_sc0_sc1, fp64, fp8_insts, full_rate_64_ops, @@ -96,12 +103,11 @@ pub const Feature = enum { no_sdst_cmpx, nsa_clause_bug, nsa_encoding, - nsa_max_size_13, - nsa_max_size_5, nsa_to_vmem_bug, offset_3f_bug, packed_fp32_ops, packed_tid, + partial_nsa_encoding, pk_fmac_f16_inst, promote_alloca, prt_strict_null, @@ -187,6 +193,30 @@ pub const all_features = blk: { .description = "Flat Scratch register is a readonly SPI initialized architected register", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.architected_sgprs)] = .{ + .llvm_name = "architected-sgprs", + .description = "Enable the architected SGPRs", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.atomic_buffer_global_pk_add_f16_insts)] = .{ + .llvm_name = "atomic-buffer-global-pk-add-f16-insts", + .description = "Has buffer_atomic_pk_add_f16 and global_atomic_pk_add_f16 instructions that can return original value", + .dependencies = featureSet(&[_]Feature{ + .flat_global_insts, + }), + }; + result[@intFromEnum(Feature.atomic_buffer_global_pk_add_f16_no_rtn_insts)] = .{ + .llvm_name = "atomic-buffer-global-pk-add-f16-no-rtn-insts", + .description = "Has buffer_atomic_pk_add_f16 and global_atomic_pk_add_f16 instructions that don't return original value", + .dependencies = featureSet(&[_]Feature{ + .flat_global_insts, + }), + }; + result[@intFromEnum(Feature.atomic_ds_pk_add_16_insts)] = .{ + .llvm_name = "atomic-ds-pk-add-16-insts", + .description = "Has ds_pk_add_bf16, ds_pk_add_f16, ds_pk_add_rtn_bf16, ds_pk_add_rtn_f16 instructions", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.atomic_fadd_no_rtn_insts)] = .{ .llvm_name = "atomic-fadd-no-rtn-insts", .description = "Has buffer_atomic_add_f32 and global_atomic_add_f32 instructions that don't return original value", @@ -201,9 +231,14 @@ pub const all_features = blk: { .flat_global_insts, }), }; - result[@intFromEnum(Feature.atomic_pk_fadd_no_rtn_insts)] = .{ - .llvm_name = "atomic-pk-fadd-no-rtn-insts", - .description = "Has buffer_atomic_pk_add_f16 and global_atomic_pk_add_f16 instructions that don't return original value", + result[@intFromEnum(Feature.atomic_flat_pk_add_16_insts)] = .{ + .llvm_name = "atomic-flat-pk-add-16-insts", + .description = "Has flat_atomic_pk_add_f16 and flat_atomic_pk_add_bf16 instructions", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.atomic_global_pk_add_bf16_inst)] = .{ + .llvm_name = "atomic-global-pk-add-bf16-inst", + .description = "Has global_atomic_pk_add_bf16 instruction", .dependencies = featureSet(&[_]Feature{ .flat_global_insts, }), @@ -233,6 +268,11 @@ pub const all_features = blk: { .description = "Has v_fmac_f32 and v_xnor_b32 instructions", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.dot10_insts)] = .{ + .llvm_name = "dot10-insts", + .description = "Has v_dot2_f32_f16 instruction", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.dot1_insts)] = .{ .llvm_name = "dot1-insts", .description = "Has v_dot4_i32_i8 and v_dot8_i32_i4 instructions", @@ -265,7 +305,7 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.dot7_insts)] = .{ .llvm_name = "dot7-insts", - .description = "Has v_dot2_f32_f16, v_dot4_u32_u8, v_dot8_u32_u4 instructions", + .description = "Has v_dot4_u32_u8, v_dot8_u32_u4 instructions", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.dot8_insts)] = .{ @@ -373,6 +413,11 @@ pub const all_features = blk: { .description = "Enable single precision FMA (not as fast as mul+add, but fused)", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.force_store_sc0_sc1)] = .{ + .llvm_name = "force-store-sc0-sc1", + .description = "Has SC0 and SC1 on stores", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.fp64)] = .{ .llvm_name = "fp64", .description = "Enable double precision operations", @@ -742,16 +787,6 @@ pub const all_features = blk: { .description = "Support NSA encoding for image instructions", .dependencies = featureSet(&[_]Feature{}), }; - result[@intFromEnum(Feature.nsa_max_size_13)] = .{ - .llvm_name = "nsa-max-size-13", - .description = "The maximum non-sequential address size in VGPRs.", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@intFromEnum(Feature.nsa_max_size_5)] = .{ - .llvm_name = "nsa-max-size-5", - .description = "The maximum non-sequential address size in VGPRs.", - .dependencies = featureSet(&[_]Feature{}), - }; result[@intFromEnum(Feature.nsa_to_vmem_bug)] = .{ .llvm_name = "nsa-to-vmem-bug", .description = "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero", @@ -772,6 +807,11 @@ pub const all_features = blk: { .description = "Workitem IDs are packed into v0 at kernel launch", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.partial_nsa_encoding)] = .{ + .llvm_name = "partial-nsa-encoding", + .description = "Support partial NSA encoding for image instructions", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.pk_fmac_f16_inst)] = .{ .llvm_name = "pk-fmac-f16-inst", .description = "Has v_pk_fmac_f16 instruction", @@ -1146,7 +1186,6 @@ pub const cpu = struct { .negative_unaligned_scratch_offset_bug, .nsa_clause_bug, .nsa_encoding, - .nsa_max_size_5, .nsa_to_vmem_bug, .offset_3f_bug, .scalar_atomics, @@ -1166,6 +1205,7 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .back_off_barrier, .dl_insts, + .dot10_insts, .dot1_insts, .dot2_insts, .dot5_insts, @@ -1183,7 +1223,6 @@ pub const cpu = struct { .negative_unaligned_scratch_offset_bug, .nsa_clause_bug, .nsa_encoding, - .nsa_max_size_5, .nsa_to_vmem_bug, .offset_3f_bug, .scalar_atomics, @@ -1203,6 +1242,7 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .back_off_barrier, .dl_insts, + .dot10_insts, .dot1_insts, .dot2_insts, .dot5_insts, @@ -1220,7 +1260,6 @@ pub const cpu = struct { .negative_unaligned_scratch_offset_bug, .nsa_clause_bug, .nsa_encoding, - .nsa_max_size_5, .nsa_to_vmem_bug, .offset_3f_bug, .scalar_atomics, @@ -1253,7 +1292,6 @@ pub const cpu = struct { .negative_unaligned_scratch_offset_bug, .nsa_clause_bug, .nsa_encoding, - .nsa_max_size_5, .nsa_to_vmem_bug, .offset_3f_bug, .scalar_atomics, @@ -1273,6 +1311,7 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .back_off_barrier, .dl_insts, + .dot10_insts, .dot1_insts, .dot2_insts, .dot5_insts, @@ -1284,7 +1323,6 @@ pub const cpu = struct { .gfx10_b_encoding, .ldsbankcount32, .nsa_encoding, - .nsa_max_size_13, .shader_cycles_register, .wavefrontsize32, }), @@ -1295,6 +1333,7 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .back_off_barrier, .dl_insts, + .dot10_insts, .dot1_insts, .dot2_insts, .dot5_insts, @@ -1306,7 +1345,6 @@ pub const cpu = struct { .gfx10_b_encoding, .ldsbankcount32, .nsa_encoding, - .nsa_max_size_13, .shader_cycles_register, .wavefrontsize32, }), @@ -1317,6 +1355,7 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .back_off_barrier, .dl_insts, + .dot10_insts, .dot1_insts, .dot2_insts, .dot5_insts, @@ -1328,7 +1367,6 @@ pub const cpu = struct { .gfx10_b_encoding, .ldsbankcount32, .nsa_encoding, - .nsa_max_size_13, .shader_cycles_register, .wavefrontsize32, }), @@ -1339,6 +1377,7 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .back_off_barrier, .dl_insts, + .dot10_insts, .dot1_insts, .dot2_insts, .dot5_insts, @@ -1350,7 +1389,6 @@ pub const cpu = struct { .gfx10_b_encoding, .ldsbankcount32, .nsa_encoding, - .nsa_max_size_13, .shader_cycles_register, .wavefrontsize32, }), @@ -1361,6 +1399,7 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .back_off_barrier, .dl_insts, + .dot10_insts, .dot1_insts, .dot2_insts, .dot5_insts, @@ -1372,7 +1411,6 @@ pub const cpu = struct { .gfx10_b_encoding, .ldsbankcount32, .nsa_encoding, - .nsa_max_size_13, .shader_cycles_register, .wavefrontsize32, }), @@ -1383,6 +1421,7 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .back_off_barrier, .dl_insts, + .dot10_insts, .dot1_insts, .dot2_insts, .dot5_insts, @@ -1394,7 +1433,6 @@ pub const cpu = struct { .gfx10_b_encoding, .ldsbankcount32, .nsa_encoding, - .nsa_max_size_13, .shader_cycles_register, .wavefrontsize32, }), @@ -1405,6 +1443,7 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .back_off_barrier, .dl_insts, + .dot10_insts, .dot1_insts, .dot2_insts, .dot5_insts, @@ -1416,7 +1455,6 @@ pub const cpu = struct { .gfx10_b_encoding, .ldsbankcount32, .nsa_encoding, - .nsa_max_size_13, .shader_cycles_register, .wavefrontsize32, }), @@ -1429,6 +1467,7 @@ pub const cpu = struct { .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, .dl_insts, + .dot10_insts, .dot5_insts, .dot7_insts, .dot8_insts, @@ -1440,8 +1479,8 @@ pub const cpu = struct { .ldsbankcount32, .mad_intra_fwd_bug, .nsa_encoding, - .nsa_max_size_5, .packed_tid, + .partial_nsa_encoding, .shader_cycles_register, .user_sgpr_init16_bug, .valu_trans_use_hazard, @@ -1457,6 +1496,7 @@ pub const cpu = struct { .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, .dl_insts, + .dot10_insts, .dot5_insts, .dot7_insts, .dot8_insts, @@ -1468,8 +1508,8 @@ pub const cpu = struct { .ldsbankcount32, .mad_intra_fwd_bug, .nsa_encoding, - .nsa_max_size_5, .packed_tid, + .partial_nsa_encoding, .shader_cycles_register, .valu_trans_use_hazard, .vcmpx_permlane_hazard, @@ -1484,6 +1524,7 @@ pub const cpu = struct { .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, .dl_insts, + .dot10_insts, .dot5_insts, .dot7_insts, .dot8_insts, @@ -1494,8 +1535,8 @@ pub const cpu = struct { .ldsbankcount32, .mad_intra_fwd_bug, .nsa_encoding, - .nsa_max_size_5, .packed_tid, + .partial_nsa_encoding, .shader_cycles_register, .user_sgpr_init16_bug, .valu_trans_use_hazard, @@ -1511,6 +1552,7 @@ pub const cpu = struct { .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, .dl_insts, + .dot10_insts, .dot5_insts, .dot7_insts, .dot8_insts, @@ -1521,14 +1563,67 @@ pub const cpu = struct { .ldsbankcount32, .mad_intra_fwd_bug, .nsa_encoding, - .nsa_max_size_5, .packed_tid, + .partial_nsa_encoding, .shader_cycles_register, .valu_trans_use_hazard, .vcmpx_permlane_hazard, .wavefrontsize32, }), }; + pub const gfx1150 = CpuModel{ + .name = "gfx1150", + .llvm_name = "gfx1150", + .features = featureSet(&[_]Feature{ + .architected_flat_scratch, + .atomic_fadd_no_rtn_insts, + .atomic_fadd_rtn_insts, + .dl_insts, + .dot10_insts, + .dot5_insts, + .dot7_insts, + .dot8_insts, + .dot9_insts, + .flat_atomic_fadd_f32_inst, + .gfx11, + .image_insts, + .ldsbankcount32, + .mad_intra_fwd_bug, + .nsa_encoding, + .packed_tid, + .partial_nsa_encoding, + .shader_cycles_register, + .vcmpx_permlane_hazard, + .wavefrontsize32, + }), + }; + pub const gfx1151 = CpuModel{ + .name = "gfx1151", + .llvm_name = "gfx1151", + .features = featureSet(&[_]Feature{ + .architected_flat_scratch, + .atomic_fadd_no_rtn_insts, + .atomic_fadd_rtn_insts, + .dl_insts, + .dot10_insts, + .dot5_insts, + .dot7_insts, + .dot8_insts, + .dot9_insts, + .flat_atomic_fadd_f32_inst, + .gfx11, + .gfx11_full_vgprs, + .image_insts, + .ldsbankcount32, + .mad_intra_fwd_bug, + .nsa_encoding, + .packed_tid, + .partial_nsa_encoding, + .shader_cycles_register, + .vcmpx_permlane_hazard, + .wavefrontsize32, + }), + }; pub const gfx600 = CpuModel{ .name = "gfx600", .llvm_name = "gfx600", @@ -1702,6 +1797,7 @@ pub const cpu = struct { .llvm_name = "gfx906", .features = featureSet(&[_]Feature{ .dl_insts, + .dot10_insts, .dot1_insts, .dot2_insts, .dot7_insts, @@ -1721,9 +1817,10 @@ pub const cpu = struct { .name = "gfx908", .llvm_name = "gfx908", .features = featureSet(&[_]Feature{ + .atomic_buffer_global_pk_add_f16_no_rtn_insts, .atomic_fadd_no_rtn_insts, - .atomic_pk_fadd_no_rtn_insts, .dl_insts, + .dot10_insts, .dot1_insts, .dot2_insts, .dot3_insts, @@ -1764,11 +1861,12 @@ pub const cpu = struct { .name = "gfx90a", .llvm_name = "gfx90a", .features = featureSet(&[_]Feature{ + .atomic_buffer_global_pk_add_f16_insts, .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, - .atomic_pk_fadd_no_rtn_insts, .back_off_barrier, .dl_insts, + .dot10_insts, .dot1_insts, .dot2_insts, .dot3_insts, @@ -1811,11 +1909,93 @@ pub const cpu = struct { .llvm_name = "gfx940", .features = featureSet(&[_]Feature{ .architected_flat_scratch, + .atomic_buffer_global_pk_add_f16_insts, + .atomic_ds_pk_add_16_insts, .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, - .atomic_pk_fadd_no_rtn_insts, + .atomic_flat_pk_add_16_insts, + .atomic_global_pk_add_bf16_inst, .back_off_barrier, .dl_insts, + .dot10_insts, + .dot1_insts, + .dot2_insts, + .dot3_insts, + .dot4_insts, + .dot5_insts, + .dot6_insts, + .dot7_insts, + .dpp_64bit, + .flat_atomic_fadd_f32_inst, + .fma_mix_insts, + .fmacf64_inst, + .force_store_sc0_sc1, + .fp8_insts, + .full_rate_64_ops, + .gfx9, + .gfx90a_insts, + .gfx940_insts, + .ldsbankcount32, + .mai_insts, + .packed_fp32_ops, + .packed_tid, + .pk_fmac_f16_inst, + .sramecc_support, + }), + }; + pub const gfx941 = CpuModel{ + .name = "gfx941", + .llvm_name = "gfx941", + .features = featureSet(&[_]Feature{ + .architected_flat_scratch, + .atomic_buffer_global_pk_add_f16_insts, + .atomic_ds_pk_add_16_insts, + .atomic_fadd_no_rtn_insts, + .atomic_fadd_rtn_insts, + .atomic_flat_pk_add_16_insts, + .atomic_global_pk_add_bf16_inst, + .back_off_barrier, + .dl_insts, + .dot10_insts, + .dot1_insts, + .dot2_insts, + .dot3_insts, + .dot4_insts, + .dot5_insts, + .dot6_insts, + .dot7_insts, + .dpp_64bit, + .flat_atomic_fadd_f32_inst, + .fma_mix_insts, + .fmacf64_inst, + .force_store_sc0_sc1, + .fp8_insts, + .full_rate_64_ops, + .gfx9, + .gfx90a_insts, + .gfx940_insts, + .ldsbankcount32, + .mai_insts, + .packed_fp32_ops, + .packed_tid, + .pk_fmac_f16_inst, + .sramecc_support, + }), + }; + pub const gfx942 = CpuModel{ + .name = "gfx942", + .llvm_name = "gfx942", + .features = featureSet(&[_]Feature{ + .architected_flat_scratch, + .atomic_buffer_global_pk_add_f16_insts, + .atomic_ds_pk_add_16_insts, + .atomic_fadd_no_rtn_insts, + .atomic_fadd_rtn_insts, + .atomic_flat_pk_add_16_insts, + .atomic_global_pk_add_bf16_inst, + .back_off_barrier, + .dl_insts, + .dot10_insts, .dot1_insts, .dot2_insts, .dot3_insts, diff --git a/lib/std/target/arm.zig b/lib/std/target/arm.zig index a78fd6785addfbd27b7b507a91987182977ee732..5245b3357e470275c178249fb7a834beed0e244a 100644 --- a/lib/std/target/arm.zig +++ b/lib/std/target/arm.zig @@ -122,7 +122,9 @@ pub const Feature = enum { r4, ras, rclass, - read_tp_hard, + read_tp_tpidrprw, + read_tp_tpidruro, + read_tp_tpidrurw, reserve_r9, ret_addr_stack, sb, @@ -949,9 +951,19 @@ pub const all_features = blk: { .description = "Is realtime profile ('R' series)", .dependencies = featureSet(&[_]Feature{}), }; - result[@intFromEnum(Feature.read_tp_hard)] = .{ - .llvm_name = "read-tp-hard", - .description = "Reading thread pointer from register", + result[@intFromEnum(Feature.read_tp_tpidrprw)] = .{ + .llvm_name = "read-tp-tpidrprw", + .description = "Reading thread pointer from TPIDRPRW register", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.read_tp_tpidruro)] = .{ + .llvm_name = "read-tp-tpidruro", + .description = "Reading thread pointer from TPIDRURO register", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.read_tp_tpidrurw)] = .{ + .llvm_name = "read-tp-tpidrurw", + .description = "Reading thread pointer from TPIDRURW register", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.reserve_r9)] = .{ diff --git a/lib/std/target/avr.zig b/lib/std/target/avr.zig index a39475cb2a2028c4734fd91632471ba2dbdbcb6c..bda274d2e6434a040396e37ef031fac4be865d86 100644 --- a/lib/std/target/avr.zig +++ b/lib/std/target/avr.zig @@ -25,12 +25,12 @@ pub const Feature = enum { elpmx, ijmpcall, jmpcall, + lowbytefirst, lpm, lpmx, memmappedregs, movw, mul, - progmem, rmw, smallstack, special, @@ -69,7 +69,6 @@ pub const all_features = blk: { .avr0, .lpm, .memmappedregs, - .progmem, }), }; result[@intFromEnum(Feature.avr2)] = .{ @@ -207,6 +206,11 @@ pub const all_features = blk: { .description = "The device supports the `JMP` and `CALL` instructions", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.lowbytefirst)] = .{ + .llvm_name = "lowbytefirst", + .description = "Do the low byte first when writing a 16-bit port or storing a 16-bit word", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.lpm)] = .{ .llvm_name = "lpm", .description = "The device supports the `LPM` instruction", @@ -232,11 +236,6 @@ pub const all_features = blk: { .description = "The device supports the multiplication instructions", .dependencies = featureSet(&[_]Feature{}), }; - result[@intFromEnum(Feature.progmem)] = .{ - .llvm_name = "progmem", - .description = "The device has a separate flash namespace", - .dependencies = featureSet(&[_]Feature{}), - }; result[@intFromEnum(Feature.rmw)] = .{ .llvm_name = "rmw", .description = "The device supports the read-write-modify instructions: XCH, LAS, LAC, LAT", @@ -303,11 +302,11 @@ pub const all_features = blk: { .elpmx, .ijmpcall, .jmpcall, + .lowbytefirst, .lpm, .lpmx, .movw, .mul, - .progmem, .spm, .spmx, .sram, @@ -322,11 +321,11 @@ pub const all_features = blk: { .@"break", .ijmpcall, .jmpcall, + .lowbytefirst, .lpm, .lpmx, .movw, .mul, - .progmem, .sram, }), }; diff --git a/lib/std/target/bpf.zig b/lib/std/target/bpf.zig index 35f4aac57fe84714965bf51eb9c66df80ce97c90..40dc2d1c7e90229adde8e4769b3d41dea0767523 100644 --- a/lib/std/target/bpf.zig +++ b/lib/std/target/bpf.zig @@ -66,6 +66,8 @@ pub const cpu = struct { pub const v3 = CpuModel{ .name = "v3", .llvm_name = "v3", - .features = featureSet(&[_]Feature{}), + .features = featureSet(&[_]Feature{ + .alu32, + }), }; }; diff --git a/lib/std/target/csky.zig b/lib/std/target/csky.zig index ef153a2708e5345563edf9601feeb5b401095378..3f41fa886d26de48a1c201bc2ba28ac4b2ba4731 100644 --- a/lib/std/target/csky.zig +++ b/lib/std/target/csky.zig @@ -214,7 +214,7 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.dsp_silan)] = .{ .llvm_name = "dsp_silan", - .description = "Enable DSP Silan instructions", + .description = "Enable DSP Silan instrutions", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.dspe60)] = .{ @@ -224,7 +224,7 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.dspv2)] = .{ .llvm_name = "dspv2", - .description = "Enable DSP V2.0 instructions", + .description = "Enable DSP V2.0 instrutions", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.e1)] = .{ @@ -243,7 +243,7 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.edsp)] = .{ .llvm_name = "edsp", - .description = "Enable DSP instructions", + .description = "Enable DSP instrutions", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.elrw)] = .{ @@ -298,12 +298,12 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.fpuv3_hf)] = .{ .llvm_name = "fpuv3_hf", - .description = "Enable FPUv3 harf precision operate instructions", + .description = "Enable FPUv3 half precision operate instructions", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.fpuv3_hi)] = .{ .llvm_name = "fpuv3_hi", - .description = "Enable FPUv3 harf word converting instructions", + .description = "Enable FPUv3 half word converting instructions", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.fpuv3_sf)] = .{ @@ -333,12 +333,12 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.hwdiv)] = .{ .llvm_name = "hwdiv", - .description = "Enable divide instructions", + .description = "Enable divide instrutions", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.istack)] = .{ .llvm_name = "istack", - .description = "Enable interrupt attribute", + .description = "Enable interrput attribute", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.java)] = .{ @@ -362,7 +362,7 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.multiple_stld)] = .{ .llvm_name = "multiple_stld", - .description = "Enable multiple load/store instructions", + .description = "Enable multiple load/store instrutions", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.nvic)] = .{ @@ -372,7 +372,7 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.pushpop)] = .{ .llvm_name = "pushpop", - .description = "Enable push/pop instructions", + .description = "Enable push/pop instrutions", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.smart)] = .{ @@ -3079,7 +3079,7 @@ pub const cpu = struct { .btst16, }), }; - pub const @"i805" = CpuModel{ + pub const i805 = CpuModel{ .name = "i805", .llvm_name = "i805", .features = featureSet(&[_]Feature{ diff --git a/lib/std/target/loongarch.zig b/lib/std/target/loongarch.zig index 6f0bf426bb05da9323589c55fd8cce03373ecb80..65dc33d78487dc6c7e31a1d389e319b693b51de8 100644 --- a/lib/std/target/loongarch.zig +++ b/lib/std/target/loongarch.zig @@ -16,6 +16,7 @@ pub const Feature = enum { lbt, lsx, lvz, + ual, }; pub const featureSet = CpuFeature.feature_set_fns(Feature).featureSet; @@ -88,6 +89,11 @@ pub const all_features = blk: { .description = "'LVZ' (Loongson Virtualization Extension)", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.ual)] = .{ + .llvm_name = "ual", + .description = "Allow memory accesses to be unaligned", + .dependencies = featureSet(&[_]Feature{}), + }; const ti = @typeInfo(Feature); for (&result, 0..) |*elem, i| { elem.index = i; @@ -114,6 +120,7 @@ pub const cpu = struct { .llvm_name = "generic-la64", .features = featureSet(&[_]Feature{ .@"64bit", + .ual, }), }; pub const la464 = CpuModel{ @@ -124,6 +131,16 @@ pub const cpu = struct { .lasx, .lbt, .lvz, + .ual, + }), + }; + pub const loongarch64 = CpuModel{ + .name = "loongarch64", + .llvm_name = "loongarch64", + .features = featureSet(&[_]Feature{ + .@"64bit", + .d, + .ual, }), }; }; diff --git a/lib/std/target/m68k.zig b/lib/std/target/m68k.zig index 422b95ca177a321e7b67d7811f87a6c9bc31ff68..054b3974d1fc08eb06ccc2d4933b2e6d14b16d70 100644 --- a/lib/std/target/m68k.zig +++ b/lib/std/target/m68k.zig @@ -11,6 +11,8 @@ pub const Feature = enum { isa_68030, isa_68040, isa_68060, + isa_68881, + isa_68882, reserve_a0, reserve_a1, reserve_a2, @@ -68,6 +70,7 @@ pub const all_features = blk: { .description = "Is M68040 ISA supported", .dependencies = featureSet(&[_]Feature{ .isa_68030, + .isa_68882, }), }; result[@intFromEnum(Feature.isa_68060)] = .{ @@ -77,6 +80,18 @@ pub const all_features = blk: { .isa_68040, }), }; + result[@intFromEnum(Feature.isa_68881)] = .{ + .llvm_name = "isa-68881", + .description = "Is M68881 (FPU) ISA supported", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.isa_68882)] = .{ + .llvm_name = "isa-68882", + .description = "Is M68882 (FPU) ISA supported", + .dependencies = featureSet(&[_]Feature{ + .isa_68881, + }), + }; result[@intFromEnum(Feature.reserve_a0)] = .{ .llvm_name = "reserve-a0", .description = "Reserve A0 register", diff --git a/lib/std/target/nvptx.zig b/lib/std/target/nvptx.zig index dfe3061bae4440f9c2a7b2b033f5483ed7a52239..fa2ea2e5499ec18be6f89d73e8ac7a3d8867afc0 100644 --- a/lib/std/target/nvptx.zig +++ b/lib/std/target/nvptx.zig @@ -25,6 +25,8 @@ pub const Feature = enum { ptx76, ptx77, ptx78, + ptx80, + ptx81, sm_20, sm_21, sm_30, @@ -45,6 +47,7 @@ pub const Feature = enum { sm_87, sm_89, sm_90, + sm_90, }; pub const featureSet = CpuFeature.feature_set_fns(Feature).featureSet; @@ -58,202 +61,217 @@ pub const all_features = blk: { var result: [len]CpuFeature = undefined; result[@intFromEnum(Feature.ptx32)] = .{ .llvm_name = "ptx32", - .description = "Use PTX version 3.2", + .description = "Use PTX version 32", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.ptx40)] = .{ .llvm_name = "ptx40", - .description = "Use PTX version 4.0", + .description = "Use PTX version 40", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.ptx41)] = .{ .llvm_name = "ptx41", - .description = "Use PTX version 4.1", + .description = "Use PTX version 41", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.ptx42)] = .{ .llvm_name = "ptx42", - .description = "Use PTX version 4.2", + .description = "Use PTX version 42", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.ptx43)] = .{ .llvm_name = "ptx43", - .description = "Use PTX version 4.3", + .description = "Use PTX version 43", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.ptx50)] = .{ .llvm_name = "ptx50", - .description = "Use PTX version 5.0", + .description = "Use PTX version 50", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.ptx60)] = .{ .llvm_name = "ptx60", - .description = "Use PTX version 6.0", + .description = "Use PTX version 60", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.ptx61)] = .{ .llvm_name = "ptx61", - .description = "Use PTX version 6.1", + .description = "Use PTX version 61", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.ptx63)] = .{ .llvm_name = "ptx63", - .description = "Use PTX version 6.3", + .description = "Use PTX version 63", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.ptx64)] = .{ .llvm_name = "ptx64", - .description = "Use PTX version 6.4", + .description = "Use PTX version 64", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.ptx65)] = .{ .llvm_name = "ptx65", - .description = "Use PTX version 6.5", + .description = "Use PTX version 65", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.ptx70)] = .{ .llvm_name = "ptx70", - .description = "Use PTX version 7.0", + .description = "Use PTX version 70", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.ptx71)] = .{ .llvm_name = "ptx71", - .description = "Use PTX version 7.1", + .description = "Use PTX version 71", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.ptx72)] = .{ .llvm_name = "ptx72", - .description = "Use PTX version 7.2", + .description = "Use PTX version 72", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.ptx73)] = .{ .llvm_name = "ptx73", - .description = "Use PTX version 7.3", + .description = "Use PTX version 73", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.ptx74)] = .{ .llvm_name = "ptx74", - .description = "Use PTX version 7.4", + .description = "Use PTX version 74", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.ptx75)] = .{ .llvm_name = "ptx75", - .description = "Use PTX version 7.5", + .description = "Use PTX version 75", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.ptx76)] = .{ .llvm_name = "ptx76", - .description = "Use PTX version 7.6", + .description = "Use PTX version 76", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.ptx77)] = .{ .llvm_name = "ptx77", - .description = "Use PTX version 7.7", + .description = "Use PTX version 77", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.ptx78)] = .{ .llvm_name = "ptx78", - .description = "Use PTX version 7.8", + .description = "Use PTX version 78", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.ptx80)] = .{ + .llvm_name = "ptx80", + .description = "Use PTX version 80", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.ptx81)] = .{ + .llvm_name = "ptx81", + .description = "Use PTX version 81", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.sm_20)] = .{ .llvm_name = "sm_20", - .description = "Target SM 2.0", + .description = "Target SM 20", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.sm_21)] = .{ .llvm_name = "sm_21", - .description = "Target SM 2.1", + .description = "Target SM 21", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.sm_30)] = .{ .llvm_name = "sm_30", - .description = "Target SM 3.0", + .description = "Target SM 30", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.sm_32)] = .{ .llvm_name = "sm_32", - .description = "Target SM 3.2", + .description = "Target SM 32", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.sm_35)] = .{ .llvm_name = "sm_35", - .description = "Target SM 3.5", + .description = "Target SM 35", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.sm_37)] = .{ .llvm_name = "sm_37", - .description = "Target SM 3.7", + .description = "Target SM 37", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.sm_50)] = .{ .llvm_name = "sm_50", - .description = "Target SM 5.0", + .description = "Target SM 50", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.sm_52)] = .{ .llvm_name = "sm_52", - .description = "Target SM 5.2", + .description = "Target SM 52", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.sm_53)] = .{ .llvm_name = "sm_53", - .description = "Target SM 5.3", + .description = "Target SM 53", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.sm_60)] = .{ .llvm_name = "sm_60", - .description = "Target SM 6.0", + .description = "Target SM 60", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.sm_61)] = .{ .llvm_name = "sm_61", - .description = "Target SM 6.1", + .description = "Target SM 61", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.sm_62)] = .{ .llvm_name = "sm_62", - .description = "Target SM 6.2", + .description = "Target SM 62", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.sm_70)] = .{ .llvm_name = "sm_70", - .description = "Target SM 7.0", + .description = "Target SM 70", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.sm_72)] = .{ .llvm_name = "sm_72", - .description = "Target SM 7.2", + .description = "Target SM 72", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.sm_75)] = .{ .llvm_name = "sm_75", - .description = "Target SM 7.5", + .description = "Target SM 75", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.sm_80)] = .{ .llvm_name = "sm_80", - .description = "Target SM 8.0", + .description = "Target SM 80", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.sm_86)] = .{ .llvm_name = "sm_86", - .description = "Target SM 8.6", + .description = "Target SM 86", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.sm_87)] = .{ .llvm_name = "sm_87", - .description = "Target SM 8.7", + .description = "Target SM 87", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.sm_89)] = .{ .llvm_name = "sm_89", - .description = "Target SM 8.9", + .description = "Target SM 89", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.sm_90)] = .{ .llvm_name = "sm_90", - .description = "Target SM 9.0", + .description = "Target SM 90", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.sm_90)] = .{ + .llvm_name = "sm_90", + .description = "Target SM 90", .dependencies = featureSet(&[_]Feature{}), }; const ti = @typeInfo(Feature); @@ -424,4 +442,12 @@ pub const cpu = struct { .sm_90, }), }; + pub const sm_90a = CpuModel{ + .name = "sm_90a", + .llvm_name = "sm_90a", + .features = featureSet(&[_]Feature{ + .ptx80, + .sm_90, + }), + }; }; diff --git a/lib/std/target/riscv.zig b/lib/std/target/riscv.zig index 8e49a6b180848731cbb45ffa50a1f8aa685d6a68..66c02ae6d093d0057d5f8d7a012017015301ccf7 100644 --- a/lib/std/target/riscv.zig +++ b/lib/std/target/riscv.zig @@ -10,14 +10,33 @@ pub const Feature = enum { a, c, d, + dlen_factor_2, e, - experimental_zawrs, - experimental_zca, - experimental_zcd, - experimental_zcf, + experimental_smaia, + experimental_ssaia, + experimental_zacas, + experimental_zfa, + experimental_zfbfmin, + experimental_zicond, experimental_zihintntl, experimental_ztso, - experimental_zvfh, + experimental_zvbb, + experimental_zvbc, + experimental_zvfbfmin, + experimental_zvfbfwma, + experimental_zvkg, + experimental_zvkn, + experimental_zvknc, + experimental_zvkned, + experimental_zvkng, + experimental_zvknha, + experimental_zvknhb, + experimental_zvks, + experimental_zvksc, + experimental_zvksed, + experimental_zvksg, + experimental_zvksh, + experimental_zvkt, f, forced_atomics, h, @@ -59,15 +78,32 @@ pub const Feature = enum { reserve_x8, reserve_x9, save_restore, + seq_cst_trailing_fence, short_forward_branch_opt, svinval, svnapot, svpbmt, tagged_globals, unaligned_scalar_mem, + unaligned_vector_mem, v, + xcvbitmanip, + xcvmac, + xsfcie, + xsfvcp, + xtheadba, + xtheadbb, + xtheadbs, + xtheadcmo, + xtheadcondmov, + xtheadfmemidx, + xtheadmac, + xtheadmemidx, + xtheadmempair, + xtheadsync, xtheadvdot, xventanacondops, + zawrs, zba, zbb, zbc, @@ -75,6 +111,13 @@ pub const Feature = enum { zbkc, zbkx, zbs, + zca, + zcb, + zcd, + zce, + zcf, + zcmp, + zcmt, zdinx, zfh, zfhmin, @@ -84,7 +127,11 @@ pub const Feature = enum { zicbom, zicbop, zicboz, + zicntr, + zicsr, + zifencei, zihintpause, + zihpm, zk, zkn, zknd, @@ -101,6 +148,7 @@ pub const Feature = enum { zve64d, zve64f, zve64x, + zvfh, zvl1024b, zvl128b, zvl16384b, @@ -151,34 +199,53 @@ pub const all_features = blk: { .f, }), }; + result[@intFromEnum(Feature.dlen_factor_2)] = .{ + .llvm_name = "dlen-factor-2", + .description = "Vector unit DLEN(data path width) is half of VLEN", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.e)] = .{ .llvm_name = "e", - .description = "Implements RV32E (provides 16 rather than 32 GPRs)", + .description = "Implements RV{32,64}E (provides 16 rather than 32 GPRs)", .dependencies = featureSet(&[_]Feature{}), }; - result[@intFromEnum(Feature.experimental_zawrs)] = .{ - .llvm_name = "experimental-zawrs", - .description = "'Zawrs' (Wait on Reservation Set)", + result[@intFromEnum(Feature.experimental_smaia)] = .{ + .llvm_name = "experimental-smaia", + .description = "'Smaia' (Smaia encompasses all added CSRs and all modifications to interrupt response behavior that the AIA specifies for a hart, over all privilege levels.)", .dependencies = featureSet(&[_]Feature{}), }; - result[@intFromEnum(Feature.experimental_zca)] = .{ - .llvm_name = "experimental-zca", - .description = "'Zca' (part of the C extension, excluding compressed floating point loads/stores)", + result[@intFromEnum(Feature.experimental_ssaia)] = .{ + .llvm_name = "experimental-ssaia", + .description = "'Ssaia' (Ssaia is essentially the same as Smaia except excluding the machine-level CSRs and behavior not directly visible to supervisor level.)", .dependencies = featureSet(&[_]Feature{}), }; - result[@intFromEnum(Feature.experimental_zcd)] = .{ - .llvm_name = "experimental-zcd", - .description = "'Zcd' (Compressed Double-Precision Floating-Point Instructions)", + result[@intFromEnum(Feature.experimental_zacas)] = .{ + .llvm_name = "experimental-zacas", + .description = "'Zacas' (Atomic Compare-And-Swap Instructions)", .dependencies = featureSet(&[_]Feature{}), }; - result[@intFromEnum(Feature.experimental_zcf)] = .{ - .llvm_name = "experimental-zcf", - .description = "'Zcf' (Compressed Single-Precision Floating-Point Instructions)", + result[@intFromEnum(Feature.experimental_zfa)] = .{ + .llvm_name = "experimental-zfa", + .description = "'Zfa' (Additional Floating-Point)", + .dependencies = featureSet(&[_]Feature{ + .f, + }), + }; + result[@intFromEnum(Feature.experimental_zfbfmin)] = .{ + .llvm_name = "experimental-zfbfmin", + .description = "'Zfbfmin' (Scalar BF16 Converts)", + .dependencies = featureSet(&[_]Feature{ + .f, + }), + }; + result[@intFromEnum(Feature.experimental_zicond)] = .{ + .llvm_name = "experimental-zicond", + .description = "'Zicond' (Integer Conditional Operations)", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.experimental_zihintntl)] = .{ .llvm_name = "experimental-zihintntl", - .description = "'zihintntl' (Non-Temporal Locality Hints)", + .description = "'Zihintntl' (Non-Temporal Locality Hints)", .dependencies = featureSet(&[_]Feature{}), }; result[@intFromEnum(Feature.experimental_ztso)] = .{ @@ -186,17 +253,103 @@ pub const all_features = blk: { .description = "'Ztso' (Memory Model - Total Store Order)", .dependencies = featureSet(&[_]Feature{}), }; - result[@intFromEnum(Feature.experimental_zvfh)] = .{ - .llvm_name = "experimental-zvfh", - .description = "'Zvfh' (Vector Half-Precision Floating-Point)", + result[@intFromEnum(Feature.experimental_zvbb)] = .{ + .llvm_name = "experimental-zvbb", + .description = "'Zvbb' (Vector Bit-manipulation used in Cryptography)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.experimental_zvbc)] = .{ + .llvm_name = "experimental-zvbc", + .description = "'Zvbc' (Vector Carryless Multiplication)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.experimental_zvfbfmin)] = .{ + .llvm_name = "experimental-zvfbfmin", + .description = "'Zvbfmin' (Vector BF16 Converts)", .dependencies = featureSet(&[_]Feature{ .zve32f, }), }; + result[@intFromEnum(Feature.experimental_zvfbfwma)] = .{ + .llvm_name = "experimental-zvfbfwma", + .description = "'Zvfbfwma' (Vector BF16 widening mul-add)", + .dependencies = featureSet(&[_]Feature{ + .zve32f, + }), + }; + result[@intFromEnum(Feature.experimental_zvkg)] = .{ + .llvm_name = "experimental-zvkg", + .description = "'Zvkg' (Vector GCM instructions for Cryptography)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.experimental_zvkn)] = .{ + .llvm_name = "experimental-zvkn", + .description = "This extension is shorthand for the following set of other extensions: Zvkned, Zvknhb, Zvbb, Zvbc, and Zvkt.", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.experimental_zvknc)] = .{ + .llvm_name = "experimental-zvknc", + .description = "This extension is shorthand for the following set of other extensions: Zvkn and Zvbc.", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.experimental_zvkned)] = .{ + .llvm_name = "experimental-zvkned", + .description = "'Zvkned' (Vector AES Encryption & Decryption (Single Round))", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.experimental_zvkng)] = .{ + .llvm_name = "experimental-zvkng", + .description = "This extension is shorthand for the following set of other extensions: Zvkn and Zvkg.", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.experimental_zvknha)] = .{ + .llvm_name = "experimental-zvknha", + .description = "'Zvknha' (Vector SHA-2 (SHA-256 only))", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.experimental_zvknhb)] = .{ + .llvm_name = "experimental-zvknhb", + .description = "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))", + .dependencies = featureSet(&[_]Feature{ + .experimental_zvknha, + }), + }; + result[@intFromEnum(Feature.experimental_zvks)] = .{ + .llvm_name = "experimental-zvks", + .description = "This extension is shorthand for the following set of other extensions: Zvksed, Zvksh, Zvbb, Zvbc, and Zvkt.", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.experimental_zvksc)] = .{ + .llvm_name = "experimental-zvksc", + .description = "This extension is shorthand for the following set of other extensions: Zvks and Zvbc.", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.experimental_zvksed)] = .{ + .llvm_name = "experimental-zvksed", + .description = "'Zvksed' (SM4 Block Cipher Instructions)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.experimental_zvksg)] = .{ + .llvm_name = "experimental-zvksg", + .description = "This extension is shorthand for the following set of other extensions: Zvks and Zvkg.", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.experimental_zvksh)] = .{ + .llvm_name = "experimental-zvksh", + .description = "'Zvksh' (SM3 Hash Function Instructions)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.experimental_zvkt)] = .{ + .llvm_name = "experimental-zvkt", + .description = "'Zvkt' (Vector Data-Independent Execution Latency)", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.f)] = .{ .llvm_name = "f", .description = "'F' (Single-Precision Floating-Point)", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .zicsr, + }), }; result[@intFromEnum(Feature.forced_atomics)] = .{ .llvm_name = "forced-atomics", @@ -398,6 +551,11 @@ pub const all_features = blk: { .description = "Enable save/restore.", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.seq_cst_trailing_fence)] = .{ + .llvm_name = "seq-cst-trailing-fence", + .description = "Enable trailing fence for seq-cst store.", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.short_forward_branch_opt)] = .{ .llvm_name = "short-forward-branch-opt", .description = "Enable short forward branch optimization", @@ -428,15 +586,93 @@ pub const all_features = blk: { .description = "Has reasonably performant unaligned scalar loads and stores", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.unaligned_vector_mem)] = .{ + .llvm_name = "unaligned-vector-mem", + .description = "Has reasonably performant unaligned vector loads and stores", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.v)] = .{ .llvm_name = "v", .description = "'V' (Vector Extension for Application Processors)", .dependencies = featureSet(&[_]Feature{ - .d, .zve64d, .zvl128b, }), }; + result[@intFromEnum(Feature.xcvbitmanip)] = .{ + .llvm_name = "xcvbitmanip", + .description = "'XCVbitmanip' (CORE-V Bit Manipulation)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.xcvmac)] = .{ + .llvm_name = "xcvmac", + .description = "'XCVmac' (CORE-V Multiply-Accumulate)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.xsfcie)] = .{ + .llvm_name = "xsfcie", + .description = "'XSfcie' (SiFive Custom Instruction Extension SCIE.)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.xsfvcp)] = .{ + .llvm_name = "xsfvcp", + .description = "'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions)", + .dependencies = featureSet(&[_]Feature{ + .zve32x, + }), + }; + result[@intFromEnum(Feature.xtheadba)] = .{ + .llvm_name = "xtheadba", + .description = "'xtheadba' (T-Head address calculation instructions)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.xtheadbb)] = .{ + .llvm_name = "xtheadbb", + .description = "'xtheadbb' (T-Head basic bit-manipulation instructions)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.xtheadbs)] = .{ + .llvm_name = "xtheadbs", + .description = "'xtheadbs' (T-Head single-bit instructions)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.xtheadcmo)] = .{ + .llvm_name = "xtheadcmo", + .description = "'xtheadcmo' (T-Head cache management instructions)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.xtheadcondmov)] = .{ + .llvm_name = "xtheadcondmov", + .description = "'xtheadcondmov' (T-Head conditional move instructions)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.xtheadfmemidx)] = .{ + .llvm_name = "xtheadfmemidx", + .description = "'xtheadfmemidx' (T-Head FP Indexed Memory Operations)", + .dependencies = featureSet(&[_]Feature{ + .f, + }), + }; + result[@intFromEnum(Feature.xtheadmac)] = .{ + .llvm_name = "xtheadmac", + .description = "'xtheadmac' (T-Head Multiply-Accumulate Instructions)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.xtheadmemidx)] = .{ + .llvm_name = "xtheadmemidx", + .description = "'xtheadmemidx' (T-Head Indexed Memory Operations)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.xtheadmempair)] = .{ + .llvm_name = "xtheadmempair", + .description = "'xtheadmempair' (T-Head two-GPR Memory Operations)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.xtheadsync)] = .{ + .llvm_name = "xtheadsync", + .description = "'xtheadsync' (T-Head multicore synchronization instructions)", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.xtheadvdot)] = .{ .llvm_name = "xtheadvdot", .description = "'xtheadvdot' (T-Head Vector Extensions for Dot)", @@ -449,6 +685,11 @@ pub const all_features = blk: { .description = "'XVentanaCondOps' (Ventana Conditional Ops)", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.zawrs)] = .{ + .llvm_name = "zawrs", + .description = "'Zawrs' (Wait on Reservation Set)", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.zba)] = .{ .llvm_name = "zba", .description = "'Zba' (Address Generation Instructions)", @@ -484,6 +725,56 @@ pub const all_features = blk: { .description = "'Zbs' (Single-Bit Instructions)", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.zca)] = .{ + .llvm_name = "zca", + .description = "'Zca' (part of the C extension, excluding compressed floating point loads/stores)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.zcb)] = .{ + .llvm_name = "zcb", + .description = "'Zcb' (Compressed basic bit manipulation instructions)", + .dependencies = featureSet(&[_]Feature{ + .zca, + }), + }; + result[@intFromEnum(Feature.zcd)] = .{ + .llvm_name = "zcd", + .description = "'Zcd' (Compressed Double-Precision Floating-Point Instructions)", + .dependencies = featureSet(&[_]Feature{ + .zca, + }), + }; + result[@intFromEnum(Feature.zce)] = .{ + .llvm_name = "zce", + .description = "'Zce' (Compressed extensions for microcontrollers)", + .dependencies = featureSet(&[_]Feature{ + .zcb, + .zcmp, + .zcmt, + }), + }; + result[@intFromEnum(Feature.zcf)] = .{ + .llvm_name = "zcf", + .description = "'Zcf' (Compressed Single-Precision Floating-Point Instructions)", + .dependencies = featureSet(&[_]Feature{ + .zca, + }), + }; + result[@intFromEnum(Feature.zcmp)] = .{ + .llvm_name = "zcmp", + .description = "'Zcmp' (sequenced instuctions for code-size reduction)", + .dependencies = featureSet(&[_]Feature{ + .zca, + }), + }; + result[@intFromEnum(Feature.zcmt)] = .{ + .llvm_name = "zcmt", + .description = "'Zcmt' (table jump instuctions for code-size reduction)", + .dependencies = featureSet(&[_]Feature{ + .zca, + .zicsr, + }), + }; result[@intFromEnum(Feature.zdinx)] = .{ .llvm_name = "zdinx", .description = "'Zdinx' (Double in Integer)", @@ -508,7 +799,9 @@ pub const all_features = blk: { result[@intFromEnum(Feature.zfinx)] = .{ .llvm_name = "zfinx", .description = "'Zfinx' (Float in Integer)", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .zicsr, + }), }; result[@intFromEnum(Feature.zhinx)] = .{ .llvm_name = "zhinx", @@ -539,11 +832,35 @@ pub const all_features = blk: { .description = "'Zicboz' (Cache-Block Zero Instructions)", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.zicntr)] = .{ + .llvm_name = "zicntr", + .description = "'Zicntr' (Base Counters and Timers)", + .dependencies = featureSet(&[_]Feature{ + .zicsr, + }), + }; + result[@intFromEnum(Feature.zicsr)] = .{ + .llvm_name = "zicsr", + .description = "'zicsr' (CSRs)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.zifencei)] = .{ + .llvm_name = "zifencei", + .description = "'Zifencei' (fence.i)", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.zihintpause)] = .{ .llvm_name = "zihintpause", - .description = "'zihintpause' (Pause Hint)", + .description = "'Zihintpause' (Pause Hint)", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.zihpm)] = .{ + .llvm_name = "zihpm", + .description = "'Zihpm' (Hardware Performance Counters)", + .dependencies = featureSet(&[_]Feature{ + .zicsr, + }), + }; result[@intFromEnum(Feature.zk)] = .{ .llvm_name = "zk", .description = "'Zk' (Standard scalar cryptography extension)", @@ -620,6 +937,7 @@ pub const all_features = blk: { .llvm_name = "zve32f", .description = "'Zve32f' (Vector Extensions for Embedded Processors with maximal 32 EEW and F extension)", .dependencies = featureSet(&[_]Feature{ + .f, .zve32x, }), }; @@ -627,6 +945,7 @@ pub const all_features = blk: { .llvm_name = "zve32x", .description = "'Zve32x' (Vector Extensions for Embedded Processors with maximal 32 EEW)", .dependencies = featureSet(&[_]Feature{ + .zicsr, .zvl32b, }), }; @@ -634,6 +953,7 @@ pub const all_features = blk: { .llvm_name = "zve64d", .description = "'Zve64d' (Vector Extensions for Embedded Processors with maximal 64 EEW, F and D extension)", .dependencies = featureSet(&[_]Feature{ + .d, .zve64f, }), }; @@ -653,6 +973,14 @@ pub const all_features = blk: { .zvl64b, }), }; + result[@intFromEnum(Feature.zvfh)] = .{ + .llvm_name = "zvfh", + .description = "'Zvfh' (Vector Half-Precision Floating-Point)", + .dependencies = featureSet(&[_]Feature{ + .zfhmin, + .zve32f, + }), + }; result[@intFromEnum(Feature.zvl1024b)] = .{ .llvm_name = "zvl1024b", .description = "'Zvl' (Minimum Vector Length) 1024", @@ -795,6 +1123,8 @@ pub const cpu = struct { .llvm_name = "rocket-rv32", .features = featureSet(&[_]Feature{ .@"32bit", + .zicsr, + .zifencei, }), }; pub const rocket_rv64 = CpuModel{ @@ -802,6 +1132,8 @@ pub const cpu = struct { .llvm_name = "rocket-rv64", .features = featureSet(&[_]Feature{ .@"64bit", + .zicsr, + .zifencei, }), }; pub const sifive_7_series = CpuModel{ @@ -819,6 +1151,8 @@ pub const cpu = struct { .@"32bit", .c, .m, + .zicsr, + .zifencei, }), }; pub const sifive_e21 = CpuModel{ @@ -829,6 +1163,8 @@ pub const cpu = struct { .a, .c, .m, + .zicsr, + .zifencei, }), }; pub const sifive_e24 = CpuModel{ @@ -840,6 +1176,7 @@ pub const cpu = struct { .c, .f, .m, + .zifencei, }), }; pub const sifive_e31 = CpuModel{ @@ -850,6 +1187,8 @@ pub const cpu = struct { .a, .c, .m, + .zicsr, + .zifencei, }), }; pub const sifive_e34 = CpuModel{ @@ -861,6 +1200,7 @@ pub const cpu = struct { .c, .f, .m, + .zifencei, }), }; pub const sifive_e76 = CpuModel{ @@ -874,6 +1214,7 @@ pub const cpu = struct { .m, .no_default_unroll, .short_forward_branch_opt, + .zifencei, }), }; pub const sifive_s21 = CpuModel{ @@ -884,6 +1225,8 @@ pub const cpu = struct { .a, .c, .m, + .zicsr, + .zifencei, }), }; pub const sifive_s51 = CpuModel{ @@ -894,6 +1237,8 @@ pub const cpu = struct { .a, .c, .m, + .zicsr, + .zifencei, }), }; pub const sifive_s54 = CpuModel{ @@ -905,6 +1250,7 @@ pub const cpu = struct { .c, .d, .m, + .zifencei, }), }; pub const sifive_s76 = CpuModel{ @@ -918,6 +1264,9 @@ pub const cpu = struct { .m, .no_default_unroll, .short_forward_branch_opt, + .xsfcie, + .zifencei, + .zihintpause, }), }; pub const sifive_u54 = CpuModel{ @@ -929,6 +1278,7 @@ pub const cpu = struct { .c, .d, .m, + .zifencei, }), }; pub const sifive_u74 = CpuModel{ @@ -942,6 +1292,27 @@ pub const cpu = struct { .m, .no_default_unroll, .short_forward_branch_opt, + .zifencei, + }), + }; + pub const sifive_x280 = CpuModel{ + .name = "sifive_x280", + .llvm_name = "sifive-x280", + .features = featureSet(&[_]Feature{ + .@"64bit", + .a, + .c, + .dlen_factor_2, + .m, + .no_default_unroll, + .short_forward_branch_opt, + .v, + .zba, + .zbb, + .zfh, + .zifencei, + .zvfh, + .zvl512b, }), }; pub const syntacore_scr1_base = CpuModel{ @@ -951,6 +1322,8 @@ pub const cpu = struct { .@"32bit", .c, .no_default_unroll, + .zicsr, + .zifencei, }), }; pub const syntacore_scr1_max = CpuModel{ @@ -961,6 +1334,8 @@ pub const cpu = struct { .c, .m, .no_default_unroll, + .zicsr, + .zifencei, }), }; }; diff --git a/lib/std/target/x86.zig b/lib/std/target/x86.zig index 645d5f688dc55f6d11e501e8e9376b251ded71bf..34334acf867e429360ec69e59159fe1981b0b8a7 100644 --- a/lib/std/target/x86.zig +++ b/lib/std/target/x86.zig @@ -14,6 +14,7 @@ pub const Feature = enum { aes, allow_light_256_bit, amx_bf16, + amx_complex, amx_fp16, amx_int8, amx_tile, @@ -38,6 +39,7 @@ pub const Feature = enum { avxifma, avxneconvert, avxvnni, + avxvnniint16, avxvnniint8, bmi, bmi2, @@ -76,6 +78,7 @@ pub const Feature = enum { fast_variable_perlane_shuffle, fast_vector_fsqrt, fast_vector_shift_masks, + faster_shift_than_shuffle, fma, fma4, fsgsbase, @@ -101,6 +104,10 @@ pub const Feature = enum { movdir64b, movdiri, mwaitx, + no_bypass_delay, + no_bypass_delay_blend, + no_bypass_delay_mov, + no_bypass_delay_shuffle, nopl, pad_short_functions, pclmul, @@ -110,6 +117,7 @@ pub const Feature = enum { prefer_128_bit, prefer_256_bit, prefer_mask_registers, + prefer_movmsk_over_vtest, prefetchi, prefetchwt1, prfchw, @@ -130,6 +138,7 @@ pub const Feature = enum { seses, sgx, sha, + sha512, shstk, slow_3ops_lea, slow_incdec, @@ -140,6 +149,8 @@ pub const Feature = enum { slow_two_mem_ops, slow_unaligned_mem_16, slow_unaligned_mem_32, + sm3, + sm4, soft_float, sse, sse2, @@ -152,6 +163,7 @@ pub const Feature = enum { tagged_globals, tbm, tsxldtrk, + tuning_fast_imm_vector_shift, uintr, use_glm_div_sqrt_costs, use_slm_arith_costs, @@ -231,6 +243,13 @@ pub const all_features = blk: { .amx_tile, }), }; + result[@intFromEnum(Feature.amx_complex)] = .{ + .llvm_name = "amx-complex", + .description = "Support AMX-COMPLEX instructions", + .dependencies = featureSet(&[_]Feature{ + .amx_tile, + }), + }; result[@intFromEnum(Feature.amx_fp16)] = .{ .llvm_name = "amx-fp16", .description = "Support AMX amx-fp16 instructions", @@ -326,7 +345,7 @@ pub const all_features = blk: { }; result[@intFromEnum(Feature.avx512ifma)] = .{ .llvm_name = "avx512ifma", - .description = "Enable AVX-512 Integer Fused Multiply-Add", + .description = "Enable AVX-512 Integer Fused Multiple-Add", .dependencies = featureSet(&[_]Feature{ .avx512f, }), @@ -401,6 +420,13 @@ pub const all_features = blk: { .avx2, }), }; + result[@intFromEnum(Feature.avxvnniint16)] = .{ + .llvm_name = "avxvnniint16", + .description = "Enable AVX-VNNI-INT16", + .dependencies = featureSet(&[_]Feature{ + .avx2, + }), + }; result[@intFromEnum(Feature.avxvnniint8)] = .{ .llvm_name = "avxvnniint8", .description = "Enable AVX-VNNI-INT8", @@ -597,16 +623,21 @@ pub const all_features = blk: { .description = "Prefer a left/right vector logical shift pair over a shift+and pair", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.faster_shift_than_shuffle)] = .{ + .llvm_name = "faster-shift-than-shuffle", + .description = "Shifts are faster (or as fast) as shuffle", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.fma)] = .{ .llvm_name = "fma", - .description = "Enable three-operand fused multiply-add", + .description = "Enable three-operand fused multiple-add", .dependencies = featureSet(&[_]Feature{ .avx, }), }; result[@intFromEnum(Feature.fma4)] = .{ .llvm_name = "fma4", - .description = "Enable four-operand fused multiply-add", + .description = "Enable four-operand fused multiple-add", .dependencies = featureSet(&[_]Feature{ .avx, .sse4a, @@ -731,6 +762,26 @@ pub const all_features = blk: { .description = "Enable MONITORX/MWAITX timer functionality", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.no_bypass_delay)] = .{ + .llvm_name = "no-bypass-delay", + .description = "Has no bypass delay when using the 'wrong' domain", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.no_bypass_delay_blend)] = .{ + .llvm_name = "no-bypass-delay-blend", + .description = "Has no bypass delay when using the 'wrong' blend type", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.no_bypass_delay_mov)] = .{ + .llvm_name = "no-bypass-delay-mov", + .description = "Has no bypass delay when using the 'wrong' mov type", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@intFromEnum(Feature.no_bypass_delay_shuffle)] = .{ + .llvm_name = "no-bypass-delay-shuffle", + .description = "Has no bypass delay when using the 'wrong' shuffle type", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.nopl)] = .{ .llvm_name = "nopl", .description = "Enable NOPL instruction (generally pentium pro+)", @@ -778,6 +829,11 @@ pub const all_features = blk: { .description = "Prefer AVX512 mask registers over PTEST/MOVMSK", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.prefer_movmsk_over_vtest)] = .{ + .llvm_name = "prefer-movmsk-over-vtest", + .description = "Prefer movmsk over vtest instruction", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.prefetchi)] = .{ .llvm_name = "prefetchi", .description = "Prefetch instruction with T0 or T1 Hint", @@ -887,6 +943,13 @@ pub const all_features = blk: { .sse2, }), }; + result[@intFromEnum(Feature.sha512)] = .{ + .llvm_name = "sha512", + .description = "Support SHA512 instructions", + .dependencies = featureSet(&[_]Feature{ + .avx, + }), + }; result[@intFromEnum(Feature.shstk)] = .{ .llvm_name = "shstk", .description = "Support CET Shadow-Stack instructions", @@ -937,6 +1000,20 @@ pub const all_features = blk: { .description = "Slow unaligned 32-byte memory access", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.sm3)] = .{ + .llvm_name = "sm3", + .description = "Support SM3 instructions", + .dependencies = featureSet(&[_]Feature{ + .avx, + }), + }; + result[@intFromEnum(Feature.sm4)] = .{ + .llvm_name = "sm4", + .description = "Support SM4 instructions", + .dependencies = featureSet(&[_]Feature{ + .avx, + }), + }; result[@intFromEnum(Feature.soft_float)] = .{ .llvm_name = "soft-float", .description = "Use software floating point features", @@ -1009,6 +1086,11 @@ pub const all_features = blk: { .description = "Support TSXLDTRK instructions", .dependencies = featureSet(&[_]Feature{}), }; + result[@intFromEnum(Feature.tuning_fast_imm_vector_shift)] = .{ + .llvm_name = "tuning-fast-imm-vector-shift", + .description = "Vector shifts are fast (2/cycle) as opposed to slow (1/cycle)", + .dependencies = featureSet(&[_]Feature{}), + }; result[@intFromEnum(Feature.uintr)] = .{ .llvm_name = "uintr", .description = "Has UINTR Instructions", @@ -1148,10 +1230,14 @@ pub const cpu = struct { .movbe, .movdir64b, .movdiri, + .no_bypass_delay_blend, + .no_bypass_delay_mov, + .no_bypass_delay_shuffle, .nopl, .pconfig, .pku, .popcnt, + .prefer_movmsk_over_vtest, .prfchw, .ptwrite, .rdpid, @@ -1162,6 +1248,7 @@ pub const cpu = struct { .sha, .shstk, .slow_3ops_lea, + .tuning_fast_imm_vector_shift, .vaes, .vpclmulqdq, .vzeroupper, @@ -1342,6 +1429,7 @@ pub const cpu = struct { .lea_uses_ag, .mmx, .movbe, + .no_bypass_delay, .nopl, .pad_short_functions, .sahf, @@ -1352,6 +1440,46 @@ pub const cpu = struct { .x87, }), }; + pub const atom_sse4_2_movbe = CpuModel{ + .name = "atom_sse4_2_movbe", + .llvm_name = "atom_sse4_2_movbe", + .features = featureSet(&[_]Feature{ + .@"64bit", + .aes, + .clflushopt, + .cmov, + .crc32, + .cx16, + .false_deps_popcnt, + .fast_7bytenop, + .fast_movbe, + .fsgsbase, + .fxsr, + .idivq_to_divl, + .mmx, + .movbe, + .no_bypass_delay, + .nopl, + .pclmul, + .popcnt, + .prfchw, + .rdrnd, + .rdseed, + .sahf, + .sha, + .slow_incdec, + .slow_lea, + .slow_pmulld, + .slow_two_mem_ops, + .sse4_2, + .use_slm_arith_costs, + .vzeroupper, + .x87, + .xsavec, + .xsaveopt, + .xsaves, + }), + }; pub const barcelona = CpuModel{ .name = "barcelona", .llvm_name = "barcelona", @@ -1529,6 +1657,7 @@ pub const cpu = struct { .lea_uses_ag, .mmx, .movbe, + .no_bypass_delay, .nopl, .pad_short_functions, .sahf, @@ -1570,6 +1699,8 @@ pub const cpu = struct { .macrofusion, .mmx, .movbe, + .no_bypass_delay_mov, + .no_bypass_delay_shuffle, .nopl, .pclmul, .popcnt, @@ -1701,6 +1832,9 @@ pub const cpu = struct { .macrofusion, .mmx, .movbe, + .no_bypass_delay_blend, + .no_bypass_delay_mov, + .no_bypass_delay_shuffle, .nopl, .pclmul, .pku, @@ -1712,6 +1846,7 @@ pub const cpu = struct { .sahf, .sha, .slow_3ops_lea, + .tuning_fast_imm_vector_shift, .vzeroupper, .x87, .xsavec, @@ -1748,6 +1883,7 @@ pub const cpu = struct { .fast_variable_crosslane_shuffle, .fast_variable_perlane_shuffle, .fast_vector_fsqrt, + .faster_shift_than_shuffle, .fsgsbase, .fxsr, .idivq_to_divl, @@ -1756,6 +1892,9 @@ pub const cpu = struct { .macrofusion, .mmx, .movbe, + .no_bypass_delay_blend, + .no_bypass_delay_mov, + .no_bypass_delay_shuffle, .nopl, .pclmul, .pku, @@ -1766,6 +1905,7 @@ pub const cpu = struct { .rdseed, .sahf, .slow_3ops_lea, + .tuning_fast_imm_vector_shift, .vzeroupper, .x87, .xsavec, @@ -1802,6 +1942,7 @@ pub const cpu = struct { .fast_variable_crosslane_shuffle, .fast_variable_perlane_shuffle, .fast_vector_fsqrt, + .faster_shift_than_shuffle, .fsgsbase, .fxsr, .idivq_to_divl, @@ -1810,6 +1951,9 @@ pub const cpu = struct { .macrofusion, .mmx, .movbe, + .no_bypass_delay_blend, + .no_bypass_delay_mov, + .no_bypass_delay_shuffle, .nopl, .pclmul, .pku, @@ -1820,6 +1964,7 @@ pub const cpu = struct { .rdseed, .sahf, .slow_3ops_lea, + .tuning_fast_imm_vector_shift, .vzeroupper, .x87, .xsavec, @@ -1845,77 +1990,6 @@ pub const cpu = struct { .x87, }), }; - pub const core_avx2 = CpuModel{ - .name = "core_avx2", - .llvm_name = "core-avx2", - .features = featureSet(&[_]Feature{ - .@"64bit", - .allow_light_256_bit, - .avx2, - .bmi, - .bmi2, - .cmov, - .crc32, - .cx16, - .ermsb, - .f16c, - .false_deps_lzcnt_tzcnt, - .false_deps_popcnt, - .fast_15bytenop, - .fast_scalar_fsqrt, - .fast_shld_rotate, - .fast_variable_crosslane_shuffle, - .fast_variable_perlane_shuffle, - .fma, - .fsgsbase, - .fxsr, - .idivq_to_divl, - .invpcid, - .lzcnt, - .macrofusion, - .mmx, - .movbe, - .nopl, - .pclmul, - .popcnt, - .rdrnd, - .sahf, - .slow_3ops_lea, - .vzeroupper, - .x87, - .xsaveopt, - }), - }; - pub const core_avx_i = CpuModel{ - .name = "core_avx_i", - .llvm_name = "core-avx-i", - .features = featureSet(&[_]Feature{ - .@"64bit", - .cmov, - .crc32, - .cx16, - .f16c, - .false_deps_popcnt, - .fast_15bytenop, - .fast_scalar_fsqrt, - .fast_shld_rotate, - .fsgsbase, - .fxsr, - .idivq_to_divl, - .macrofusion, - .mmx, - .nopl, - .pclmul, - .popcnt, - .rdrnd, - .sahf, - .slow_3ops_lea, - .slow_unaligned_mem_32, - .vzeroupper, - .x87, - .xsaveopt, - }), - }; pub const corei7 = CpuModel{ .name = "corei7", .llvm_name = "corei7", @@ -1927,6 +2001,7 @@ pub const cpu = struct { .fxsr, .macrofusion, .mmx, + .no_bypass_delay_mov, .nopl, .popcnt, .sahf, @@ -1935,34 +2010,6 @@ pub const cpu = struct { .x87, }), }; - pub const corei7_avx = CpuModel{ - .name = "corei7_avx", - .llvm_name = "corei7-avx", - .features = featureSet(&[_]Feature{ - .@"64bit", - .avx, - .cmov, - .crc32, - .cx16, - .false_deps_popcnt, - .fast_15bytenop, - .fast_scalar_fsqrt, - .fast_shld_rotate, - .fxsr, - .idivq_to_divl, - .macrofusion, - .mmx, - .nopl, - .pclmul, - .popcnt, - .sahf, - .slow_3ops_lea, - .slow_unaligned_mem_32, - .vzeroupper, - .x87, - .xsaveopt, - }), - }; pub const emeraldrapids = CpuModel{ .name = "emeraldrapids", .llvm_name = "emeraldrapids", @@ -2016,6 +2063,9 @@ pub const cpu = struct { .movbe, .movdir64b, .movdiri, + .no_bypass_delay_blend, + .no_bypass_delay_mov, + .no_bypass_delay_shuffle, .nopl, .pconfig, .pku, @@ -2031,6 +2081,7 @@ pub const cpu = struct { .sha, .shstk, .tsxldtrk, + .tuning_fast_imm_vector_shift, .uintr, .vaes, .vpclmulqdq, @@ -2085,6 +2136,7 @@ pub const cpu = struct { .fxsr, .mmx, .movbe, + .no_bypass_delay, .nopl, .pclmul, .popcnt, @@ -2120,6 +2172,7 @@ pub const cpu = struct { .fxsr, .mmx, .movbe, + .no_bypass_delay, .nopl, .pclmul, .popcnt, @@ -2161,6 +2214,7 @@ pub const cpu = struct { .cmpccxadd, .crc32, .cx16, + .enqcmd, .f16c, .fast_movbe, .fma, @@ -2174,6 +2228,7 @@ pub const cpu = struct { .movbe, .movdir64b, .movdiri, + .no_bypass_delay, .nopl, .pconfig, .pku, @@ -2191,6 +2246,7 @@ pub const cpu = struct { .slow_incdec, .slow_lea, .slow_two_mem_ops, + .uintr, .use_glm_div_sqrt_costs, .vaes, .vpclmulqdq, @@ -2257,6 +2313,9 @@ pub const cpu = struct { .movbe, .movdir64b, .movdiri, + .no_bypass_delay_blend, + .no_bypass_delay_mov, + .no_bypass_delay_shuffle, .nopl, .pconfig, .pku, @@ -2273,6 +2332,94 @@ pub const cpu = struct { .sha, .shstk, .tsxldtrk, + .tuning_fast_imm_vector_shift, + .uintr, + .vaes, + .vpclmulqdq, + .vzeroupper, + .waitpkg, + .wbnoinvd, + .x87, + .xsavec, + .xsaveopt, + .xsaves, + }), + }; + pub const graniterapids_d = CpuModel{ + .name = "graniterapids_d", + .llvm_name = "graniterapids-d", + .features = featureSet(&[_]Feature{ + .@"64bit", + .adx, + .allow_light_256_bit, + .amx_bf16, + .amx_complex, + .amx_fp16, + .amx_int8, + .avx512bf16, + .avx512bitalg, + .avx512cd, + .avx512fp16, + .avx512ifma, + .avx512vbmi, + .avx512vbmi2, + .avx512vnni, + .avx512vpopcntdq, + .avxvnni, + .bmi, + .bmi2, + .cldemote, + .clflushopt, + .clwb, + .cmov, + .crc32, + .cx16, + .enqcmd, + .ermsb, + .false_deps_getmant, + .false_deps_mulc, + .false_deps_mullq, + .false_deps_perm, + .false_deps_range, + .fast_15bytenop, + .fast_gather, + .fast_scalar_fsqrt, + .fast_shld_rotate, + .fast_variable_crosslane_shuffle, + .fast_variable_perlane_shuffle, + .fast_vector_fsqrt, + .fsgsbase, + .fsrm, + .fxsr, + .gfni, + .idivq_to_divl, + .invpcid, + .lzcnt, + .macrofusion, + .mmx, + .movbe, + .movdir64b, + .movdiri, + .no_bypass_delay_blend, + .no_bypass_delay_mov, + .no_bypass_delay_shuffle, + .nopl, + .pconfig, + .pku, + .popcnt, + .prefer_256_bit, + .prefetchi, + .prfchw, + .ptwrite, + .rdpid, + .rdrnd, + .rdseed, + .sahf, + .serialize, + .sha, + .shstk, + .tsxldtrk, + .tuning_fast_imm_vector_shift, .uintr, .vaes, .vpclmulqdq, @@ -2315,6 +2462,8 @@ pub const cpu = struct { .macrofusion, .mmx, .movbe, + .no_bypass_delay_mov, + .no_bypass_delay_shuffle, .nopl, .pclmul, .popcnt, @@ -2405,6 +2554,9 @@ pub const cpu = struct { .macrofusion, .mmx, .movbe, + .no_bypass_delay_blend, + .no_bypass_delay_mov, + .no_bypass_delay_shuffle, .nopl, .pku, .popcnt, @@ -2415,6 +2567,7 @@ pub const cpu = struct { .rdseed, .sahf, .sha, + .tuning_fast_imm_vector_shift, .vaes, .vpclmulqdq, .vzeroupper, @@ -2465,6 +2618,9 @@ pub const cpu = struct { .macrofusion, .mmx, .movbe, + .no_bypass_delay_blend, + .no_bypass_delay_mov, + .no_bypass_delay_shuffle, .nopl, .pconfig, .pku, @@ -2476,6 +2632,7 @@ pub const cpu = struct { .rdseed, .sahf, .sha, + .tuning_fast_imm_vector_shift, .vaes, .vpclmulqdq, .vzeroupper, @@ -2504,6 +2661,7 @@ pub const cpu = struct { .idivq_to_divl, .macrofusion, .mmx, + .no_bypass_delay_mov, .nopl, .pclmul, .popcnt, @@ -2717,10 +2875,14 @@ pub const cpu = struct { .movbe, .movdir64b, .movdiri, + .no_bypass_delay_blend, + .no_bypass_delay_mov, + .no_bypass_delay_shuffle, .nopl, .pconfig, .pku, .popcnt, + .prefer_movmsk_over_vtest, .prfchw, .ptwrite, .rdpid, @@ -2731,6 +2893,7 @@ pub const cpu = struct { .sha, .shstk, .slow_3ops_lea, + .tuning_fast_imm_vector_shift, .vaes, .vpclmulqdq, .vzeroupper, @@ -2753,6 +2916,7 @@ pub const cpu = struct { .fxsr, .macrofusion, .mmx, + .no_bypass_delay_mov, .nopl, .popcnt, .sahf, @@ -2902,21 +3066,6 @@ pub const cpu = struct { .x87, }), }; - pub const pentium4m = CpuModel{ - .name = "pentium4m", - .llvm_name = "pentium4m", - .features = featureSet(&[_]Feature{ - .cmov, - .cx8, - .fxsr, - .mmx, - .nopl, - .slow_unaligned_mem_16, - .sse2, - .vzeroupper, - .x87, - }), - }; pub const pentium_m = CpuModel{ .name = "pentium_m", .llvm_name = "pentium-m", @@ -3009,10 +3158,14 @@ pub const cpu = struct { .movbe, .movdir64b, .movdiri, + .no_bypass_delay_blend, + .no_bypass_delay_mov, + .no_bypass_delay_shuffle, .nopl, .pconfig, .pku, .popcnt, + .prefer_movmsk_over_vtest, .prfchw, .ptwrite, .rdpid, @@ -3023,6 +3176,7 @@ pub const cpu = struct { .sha, .shstk, .slow_3ops_lea, + .tuning_fast_imm_vector_shift, .vaes, .vpclmulqdq, .vzeroupper, @@ -3074,6 +3228,9 @@ pub const cpu = struct { .macrofusion, .mmx, .movbe, + .no_bypass_delay_blend, + .no_bypass_delay_mov, + .no_bypass_delay_shuffle, .nopl, .pku, .popcnt, @@ -3084,6 +3241,7 @@ pub const cpu = struct { .rdseed, .sahf, .sha, + .tuning_fast_imm_vector_shift, .vaes, .vpclmulqdq, .vzeroupper, @@ -3110,6 +3268,7 @@ pub const cpu = struct { .idivq_to_divl, .macrofusion, .mmx, + .no_bypass_delay_mov, .nopl, .pclmul, .popcnt, @@ -3174,6 +3333,9 @@ pub const cpu = struct { .movbe, .movdir64b, .movdiri, + .no_bypass_delay_blend, + .no_bypass_delay_mov, + .no_bypass_delay_shuffle, .nopl, .pconfig, .pku, @@ -3189,6 +3351,7 @@ pub const cpu = struct { .sha, .shstk, .tsxldtrk, + .tuning_fast_imm_vector_shift, .uintr, .vaes, .vpclmulqdq, @@ -3220,6 +3383,7 @@ pub const cpu = struct { .cmpccxadd, .crc32, .cx16, + .enqcmd, .f16c, .fast_movbe, .fma, @@ -3233,6 +3397,7 @@ pub const cpu = struct { .movbe, .movdir64b, .movdiri, + .no_bypass_delay, .nopl, .pconfig, .pku, @@ -3249,6 +3414,7 @@ pub const cpu = struct { .slow_incdec, .slow_lea, .slow_two_mem_ops, + .uintr, .use_glm_div_sqrt_costs, .vaes, .vpclmulqdq, @@ -3276,6 +3442,7 @@ pub const cpu = struct { .idivq_to_divl, .mmx, .movbe, + .no_bypass_delay, .nopl, .pclmul, .popcnt, @@ -3320,6 +3487,7 @@ pub const cpu = struct { .fast_variable_crosslane_shuffle, .fast_variable_perlane_shuffle, .fast_vector_fsqrt, + .faster_shift_than_shuffle, .fsgsbase, .fxsr, .idivq_to_divl, @@ -3328,6 +3496,9 @@ pub const cpu = struct { .macrofusion, .mmx, .movbe, + .no_bypass_delay_blend, + .no_bypass_delay_mov, + .no_bypass_delay_shuffle, .nopl, .pclmul, .pku, @@ -3338,6 +3509,7 @@ pub const cpu = struct { .rdseed, .sahf, .slow_3ops_lea, + .tuning_fast_imm_vector_shift, .vzeroupper, .x87, .xsavec, @@ -3379,6 +3551,9 @@ pub const cpu = struct { .macrofusion, .mmx, .movbe, + .no_bypass_delay_blend, + .no_bypass_delay_mov, + .no_bypass_delay_shuffle, .nopl, .pclmul, .popcnt, @@ -3394,59 +3569,6 @@ pub const cpu = struct { .xsaves, }), }; - pub const skylake_avx512 = CpuModel{ - .name = "skylake_avx512", - .llvm_name = "skylake-avx512", - .features = featureSet(&[_]Feature{ - .@"64bit", - .adx, - .aes, - .allow_light_256_bit, - .avx512bw, - .avx512cd, - .avx512dq, - .avx512vl, - .bmi, - .bmi2, - .clflushopt, - .clwb, - .cmov, - .crc32, - .cx16, - .ermsb, - .false_deps_popcnt, - .fast_15bytenop, - .fast_gather, - .fast_scalar_fsqrt, - .fast_shld_rotate, - .fast_variable_crosslane_shuffle, - .fast_variable_perlane_shuffle, - .fast_vector_fsqrt, - .fsgsbase, - .fxsr, - .idivq_to_divl, - .invpcid, - .lzcnt, - .macrofusion, - .mmx, - .movbe, - .nopl, - .pclmul, - .pku, - .popcnt, - .prefer_256_bit, - .prfchw, - .rdrnd, - .rdseed, - .sahf, - .slow_3ops_lea, - .vzeroupper, - .x87, - .xsavec, - .xsaveopt, - .xsaves, - }), - }; pub const slm = CpuModel{ .name = "slm", .llvm_name = "slm", @@ -3462,6 +3584,7 @@ pub const cpu = struct { .idivq_to_divl, .mmx, .movbe, + .no_bypass_delay, .nopl, .pclmul, .popcnt, @@ -3522,6 +3645,9 @@ pub const cpu = struct { .movbe, .movdir64b, .movdiri, + .no_bypass_delay_blend, + .no_bypass_delay_mov, + .no_bypass_delay_shuffle, .nopl, .pku, .popcnt, @@ -3533,6 +3659,7 @@ pub const cpu = struct { .sahf, .sha, .shstk, + .tuning_fast_imm_vector_shift, .vaes, .vpclmulqdq, .vzeroupper, @@ -3559,6 +3686,7 @@ pub const cpu = struct { .gfni, .mmx, .movbe, + .no_bypass_delay, .nopl, .pclmul, .popcnt, @@ -3592,6 +3720,7 @@ pub const cpu = struct { .fxsr, .macrofusion, .mmx, + .no_bypass_delay_mov, .nopl, .pclmul, .popcnt, diff --git a/tools/update_cpu_features.zig b/tools/update_cpu_features.zig index 0b14769eadb18dd2f0c5f2e44f9efc50a5ab2413..805fe1774714b670624030dbce2fec96ae3e5dfc 100644 --- a/tools/update_cpu_features.zig +++ b/tools/update_cpu_features.zig @@ -40,6 +40,7 @@ const LlvmTarget = struct { feature_overrides: []const FeatureOverride = &.{}, extra_cpus: []const Cpu = &.{}, extra_features: []const Feature = &.{}, + omit_cpus: []const []const u8 = &.{}, branch_quota: ?usize = null, }; @@ -915,6 +916,40 @@ const llvm_targets = [_]LlvmTarget{ .extra_deps = &.{"soft_float"}, }, }, + .omit_cpus = &.{ + // LLVM defines a bunch of dumb aliases with foreach loops in X86.td. + "pentium_mmx", + "pentium_pro", + "pentium_ii", + "pentium_3m", + "pentium_iii_no_xmm_regs", + "pentium_iii", + "pentium_m", + "pentium4m", + "pentium_4", + "pentium_4_sse3", + "core_2_duo_ssse3", + "core_2_duo_sse4_1", + "atom_sse4_2", + "goldmont_plus", + "core_i7_sse4_2", + "core_aes_pclmulqdq", + "corei7-avx", + "core_2nd_gen_avx", + "core-avx-i", + "core_3rd_gen_avx", + "core-avx2", + "core_4th_gen_avx", + "core_4th_gen_avx_tsx", + "core_5th_gen_avx", + "core_5th_gen_avx_tsx", + "mic_avx512", + "skylake_avx512", + "skylake-avx512", + "icelake_client", + "icelake_server", + "graniterapids_d", + }, }, .{ .zig_name = "xcore", @@ -1129,6 +1164,10 @@ fn processOneTarget(job: Job) anyerror!void { if (hasSuperclass(&kv.value_ptr.object, "Processor")) { const llvm_name = kv.value_ptr.object.get("Name").?.string; if (llvm_name.len == 0) continue; + const omitted = for (llvm_target.omit_cpus) |omit_cpu_name| { + if (mem.eql(u8, omit_cpu_name, llvm_name)) break true; + } else false; + if (omitted) continue; var zig_name = try llvmNameToZigName(arena, llvm_name); var deps = std.ArrayList([]const u8).init(arena); -- 2.54.0