authorgravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2021-02-24 21:54:23-07:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2021-02-24 21:54:23-07:00
log449f4de3825d3448c2aa0cda79c1a567adb08b59
treeec2c79770135e854560743c489aa4b5eea7554ac
parent9b8a94265ab7313f07b300ddc349a60c85d556d1

zig fmt src/

9 files changed, 45 insertions(+), 57 deletions(-)

src/Module.zig+4-5
...@@ -1251,11 +1251,10 @@ fn astgenAndSemaFn(...@@ -1251,11 +1251,10 @@ fn astgenAndSemaFn(
1251 .param_types = param_types,1251 .param_types = param_types,
1252 .cc = cc,1252 .cc = cc,
1253 });1253 });
1254 } else1254 } else try astgen.addZirInstTag(mod, &fn_type_scope.base, fn_src, .fn_type, .{
1255 try astgen.addZirInstTag(mod, &fn_type_scope.base, fn_src, .fn_type, .{1255 .return_type = return_type_inst,
1256 .return_type = return_type_inst,1256 .param_types = param_types,
1257 .param_types = param_types,1257 });
1258 });
12591258
1260 if (std.builtin.mode == .Debug and mod.comp.verbose_ir) {1259 if (std.builtin.mode == .Debug and mod.comp.verbose_ir) {
1261 zir.dumpZir(mod.gpa, "fn_type", decl.name, fn_type_scope.instructions.items) catch {};1260 zir.dumpZir(mod.gpa, "fn_type", decl.name, fn_type_scope.instructions.items) catch {};
src/astgen.zig+12-15
...@@ -2143,11 +2143,10 @@ fn ifExpr(...@@ -2143,11 +2143,10 @@ fn ifExpr(
2143 .src = token_starts[tree.lastToken(else_node)],2143 .src = token_starts[tree.lastToken(else_node)],
2144 .result = try expr(mod, sub_scope, block_scope.break_result_loc, else_node),2144 .result = try expr(mod, sub_scope, block_scope.break_result_loc, else_node),
2145 };2145 };
2146 } else2146 } else .{
2147 .{2147 .src = token_starts[tree.lastToken(if_full.ast.then_expr)],
2148 .src = token_starts[tree.lastToken(if_full.ast.then_expr)],2148 .result = null,
2149 .result = null,2149 };
2150 };
21512150
2152 return finishThenElseBlock(2151 return finishThenElseBlock(
2153 mod,2152 mod,
...@@ -2316,11 +2315,10 @@ fn whileExpr(...@@ -2316,11 +2315,10 @@ fn whileExpr(
2316 .src = token_starts[tree.lastToken(else_node)],2315 .src = token_starts[tree.lastToken(else_node)],
2317 .result = try expr(mod, sub_scope, loop_scope.break_result_loc, else_node),2316 .result = try expr(mod, sub_scope, loop_scope.break_result_loc, else_node),
2318 };2317 };
2319 } else2318 } else .{
2320 .{2319 .src = token_starts[tree.lastToken(while_full.ast.then_expr)],
2321 .src = token_starts[tree.lastToken(while_full.ast.then_expr)],2320 .result = null,
2322 .result = null,2321 };
2323 };
23242322
2325 if (loop_scope.label) |some| {2323 if (loop_scope.label) |some| {
2326 if (!some.used) {2324 if (!some.used) {
...@@ -2514,11 +2512,10 @@ fn forExpr(...@@ -2514,11 +2512,10 @@ fn forExpr(
2514 .src = token_starts[tree.lastToken(else_node)],2512 .src = token_starts[tree.lastToken(else_node)],
2515 .result = try expr(mod, sub_scope, loop_scope.break_result_loc, else_node),2513 .result = try expr(mod, sub_scope, loop_scope.break_result_loc, else_node),
2516 };2514 };
2517 } else2515 } else .{
2518 .{2516 .src = token_starts[tree.lastToken(for_full.ast.then_expr)],
2519 .src = token_starts[tree.lastToken(for_full.ast.then_expr)],2517 .result = null,
2520 .result = null,2518 };
2521 };
25222519
2523 if (loop_scope.label) |some| {2520 if (loop_scope.label) |some| {
2524 if (!some.used) {2521 if (!some.used) {
src/codegen.zig+1-2
...@@ -2950,8 +2950,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {...@@ -2950,8 +2950,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
2950 4, 8 => {2950 4, 8 => {
2951 const offset = if (math.cast(i9, adj_off)) |imm|2951 const offset = if (math.cast(i9, adj_off)) |imm|
2952 Instruction.LoadStoreOffset.imm_post_index(-imm)2952 Instruction.LoadStoreOffset.imm_post_index(-imm)
2953 else |_|2953 else |_| Instruction.LoadStoreOffset.reg(try self.copyToTmpRegister(src, Type.initTag(.u64), MCValue{ .immediate = adj_off }));
2954 Instruction.LoadStoreOffset.reg(try self.copyToTmpRegister(src, Type.initTag(.u64), MCValue{ .immediate = adj_off }));
2955 const rn: Register = switch (arch) {2954 const rn: Register = switch (arch) {
2956 .aarch64, .aarch64_be => .x29,2955 .aarch64, .aarch64_be => .x29,
2957 .aarch64_32 => .w29,2956 .aarch64_32 => .w29,
src/codegen/c.zig+1-2
...@@ -626,8 +626,7 @@ fn genBlock(o: *Object, inst: *Inst.Block) !CValue {...@@ -626,8 +626,7 @@ fn genBlock(o: *Object, inst: *Inst.Block) !CValue {
626 const local = try o.allocLocal(inst.base.ty, .Mut);626 const local = try o.allocLocal(inst.base.ty, .Mut);
627 try writer.writeAll(";\n");627 try writer.writeAll(";\n");
628 break :blk local;628 break :blk local;
629 } else629 } else CValue{ .none = {} };
630 CValue{ .none = {} };
631630
632 inst.codegen.mcv = @bitCast(@import("../codegen.zig").AnyMCValue, result);631 inst.codegen.mcv = @bitCast(@import("../codegen.zig").AnyMCValue, result);
633 try genBody(o, inst.body);632 try genBody(o, inst.body);
src/codegen/spirv.zig+1-3
...@@ -45,7 +45,5 @@ pub const SPIRVModule = struct {...@@ -45,7 +45,5 @@ pub const SPIRVModule = struct {
45 return self.next_id;45 return self.next_id;
46 }46 }
4747
48 pub fn genDecl(self: SPIRVModule, id: u32, code: *std.ArrayList(u32), decl: *Decl) !void {48 pub fn genDecl(self: SPIRVModule, id: u32, code: *std.ArrayList(u32), decl: *Decl) !void {}
49
50 }
51};49};
src/link/SpirV.zig+16-16
...@@ -1,17 +1,3 @@...@@ -1,17 +1,3 @@
1const SpirV = @This();
2
3const std = @import("std");
4const Allocator = std.mem.Allocator;
5const assert = std.debug.assert;
6
7const Module = @import("../Module.zig");
8const Compilation = @import("../Compilation.zig");
9const link = @import("../link.zig");
10const codegen = @import("../codegen/spirv.zig");
11const trace = @import("../tracy.zig").trace;
12const build_options = @import("build_options");
13const spec = @import("../codegen/spirv/spec.zig");
14
15//! SPIR-V Spec documentation: https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html1//! SPIR-V Spec documentation: https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html
16//! According to above documentation, a SPIR-V module has the following logical layout:2//! According to above documentation, a SPIR-V module has the following logical layout:
17//! Header.3//! Header.
...@@ -30,6 +16,20 @@ const spec = @import("../codegen/spirv/spec.zig");...@@ -30,6 +16,20 @@ const spec = @import("../codegen/spirv/spec.zig");
30//! All function declarations without a body (extern functions presumably).16//! All function declarations without a body (extern functions presumably).
31//! All regular functions.17//! All regular functions.
3218
19const SpirV = @This();
20
21const std = @import("std");
22const Allocator = std.mem.Allocator;
23const assert = std.debug.assert;
24
25const Module = @import("../Module.zig");
26const Compilation = @import("../Compilation.zig");
27const link = @import("../link.zig");
28const codegen = @import("../codegen/spirv.zig");
29const trace = @import("../tracy.zig").trace;
30const build_options = @import("build_options");
31const spec = @import("../codegen/spirv/spec.zig");
32
33pub const FnData = struct {33pub const FnData = struct {
34 id: ?u32 = null,34 id: ?u32 = null,
35 code: std.ArrayListUnmanaged(u32) = .{},35 code: std.ArrayListUnmanaged(u32) = .{},
...@@ -199,7 +199,7 @@ fn writeCapabilities(binary: *std.ArrayList(u32), target: std.Target) !void {...@@ -199,7 +199,7 @@ fn writeCapabilities(binary: *std.ArrayList(u32), target: std.Target) !void {
199 else => unreachable, // TODO199 else => unreachable, // TODO
200 };200 };
201201
202 try codegen.writeInstruction(binary, .OpCapability, &[_]u32{ @enumToInt(cap) });202 try codegen.writeInstruction(binary, .OpCapability, &[_]u32{@enumToInt(cap)});
203}203}
204204
205fn writeMemoryModel(binary: *std.ArrayList(u32), target: std.Target) !void {205fn writeMemoryModel(binary: *std.ArrayList(u32), target: std.Target) !void {
...@@ -221,7 +221,7 @@ fn writeMemoryModel(binary: *std.ArrayList(u32), target: std.Target) !void {...@@ -221,7 +221,7 @@ fn writeMemoryModel(binary: *std.ArrayList(u32), target: std.Target) !void {
221 };221 };
222222
223 try codegen.writeInstruction(binary, .OpMemoryModel, &[_]u32{223 try codegen.writeInstruction(binary, .OpMemoryModel, &[_]u32{
224 @enumToInt(addressing_model), @enumToInt(memory_model)224 @enumToInt(addressing_model), @enumToInt(memory_model),
225 });225 });
226}226}
227227
src/main.zig+1-2
...@@ -3221,8 +3221,7 @@ pub const ClangArgIterator = struct {...@@ -3221,8 +3221,7 @@ pub const ClangArgIterator = struct {
3221 self.zig_equivalent = clang_arg.zig_equivalent;3221 self.zig_equivalent = clang_arg.zig_equivalent;
3222 break :find_clang_arg;3222 break :find_clang_arg;
3223 },3223 },
3224 }3224 } else {
3225 else {
3226 fatal("Unknown Clang option: '{s}'", .{arg});3225 fatal("Unknown Clang option: '{s}'", .{arg});
3227 }3226 }
3228 }3227 }
src/translate_c.zig+6-9
...@@ -2313,8 +2313,7 @@ fn transCaseStmt(c: *Context, scope: *Scope, stmt: *const clang.Stmt, items: *st...@@ -2313,8 +2313,7 @@ fn transCaseStmt(c: *Context, scope: *Scope, stmt: *const clang.Stmt, items: *st
2313 const rhs_node = try transExprCoercing(c, scope, rhs, .used);2313 const rhs_node = try transExprCoercing(c, scope, rhs, .used);
23142314
2315 break :blk try Tag.ellipsis3.create(c.arena, .{ .lhs = lhs_node, .rhs = rhs_node });2315 break :blk try Tag.ellipsis3.create(c.arena, .{ .lhs = lhs_node, .rhs = rhs_node });
2316 } else2316 } else try transExprCoercing(c, scope, case_stmt.getLHS(), .used);
2317 try transExprCoercing(c, scope, case_stmt.getLHS(), .used);
23182317
2319 try items.append(expr);2318 try items.append(expr);
2320 sub = case_stmt.getSubStmt();2319 sub = case_stmt.getSubStmt();
...@@ -2551,8 +2550,7 @@ fn transArrayAccess(c: *Context, scope: *Scope, stmt: *const clang.ArraySubscrip...@@ -2551,8 +2550,7 @@ fn transArrayAccess(c: *Context, scope: *Scope, stmt: *const clang.ArraySubscrip
2551 // check if long long first so that signed long long doesn't just become unsigned long long2550 // check if long long first so that signed long long doesn't just become unsigned long long
2552 var typeid_node = if (is_longlong) try Tag.identifier.create(c.arena, "usize") else try transQualTypeIntWidthOf(c, qt, false);2551 var typeid_node = if (is_longlong) try Tag.identifier.create(c.arena, "usize") else try transQualTypeIntWidthOf(c, qt, false);
2553 break :blk try Tag.int_cast.create(c.arena, .{ .lhs = typeid_node, .rhs = try transExpr(c, scope, subscr_expr, .used) });2552 break :blk try Tag.int_cast.create(c.arena, .{ .lhs = typeid_node, .rhs = try transExpr(c, scope, subscr_expr, .used) });
2554 } else2553 } else try transExpr(c, scope, subscr_expr, .used);
2555 try transExpr(c, scope, subscr_expr, .used);
25562554
2557 const node = try Tag.array_access.create(c.arena, .{2555 const node = try Tag.array_access.create(c.arena, .{
2558 .lhs = container_node,2556 .lhs = container_node,
...@@ -2752,8 +2750,7 @@ fn transUnaryOperator(c: *Context, scope: *Scope, stmt: *const clang.UnaryOperat...@@ -2752,8 +2750,7 @@ fn transUnaryOperator(c: *Context, scope: *Scope, stmt: *const clang.UnaryOperat
2752 } else if (cIsUnsignedInteger(op_expr.getType())) {2750 } else if (cIsUnsignedInteger(op_expr.getType())) {
2753 // use -% x for unsigned integers2751 // use -% x for unsigned integers
2754 return Tag.negate_wrap.create(c.arena, try transExpr(c, scope, op_expr, .used));2752 return Tag.negate_wrap.create(c.arena, try transExpr(c, scope, op_expr, .used));
2755 } else2753 } else return fail(c, error.UnsupportedTranslation, stmt.getBeginLoc(), "C negation with non float non integer", .{});
2756 return fail(c, error.UnsupportedTranslation, stmt.getBeginLoc(), "C negation with non float non integer", .{});
2757 },2754 },
2758 .Not => {2755 .Not => {
2759 return Tag.bit_not.create(c.arena, try transExpr(c, scope, op_expr, .used));2756 return Tag.bit_not.create(c.arena, try transExpr(c, scope, op_expr, .used));
...@@ -4593,7 +4590,8 @@ fn parseCPrimaryExprInner(c: *Context, m: *MacroCtx, scope: *Scope) ParseError!N...@@ -4593,7 +4590,8 @@ fn parseCPrimaryExprInner(c: *Context, m: *MacroCtx, scope: *Scope) ParseError!N
4593 // (type)alignof(x)4590 // (type)alignof(x)
4594 .Keyword_alignof,4591 .Keyword_alignof,
4595 // (type)identifier4592 // (type)identifier
4596 .Identifier => {},4593 .Identifier,
4594 => {},
4597 // (type)integer4595 // (type)integer
4598 .IntegerLiteral => {4596 .IntegerLiteral => {
4599 saw_integer_literal = true;4597 saw_integer_literal = true;
...@@ -5068,8 +5066,7 @@ fn getContainerTypeOf(c: *Context, ref: Node) ?Node {...@@ -5068,8 +5066,7 @@ fn getContainerTypeOf(c: *Context, ref: Node) ?Node {
5068 return getContainer(c, field.type);5066 return getContainer(c, field.type);
5069 }5067 }
5070 }5068 }
5071 } else5069 } else return ty_node;
5072 return ty_node;
5073 }5070 }
5074 }5071 }
5075 return null;5072 return null;
src/translate_c/ast.zig+3-3
...@@ -312,7 +312,7 @@ pub const Node = extern union {...@@ -312,7 +312,7 @@ pub const Node = extern union {
312 => Payload.Value,312 => Payload.Value,
313 .@"if" => Payload.If,313 .@"if" => Payload.If,
314 .@"while" => Payload.While,314 .@"while" => Payload.While,
315 .@"switch", .array_init,.switch_prong => Payload.Switch,315 .@"switch", .array_init, .switch_prong => Payload.Switch,
316 .break_val => Payload.BreakVal,316 .break_val => Payload.BreakVal,
317 .call => Payload.Call,317 .call => Payload.Call,
318 .var_decl => Payload.VarDecl,318 .var_decl => Payload.VarDecl,
...@@ -394,7 +394,8 @@ pub const Node = extern union {...@@ -394,7 +394,8 @@ pub const Node = extern union {
394 some.data394 some.data
395 else if (case.castTag(.switch_prong)) |some|395 else if (case.castTag(.switch_prong)) |some|
396 some.data.cond396 some.data.cond
397 else unreachable;397 else
398 unreachable;
398399
399 if (!body.isNoreturn(break_counts)) return false;400 if (!body.isNoreturn(break_counts)) return false;
400 }401 }
...@@ -406,7 +407,6 @@ pub const Node = extern union {...@@ -406,7 +407,6 @@ pub const Node = extern union {
406 }407 }
407 return false;408 return false;
408 }409 }
409
410};410};
411411
412pub const Payload = struct {412pub const Payload = struct {