From 588aa35b3a83bf7d3db17db8187d82257bdea2c9 Mon Sep 17 00:00:00 2001 From: Ayoctl Date: Sat, 17 Oct 2026 06:47:35 +0900 Subject: [PATCH] Workaround miscompilation on Apple Silicon CPUs As of 9cf3a2b7f8dbb, a handful of CPU features were added to Apple Silicon CPU models. This results in a broken compiler reporting `error.OutOfMemory` when it is compiled against those targets in release mode. A compiler built with `-DZIG_TARGET_MCPU=baseline` doesn't crash, and neither does one built after the LLVM 23 update, so it is likely that the LLVM 22 backend is mishandling these new features. Considering that this has already been fixed in LLVM 23, it is reasonable to introduce a workaround that gates a feature that a) fixes the problem and b) has less impact overall, hence this fix for 0.17.1. --- lib/std/zig/system.zig | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/lib/std/zig/system.zig b/lib/std/zig/system.zig index 41de483284a972e2f6e87668b739fba5592415ae..9b8eba1fc531a3f9c54782398e6883e423f994f7 100644 --- a/lib/std/zig/system.zig +++ b/lib/std/zig/system.zig @@ -453,6 +453,21 @@ pub fn resolveTargetQuery(io: Io, query: Target.Query) DetectError!Target { if (result.cpu.arch.isXtensa() and result.abi == .call0) { result.cpu.features.removeFeature(@backingInt(Target.xtensa.Feature.windowed)); } + + // A workaround for https://codeberg.org/ziglang/zig/issues/37215. + const apple_silicon_models = [_]*const Target.Cpu.Model{ + &Target.aarch64.cpu.apple_m1, + &Target.aarch64.cpu.apple_m2, + &Target.aarch64.cpu.apple_m3, + &Target.aarch64.cpu.apple_m4, + &Target.aarch64.cpu.apple_m5, + }; + for (apple_silicon_models) |model| { + if (result.cpu.model == model) { + result.cpu.features.removeFeature(@backingInt(Target.aarch64.Feature.fuse_aes)); + break; + } + } } // It's possible that we detect the native ABI, but fail to detect the OS version or were told -- 2.54.0