| author |  Alex Rønne Petersen <alex@alexrp.com> 2025-09-17 17:24:07+02:00 |
| committer | Alex Rønne Petersen <alex@alexrp.com> 2025-09-18 12:42:24+02:00 |
| log | 5e9e1fb0c85eacd412cb6cf4df14adc39f4c008a |
| tree | 6e8682d6f3571d5e7091561f3bf2389776af2e10 |
| parent | 6208e74145791c2f03e80e93caec4f87c60e638f |
| signature |  Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM |
std.Target: adjustments to LoongArch CPU models
* Remove the generic model; we already have generic_la32 and generic_la64 and
pick appropriately based on bitness.
* Remove the loongarch64 model. We used this as our baseline for 64-bit, but it's
actually pretty misleading and useless; it doesn't represent any real CPU and
has less features than generic_la64.
* Add la64v1_0 and la64v1_1 models.
* Change our baseline CPU model for 64-bit to be la64v1_0, thus adding LSX to
the baseline feature set.3 files changed, 55 insertions(+), 15 deletions(-)
lib- std
- Target.zig
- Target
lib/std/Target.zig+1-1
| ... | @@ -1903,7 +1903,7 @@ pub const Cpu = struct { | ... | @@ -1903,7 +1903,7 @@ pub const Cpu = struct { |
| 1903 | .csky => &csky.cpu.ck810, // gcc/clang do not have a generic csky model. | 1903 | .csky => &csky.cpu.ck810, // gcc/clang do not have a generic csky model. |
| 1904 | .hexagon => &hexagon.cpu.hexagonv68, // gcc/clang do not have a generic hexagon model. | 1904 | .hexagon => &hexagon.cpu.hexagonv68, // gcc/clang do not have a generic hexagon model. |
| 1905 | .lanai => &lanai.cpu.v11, // clang does not have a generic lanai model. | 1905 | .lanai => &lanai.cpu.v11, // clang does not have a generic lanai model. |
| 1906 | .loongarch64 => &loongarch.cpu.loongarch64, | 1906 | .loongarch64 => &loongarch.cpu.la64v1_0, |
| 1907 | .m68k => &m68k.cpu.M68000, | 1907 | .m68k => &m68k.cpu.M68000, |
| 1908 | .mips, .mipsel => &mips.cpu.mips32r2, | 1908 | .mips, .mipsel => &mips.cpu.mips32r2, |
| 1909 | .mips64, .mips64el => &mips.cpu.mips64r2, | 1909 | .mips64, .mips64el => &mips.cpu.mips64r2, |
lib/std/Target/loongarch.zig+24-14
| ... | @@ -159,11 +159,6 @@ pub const all_features = blk: { | ... | @@ -159,11 +159,6 @@ pub const all_features = blk: { |
| 159 | }; | 159 | }; |
| 160 | 160 | ||
| 161 | pub const cpu = struct { | 161 | pub const cpu = struct { |
| 162 | pub const generic: CpuModel = .{ | ||
| 163 | .name = "generic", | ||
| 164 | .llvm_name = "generic", | ||
| 165 | .features = featureSet(&[_]Feature{}), | ||
| 166 | }; | ||
| 167 | pub const generic_la32: CpuModel = .{ | 162 | pub const generic_la32: CpuModel = .{ |
| 168 | .name = "generic_la32", | 163 | .name = "generic_la32", |
| 169 | .llvm_name = "generic-la32", | 164 | .llvm_name = "generic-la32", |
| ... | @@ -191,6 +186,30 @@ pub const cpu = struct { | ... | @@ -191,6 +186,30 @@ pub const cpu = struct { |
| 191 | .ual, | 186 | .ual, |
| 192 | }), | 187 | }), |
| 193 | }; | 188 | }; |
| 189 | pub const la64v1_0: CpuModel = .{ | ||
| 190 | .name = "la64v1_0", | ||
| 191 | .llvm_name = null, | ||
| 192 | .features = featureSet(&[_]Feature{ | ||
| 193 | .@"64bit", | ||
| 194 | .lsx, | ||
| 195 | .ual, | ||
| 196 | }), | ||
| 197 | }; | ||
| 198 | pub const la64v1_1: CpuModel = .{ | ||
| 199 | .name = "la64v1_1", | ||
| 200 | .llvm_name = null, | ||
| 201 | .features = featureSet(&[_]Feature{ | ||
| 202 | .@"64bit", | ||
| 203 | .div32, | ||
| 204 | .frecipe, | ||
| 205 | .lam_bh, | ||
| 206 | .lamcas, | ||
| 207 | .ld_seq_sa, | ||
| 208 | .lsx, | ||
| 209 | .scq, | ||
| 210 | .ual, | ||
| 211 | }), | ||
| 212 | }; | ||
| 194 | pub const la664: CpuModel = .{ | 213 | pub const la664: CpuModel = .{ |
| 195 | .name = "la664", | 214 | .name = "la664", |
| 196 | .llvm_name = "la664", | 215 | .llvm_name = "la664", |
| ... | @@ -208,13 +227,4 @@ pub const cpu = struct { | ... | @@ -208,13 +227,4 @@ pub const cpu = struct { |
| 208 | .ual, | 227 | .ual, |
| 209 | }), | 228 | }), |
| 210 | }; | 229 | }; |
| 211 | pub const loongarch64: CpuModel = .{ | ||
| 212 | .name = "loongarch64", | ||
| 213 | .llvm_name = "loongarch64", | ||
| 214 | .features = featureSet(&[_]Feature{ | ||
| 215 | .@"64bit", | ||
| 216 | .d, | ||
| 217 | .ual, | ||
| 218 | }), | ||
| 219 | }; | ||
| 220 | }; | 230 | }; |
tools/update_cpu_features.zig+30
| ... | @@ -986,6 +986,36 @@ const targets = [_]ArchTarget{ | ... | @@ -986,6 +986,36 @@ const targets = [_]ArchTarget{ |
| 986 | .name = "LoongArch", | 986 | .name = "LoongArch", |
| 987 | .td_name = "LoongArch", | 987 | .td_name = "LoongArch", |
| 988 | }, | 988 | }, |
| 989 | .extra_cpus = &.{ | ||
| 990 | .{ | ||
| 991 | .llvm_name = null, | ||
| 992 | .zig_name = "la64v1_0", | ||
| 993 | .features = &.{ | ||
| 994 | "64bit", | ||
| 995 | "lsx", | ||
| 996 | "ual", | ||
| 997 | }, | ||
| 998 | }, | ||
| 999 | .{ | ||
| 1000 | .llvm_name = null, | ||
| 1001 | .zig_name = "la64v1_1", | ||
| 1002 | .features = &.{ | ||
| 1003 | "64bit", | ||
| 1004 | "div32", | ||
| 1005 | "frecipe", | ||
| 1006 | "lam_bh", | ||
| 1007 | "lamcas", | ||
| 1008 | "ld_seq_sa", | ||
| 1009 | "lsx", | ||
| 1010 | "scq", | ||
| 1011 | "ual", | ||
| 1012 | }, | ||
| 1013 | }, | ||
| 1014 | }, | ||
| 1015 | .omit_cpus = &.{ | ||
| 1016 | "generic", | ||
| 1017 | "loongarch64", | ||
| 1018 | }, | ||
| 989 | }, | 1019 | }, |
| 990 | .{ | 1020 | .{ |
| 991 | .zig_name = "m68k", | 1021 | .zig_name = "m68k", |