From 603798d409a963ccdf5ab2273a6a02ef04d0952b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= <alex@alexrp.com>
Date: Mon, 7 Sep 2026 02:27:38 +0200
Subject: [PATCH] std.zig.system.linux: some corrections to riscv CPU model
 list

---
 lib/std/zig/system/linux.zig | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/lib/std/zig/system/linux.zig b/lib/std/zig/system/linux.zig
index b1375aa17aad7f77cc986c36de5ef817ba53c35c..a1c1eb5137b9d1db37717265823ad544a60e5933 100644
--- a/lib/std/zig/system/linux.zig
+++ b/lib/std/zig/system/linux.zig
@@ -71,10 +71,11 @@ const RiscvCpuinfoImpl = struct {
 
     const cpu_names = .{
         .{ "andestech,ax45mp", &Target.riscv.cpu.andes_ax45 },
+        .{ "sifive,bullet0", &Target.riscv.cpu.sifive_u74 },
         .{ "sifive,p550", &Target.riscv.cpu.sifive_p550 },
         .{ "sifive,u54", &Target.riscv.cpu.sifive_u54 },
         .{ "sifive,u54-mc", &Target.riscv.cpu.sifive_u54 },
-        .{ "sifive,u7", &Target.riscv.cpu.sifive_7_series },
+        .{ "sifive,u7", &Target.riscv.cpu.sifive_u74 },
         .{ "sifive,u74", &Target.riscv.cpu.sifive_u74 },
         .{ "sifive,u74-mc", &Target.riscv.cpu.sifive_u74 },
         .{ "sifive,x280", &Target.riscv.cpu.sifive_x280 },
-- 
2.54.0