authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2024-07-26 03:14:32+02:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2024-08-01 01:01:24-07:00
log604e87a95868094bdddbcc6a4579f8535ae5e2a9
treea6b6afb9f6d8f82ac00aff891316a0844744e205
parent9c22a6b3ade561b4009020547980fcf2d76a9f57

std.Target: Use hexagonv60 as the baseline CPU model for hexagon.

1 files changed, 1 insertions(+), 0 deletions(-)

lib/std/Target.zig+1
...@@ -1512,6 +1512,7 @@ pub const Cpu = struct {...@@ -1512,6 +1512,7 @@ pub const Cpu = struct {
1512 pub fn baseline(arch: Arch) *const Model {1512 pub fn baseline(arch: Arch) *const Model {
1513 return switch (arch) {1513 return switch (arch) {
1514 .arm, .armeb, .thumb, .thumbeb => &arm.cpu.baseline,1514 .arm, .armeb, .thumb, .thumbeb => &arm.cpu.baseline,
1515 .hexagon => &hexagon.cpu.hexagonv60,
1515 .riscv32 => &riscv.cpu.baseline_rv32,1516 .riscv32 => &riscv.cpu.baseline_rv32,
1516 .riscv64 => &riscv.cpu.baseline_rv64,1517 .riscv64 => &riscv.cpu.baseline_rv64,
1517 .x86 => &x86.cpu.pentium4,1518 .x86 => &x86.cpu.pentium4,