authorgravatar for koachan@protonmail.comKoakuma <koachan@protonmail.com> 2022-06-15 23:29:19+07:00
committergravatar for koachan@protonmail.comKoakuma <koachan@protonmail.com> 2022-06-24 21:19:33+07:00
log672cd2f02f734a58c577a00f2bef831b6f73e8ff
tree165025f0ad3e7839b44a4070f38e3273e275dbd2
parent6218d70d09cf60e3c1d83cdd5b49ea9eed3d5259

stage2: sparc64: Implement SPARCv9 and

2 files changed, 11 insertions(+), 1 deletions(-)

src/arch/sparc64/Emit.zig+3-1
...@@ -93,7 +93,7 @@ pub fn emitMir(...@@ -93,7 +93,7 @@ pub fn emitMir(
93 .lduw => try emit.mirArithmetic3Op(inst),93 .lduw => try emit.mirArithmetic3Op(inst),
94 .ldx => try emit.mirArithmetic3Op(inst),94 .ldx => try emit.mirArithmetic3Op(inst),
9595
96 .@"and" => @panic("TODO implement sparc64 and"),96 .@"and" => try emit.mirArithmetic3Op(inst),
97 .@"or" => try emit.mirArithmetic3Op(inst),97 .@"or" => try emit.mirArithmetic3Op(inst),
98 .xor => try emit.mirArithmetic3Op(inst),98 .xor => try emit.mirArithmetic3Op(inst),
99 .xnor => try emit.mirArithmetic3Op(inst),99 .xnor => try emit.mirArithmetic3Op(inst),
...@@ -227,6 +227,7 @@ fn mirArithmetic3Op(emit: *Emit, inst: Mir.Inst.Index) !void {...@@ -227,6 +227,7 @@ fn mirArithmetic3Op(emit: *Emit, inst: Mir.Inst.Index) !void {
227 .lduh => try emit.writeInstruction(Instruction.lduh(i13, rs1, imm, rd)),227 .lduh => try emit.writeInstruction(Instruction.lduh(i13, rs1, imm, rd)),
228 .lduw => try emit.writeInstruction(Instruction.lduw(i13, rs1, imm, rd)),228 .lduw => try emit.writeInstruction(Instruction.lduw(i13, rs1, imm, rd)),
229 .ldx => try emit.writeInstruction(Instruction.ldx(i13, rs1, imm, rd)),229 .ldx => try emit.writeInstruction(Instruction.ldx(i13, rs1, imm, rd)),
230 .@"and" => try emit.writeInstruction(Instruction.@"and"(i13, rs1, imm, rd)),
230 .@"or" => try emit.writeInstruction(Instruction.@"or"(i13, rs1, imm, rd)),231 .@"or" => try emit.writeInstruction(Instruction.@"or"(i13, rs1, imm, rd)),
231 .xor => try emit.writeInstruction(Instruction.xor(i13, rs1, imm, rd)),232 .xor => try emit.writeInstruction(Instruction.xor(i13, rs1, imm, rd)),
232 .xnor => try emit.writeInstruction(Instruction.xnor(i13, rs1, imm, rd)),233 .xnor => try emit.writeInstruction(Instruction.xnor(i13, rs1, imm, rd)),
...@@ -251,6 +252,7 @@ fn mirArithmetic3Op(emit: *Emit, inst: Mir.Inst.Index) !void {...@@ -251,6 +252,7 @@ fn mirArithmetic3Op(emit: *Emit, inst: Mir.Inst.Index) !void {
251 .lduh => try emit.writeInstruction(Instruction.lduh(Register, rs1, rs2, rd)),252 .lduh => try emit.writeInstruction(Instruction.lduh(Register, rs1, rs2, rd)),
252 .lduw => try emit.writeInstruction(Instruction.lduw(Register, rs1, rs2, rd)),253 .lduw => try emit.writeInstruction(Instruction.lduw(Register, rs1, rs2, rd)),
253 .ldx => try emit.writeInstruction(Instruction.ldx(Register, rs1, rs2, rd)),254 .ldx => try emit.writeInstruction(Instruction.ldx(Register, rs1, rs2, rd)),
255 .@"and" => try emit.writeInstruction(Instruction.@"and"(Register, rs1, rs2, rd)),
254 .@"or" => try emit.writeInstruction(Instruction.@"or"(Register, rs1, rs2, rd)),256 .@"or" => try emit.writeInstruction(Instruction.@"or"(Register, rs1, rs2, rd)),
255 .xor => try emit.writeInstruction(Instruction.xor(Register, rs1, rs2, rd)),257 .xor => try emit.writeInstruction(Instruction.xor(Register, rs1, rs2, rd)),
256 .xnor => try emit.writeInstruction(Instruction.xnor(Register, rs1, rs2, rd)),258 .xnor => try emit.writeInstruction(Instruction.xnor(Register, rs1, rs2, rd)),
src/arch/sparc64/bits.zig+8
...@@ -1229,6 +1229,14 @@ pub const Instruction = union(enum) {...@@ -1229,6 +1229,14 @@ pub const Instruction = union(enum) {
1229 };1229 };
1230 }1230 }
12311231
1232 pub fn @"and"(comptime s2: type, rs1: Register, rs2: s2, rd: Register) Instruction {
1233 return switch (s2) {
1234 Register => format3a(0b10, 0b00_0001, rs1, rs2, rd),
1235 i13 => format3b(0b10, 0b00_0001, rs1, rs2, rd),
1236 else => unreachable,
1237 };
1238 }
1239
1232 pub fn @"or"(comptime s2: type, rs1: Register, rs2: s2, rd: Register) Instruction {1240 pub fn @"or"(comptime s2: type, rs1: Register, rs2: s2, rd: Register) Instruction {
1233 return switch (s2) {1241 return switch (s2) {
1234 Register => format3a(0b10, 0b00_0010, rs1, rs2, rd),1242 Register => format3a(0b10, 0b00_0010, rs1, rs2, rd),