| ... | ... | @@ -16107,20 +16107,12 @@ const Struct_array_1_f32 = extern struct { |
| 16107 | 16107 | a: [1]f32, |
| 16108 | 16108 | }; |
| 16109 | 16109 | |
| 16110 | | comptime { |
| 16111 | | skip: { |
| 16112 | | if (builtin.cpu.arch.isWasm()) break :skip; |
| 16113 | | |
| 16114 | | _ = struct { |
| 16115 | | export fn zig_ret_struct_array_1_f32() Struct_array_1_f32 { |
| 16116 | | return .{ .a = .{1} }; |
| 16117 | | } |
| 16118 | | export fn zig_struct_array_1_f32(s: Struct_array_1_f32, i: usize) void { |
| 16119 | | expect(s.a[0] == 2) catch @panic("test failure"); |
| 16120 | | expect(i == 3) catch @panic("test failure"); |
| 16121 | | } |
| 16122 | | }; |
| 16123 | | } |
| 16110 | export fn zig_ret_struct_array_1_f32() Struct_array_1_f32 { |
| 16111 | return .{ .a = .{1} }; |
| 16112 | } |
| 16113 | export fn zig_struct_array_1_f32(s: Struct_array_1_f32, i: usize) void { |
| 16114 | expect(s.a[0] == 2) catch @panic("test failure"); |
| 16115 | expect(i == 3) catch @panic("test failure"); |
| 16124 | 16116 | } |
| 16125 | 16117 | |
| 16126 | 16118 | extern fn c_ret_struct_array_1_f32() Struct_array_1_f32; |
| ... | ... | @@ -16134,7 +16126,6 @@ test "struct [1]f32" { |
| 16134 | 16126 | if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest; |
| 16135 | 16127 | if (builtin.cpu.arch.isRISCV()) return error.SkipZigTest; |
| 16136 | 16128 | if (builtin.cpu.arch == .s390x) return error.SkipZigTest; |
| 16137 | | if (builtin.cpu.arch.isWasm()) return error.SkipZigTest; |
| 16138 | 16129 | |
| 16139 | 16130 | const s = c_ret_struct_array_1_f32(); |
| 16140 | 16131 | try expect(s.a[0] == 4); |
| ... | ... | @@ -16303,7 +16294,6 @@ test "struct [0:sentinel]f32" { |
| 16303 | 16294 | if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest; |
| 16304 | 16295 | if (builtin.cpu.arch.isRISCV()) return error.SkipZigTest; |
| 16305 | 16296 | if (builtin.cpu.arch == .s390x) return error.SkipZigTest; |
| 16306 | | if (builtin.cpu.arch.isWasm()) return error.SkipZigTest; |
| 16307 | 16297 | |
| 16308 | 16298 | var sentinel_index: usize = 0; |
| 16309 | 16299 | _ = &sentinel_index; |
| ... | ... | @@ -16766,20 +16756,12 @@ const Struct_array_1_f64 = extern struct { |
| 16766 | 16756 | a: [1]f64, |
| 16767 | 16757 | }; |
| 16768 | 16758 | |
| 16769 | | comptime { |
| 16770 | | skip: { |
| 16771 | | if (builtin.cpu.arch.isWasm()) break :skip; |
| 16772 | | |
| 16773 | | _ = struct { |
| 16774 | | export fn zig_ret_struct_array_1_f64() Struct_array_1_f64 { |
| 16775 | | return .{ .a = .{1} }; |
| 16776 | | } |
| 16777 | | export fn zig_struct_array_1_f64(s: Struct_array_1_f64, i: usize) void { |
| 16778 | | expect(s.a[0] == 2) catch @panic("test failure"); |
| 16779 | | expect(i == 3) catch @panic("test failure"); |
| 16780 | | } |
| 16781 | | }; |
| 16782 | | } |
| 16759 | export fn zig_ret_struct_array_1_f64() Struct_array_1_f64 { |
| 16760 | return .{ .a = .{1} }; |
| 16761 | } |
| 16762 | export fn zig_struct_array_1_f64(s: Struct_array_1_f64, i: usize) void { |
| 16763 | expect(s.a[0] == 2) catch @panic("test failure"); |
| 16764 | expect(i == 3) catch @panic("test failure"); |
| 16783 | 16765 | } |
| 16784 | 16766 | |
| 16785 | 16767 | extern fn c_ret_struct_array_1_f64() Struct_array_1_f64; |
| ... | ... | @@ -16793,7 +16775,6 @@ test "struct [1]f64" { |
| 16793 | 16775 | if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest; |
| 16794 | 16776 | if (builtin.cpu.arch.isRISCV()) return error.SkipZigTest; |
| 16795 | 16777 | if (builtin.cpu.arch == .s390x) return error.SkipZigTest; |
| 16796 | | if (builtin.cpu.arch.isWasm()) return error.SkipZigTest; |
| 16797 | 16778 | |
| 16798 | 16779 | const s = c_ret_struct_array_1_f64(); |
| 16799 | 16780 | try expect(s.a[0] == 4); |