diff --git a/lib/std/zig/system/openbsd.zig b/lib/std/zig/system/openbsd.zig
index 39f2156ffa7dd189d826c4c4549e6e21445a6ee1..7c2dc0b143414bf156f1dd8f3da9e5a6d3a6e076 100644
--- a/lib/std/zig/system/openbsd.zig
+++ b/lib/std/zig/system/openbsd.zig
@@ -3,6 +3,24 @@ const std = @import("std");
 
 const native_arch = builtin.target.cpu.arch;
 
+fn hwModelName(buf: [:0]u8) ?[:0]const u8 {
+    const mib: [2]c_int = [_]c_int{
+        std.c.CTL.HW,
+        std.c.HW.MODEL,
+    };
+    var len: usize = buf.len + 1;
+
+    std.posix.sysctl(&mib, buf.ptr, &len, null, 0) catch |err| switch (err) {
+        error.NameTooLong => unreachable,
+        error.PermissionDenied => unreachable,
+        error.SystemResources => unreachable,
+        error.UnknownName => unreachable,
+        error.Unexpected => return null,
+    };
+
+    return buf[0 .. len - 1 :0];
+}
+
 const aarch64 = struct {
     fn sysctlReg(key: c_int) ?u64 {
         const mib: [2]c_int = [_]c_int{
@@ -43,6 +61,37 @@ const aarch64 = struct {
     }
 };
 
+const arm = struct {
+    const models = .{
+        .{ "ARM Cortex-A12", &std.Target.arm.cpu.cortex_a12 },
+        .{ "ARM Cortex-A15", &std.Target.arm.cpu.cortex_a15 },
+        .{ "ARM Cortex-A17", &std.Target.arm.cpu.cortex_a17 },
+        .{ "ARM Cortex-A32", &std.Target.arm.cpu.cortex_a32 },
+        .{ "ARM Cortex-A35", &std.Target.arm.cpu.cortex_a35 },
+        .{ "ARM Cortex-A53", &std.Target.arm.cpu.cortex_a53 },
+        .{ "ARM Cortex-A55", &std.Target.arm.cpu.cortex_a55 },
+        .{ "ARM Cortex-A57", &std.Target.arm.cpu.cortex_a57 },
+        .{ "ARM Cortex-A5", &std.Target.arm.cpu.cortex_a5 },
+        .{ "ARM Cortex-A72", &std.Target.arm.cpu.cortex_a72 },
+        .{ "ARM Cortex-A73", &std.Target.arm.cpu.cortex_a73 },
+        .{ "ARM Cortex-A75", &std.Target.arm.cpu.cortex_a75 },
+        .{ "ARM Cortex-A7", &std.Target.arm.cpu.cortex_a7 },
+        .{ "ARM Cortex-A8", &std.Target.arm.cpu.cortex_a8 },
+        .{ "ARM Cortex-A9", &std.Target.arm.cpu.cortex_a9 },
+    };
+
+    fn detectNativeCpu(arch: std.Target.Cpu.Arch) ?std.Target.Cpu {
+        var buf: [64:0]u8 = undefined;
+        const name = hwModelName(&buf) orelse return null;
+
+        inline for (models) |pair| {
+            if (std.mem.startsWith(u8, name, pair[0])) return pair[1].toCpu(arch);
+        }
+
+        return null;
+    }
+};
+
 const powerpc = struct {
     const models = .{
         .{ "601", &std.Target.powerpc.cpu.@"601" },
@@ -72,22 +121,8 @@ const powerpc = struct {
     };
 
     fn detectNativeCpu(arch: std.Target.Cpu.Arch) ?std.Target.Cpu {
-        const mib: [2]c_int = [_]c_int{
-            std.c.CTL.HW,
-            std.c.HW.MODEL,
-        };
         var buf: [64:0]u8 = undefined;
-        var len: usize = buf.len + 1;
-
-        std.posix.sysctl(&mib, &buf, &len, null, 0) catch |err| switch (err) {
-            error.NameTooLong => unreachable,
-            error.PermissionDenied => unreachable,
-            error.SystemResources => unreachable,
-            error.UnknownName => unreachable,
-            error.Unexpected => return null,
-        };
-
-        const name = buf[0 .. len - 1 :0];
+        const name = hwModelName(&buf) orelse return null;
 
         inline for (models) |pair| {
             if (std.mem.startsWith(u8, name, pair[0])) return pair[1].toCpu(arch);
@@ -100,6 +135,7 @@ const powerpc = struct {
 pub fn detectNativeCpuAndFeatures() ?std.Target.Cpu {
     return switch (native_arch) {
         .aarch64 => aarch64.detectNativeCpuAndFeatures(native_arch),
+        .arm => arm.detectNativeCpu(native_arch),
         .powerpc, .powerpc64 => powerpc.detectNativeCpu(native_arch),
         else => null,
     };