authorgravatar for joachim.schmidt557@outlook.comJoachim Schmidt <joachim.schmidt557@outlook.com> 2020-10-11 09:57:25+02:00
committergravatar for joachim.schmidt557@outlook.comJoachim Schmidt <joachim.schmidt557@outlook.com> 2020-10-25 12:51:19+01:00
log7391087df152e0e721259cb90e31474eb46e4f86
tree298e7d07501d6241c4944022bfc1f0c0d69b7a0f
parent59af275680ad12f7da4dcc5b41a2cab707ec2ffa

stage2 ARM: better immediate loading feat. movw and movt

2 files changed, 83 insertions(+), 27 deletions(-)

src/codegen.zig+31-27
......@@ -2274,35 +2274,39 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
22742274 return self.genSetReg(src, reg, .{ .immediate = 0xaaaaaaaa });
22752275 },
22762276 .immediate => |x| {
2277 // TODO better analysis of x to determine the
2278 // least amount of necessary instructions (use
2279 // more intelligent rotating)
2280 if (x <= math.maxInt(u8)) {
2281 mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, reg, Instruction.Operand.imm(@truncate(u8, x), 0)).toU32());
2282 return;
2283 } else if (x <= math.maxInt(u16)) {
2284 // TODO Use movw Note: Not supported on
2285 // all ARM targets!
2286 mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, reg, Instruction.Operand.imm(@truncate(u8, x), 0)).toU32());
2287 mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 8), 12)).toU32());
2288 } else if (x <= math.maxInt(u32)) {
2289 // TODO Use movw and movt Note: Not
2290 // supported on all ARM targets! Also TODO
2291 // write constant to code and load
2292 // relative to pc
2277 if (x > math.maxInt(u32)) return self.fail(src, "ARM registers are 32-bit wide", .{});
22932278
2294 // immediate: 0xaabbccdd
2295 // mov reg, #0xaa
2296 // orr reg, reg, #0xbb, 24
2297 // orr reg, reg, #0xcc, 16
2298 // orr reg, reg, #0xdd, 8
2299 mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, reg, Instruction.Operand.imm(@truncate(u8, x), 0)).toU32());
2300 mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 8), 12)).toU32());
2301 mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 16), 8)).toU32());
2302 mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 24), 4)).toU32());
2303 return;
2279 if (Instruction.Operand.fromU32(@intCast(u32, x))) |op| {
2280 mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, reg, op).toU32());
2281 } else if (Instruction.Operand.fromU32(~@intCast(u32, x))) |op| {
2282 mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mvn(.al, reg, op).toU32());
2283 } else if (x <= math.maxInt(u16)) {
2284 if (Target.arm.featureSetHas(self.target.cpu.features, .has_v7)) {
2285 mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.movw(.al, reg, @intCast(u16, x)).toU32());
2286 } else {
2287 mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, reg, Instruction.Operand.imm(@truncate(u8, x), 0)).toU32());
2288 mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 8), 12)).toU32());
2289 }
23042290 } else {
2305 return self.fail(src, "ARM registers are 32-bit wide", .{});
2291 // TODO write constant to code and load
2292 // relative to pc
2293 if (Target.arm.featureSetHas(self.target.cpu.features, .has_v7)) {
2294 // immediate: 0xaaaabbbb
2295 // movw reg, #0xbbbb
2296 // movt reg, #0xaaaa
2297 mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.movw(.al, reg, @truncate(u16, x)).toU32());
2298 mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.movt(.al, reg, @truncate(u16, x >> 16)).toU32());
2299 } else {
2300 // immediate: 0xaabbccdd
2301 // mov reg, #0xaa
2302 // orr reg, reg, #0xbb, 24
2303 // orr reg, reg, #0xcc, 16
2304 // orr reg, reg, #0xdd, 8
2305 mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.mov(.al, reg, Instruction.Operand.imm(@truncate(u8, x), 0)).toU32());
2306 mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 8), 12)).toU32());
2307 mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 16), 8)).toU32());
2308 mem.writeIntLittle(u32, try self.code.addManyAsArray(4), Instruction.orr(.al, reg, reg, Instruction.Operand.imm(@truncate(u8, x >> 24), 4)).toU32());
2309 }
23062310 }
23072311 },
23082312 .register => |src_reg| {
src/codegen/arm.zig+52
......@@ -317,6 +317,29 @@ pub const Instruction = union(enum) {
317317 },
318318 };
319319 }
320
321 /// Tries to convert an unsigned 32 bit integer into an
322 /// immediate operand using rotation. Returns null when there
323 /// is no conversion
324 pub fn fromU32(x: u32) ?Operand {
325 const masks = comptime blk: {
326 const base_mask: u32 = std.math.maxInt(u8);
327 var result = [_]u32{0} ** 16;
328 for (result) |*mask, i| mask.* = std.math.rotr(u32, base_mask, 2 * i);
329 break :blk result;
330 };
331
332 return for (masks) |mask, i| {
333 if (x & mask == x) {
334 break Operand{
335 .Immediate = .{
336 .imm = @intCast(u8, std.math.rotl(u32, x, 2 * i)),
337 .rotate = @intCast(u4, i),
338 },
339 };
340 }
341 } else null;
342 }
320343 };
321344
322345 /// Represents the offset operand of a load or store
......@@ -412,6 +435,25 @@ pub const Instruction = union(enum) {
412435 };
413436 }
414437
438 fn specialMov(
439 cond: Condition,
440 rd: Register,
441 imm: u16,
442 top: bool,
443 ) Instruction {
444 return Instruction{
445 .DataProcessing = .{
446 .cond = @enumToInt(cond),
447 .i = 1,
448 .opcode = if (top) 0b1010 else 0b1000,
449 .s = 0,
450 .rn = @truncate(u4, imm >> 12),
451 .rd = rd.id(),
452 .op2 = @truncate(u12, imm),
453 },
454 };
455 }
456
415457 fn singleDataTransfer(
416458 cond: Condition,
417459 rd: Register,
......@@ -618,6 +660,16 @@ pub const Instruction = union(enum) {
618660 return dataProcessing(cond, .mvn, 1, rd, .r0, op2);
619661 }
620662
663 // movw and movt
664
665 pub fn movw(cond: Condition, rd: Register, imm: u16) Instruction {
666 return specialMov(cond, rd, imm, false);
667 }
668
669 pub fn movt(cond: Condition, rd: Register, imm: u16) Instruction {
670 return specialMov(cond, rd, imm, true);
671 }
672
621673 // PSR transfer
622674
623675 pub fn mrs(cond: Condition, rd: Register, psr: Psr) Instruction {