From 73f6d498fc83763054f62677f3a67871d3825136 Mon Sep 17 00:00:00 2001 From: Pavel Verigo Date: Mon, 6 Jul 2026 12:19:58 +0200 Subject: [PATCH] compiler: use @divCeil --- src/Air.zig | 6 +++--- src/Air/Legalize.zig | 2 +- src/InternPool.zig | 6 +++--- src/Sema.zig | 10 +++++----- src/Sema/arith.zig | 14 +++++++------- src/Type.zig | 6 +++--- src/codegen/aarch64/Select.zig | 20 ++++++++++---------- src/codegen/llvm/FuncGen.zig | 4 ++-- src/codegen/riscv64/CodeGen.zig | 3 +-- src/codegen/spirv/Assembler.zig | 2 +- src/codegen/spirv/Section.zig | 2 +- src/codegen/wasm/CodeGen.zig | 6 +++--- src/codegen/x86_64/CodeGen.zig | 12 ++++++------ src/codegen/x86_64/Emit.zig | 2 +- src/link/Dwarf.zig | 6 +++--- 15 files changed, 50 insertions(+), 51 deletions(-) diff --git a/src/Air.zig b/src/Air.zig index a03899740deb47f228cfddb27b47699427b81d95..cdae23d2f5cf1b4ff470ee5f4bb0584b07e26a52 100644 --- a/src/Air.zig +++ b/src/Air.zig @@ -1517,7 +1517,7 @@ pub const ShuffleTwoMask = enum(u32) { /// Trailing: /// 0. `Inst.Ref` for every outputs_len /// 1. `Inst.Ref` for every inputs_len -/// 2. A number of u32 elements follow according to the equation `(source_len + 3) / 4`. +/// 2. A number of u32 elements follow according to the equation `@divCeil(source_len, 4)`. /// Memory starting at this position is reinterpreted as the source bytes. /// 3. for every outputs_len /// - constraint: memory at this position is reinterpreted as a null @@ -2225,7 +2225,7 @@ pub fn unwrapSwitch(air: *const Air, switch_inst: Inst.Index) UnwrappedSwitch { } const pl_op = inst.data.pl_op; const extra = air.extraData(SwitchBr, pl_op.payload); - const hint_bag_count = std.math.divCeil(usize, extra.data.cases_len + 1, 10) catch unreachable; + const hint_bag_count = @divCeil(extra.data.cases_len + 1, 10); return .{ .air = air, .operand = pl_op.operand, @@ -2394,7 +2394,7 @@ pub const UnwrappedAsm = struct { const name = std.mem.sliceTo(constraint_name[constraint.len + 1 ..], 0); // This equation accounts for the fact that even if we have exactly 4 bytes // for the string, we still use the next u32 for the null terminator. - const next_offset = std.math.divCeil(usize, constraint.len + 1 + name.len + 1, @sizeOf(u32)) catch unreachable; + const next_offset = @divCeil(constraint.len + 1 + name.len + 1, @sizeOf(u32)); self.constraint_names = self.constraint_names[next_offset..]; return .{ diff --git a/src/Air/Legalize.zig b/src/Air/Legalize.zig index 08081e5fee85ded748401f7257042fdcd5e71c02..81df10c169d0f358adc769d0681ce27bf45e6484 100644 --- a/src/Air/Legalize.zig +++ b/src/Air/Legalize.zig @@ -746,7 +746,7 @@ fn legalizeBody(l: *Legalize, body_start: usize, body_len: usize) Error!void { .switch_br, .loop_switch_br => { const pl_op = l.air_instructions.items(.data)[@intFromEnum(inst)].pl_op; const extra = l.extraData(Air.SwitchBr, pl_op.payload); - const hint_bag_count = std.math.divCeil(usize, extra.data.cases_len + 1, 10) catch unreachable; + const hint_bag_count = @divCeil(extra.data.cases_len + 1, 10); var extra_index = extra.end + hint_bag_count; for (0..extra.data.cases_len) |_| { const case_extra = l.extraData(Air.SwitchBr.Case, extra_index); diff --git a/src/InternPool.zig b/src/InternPool.zig index 792b7636a46f0cf40686efe14bc490ef7d68f1f9..eae7f32c7f17782b694a21d06c52bfe456049dcf 100644 --- a/src/InternPool.zig +++ b/src/InternPool.zig @@ -3581,11 +3581,11 @@ pub fn loadStructType(ip: *const InternPool, index: Index) LoadedStructType { .start = extra_index, .len = extra.data.fields_len, } else .empty; - extra_index += std.math.divCeil(u32, field_aligns.len, 4) catch unreachable; + extra_index += @divCeil(field_aligns.len, 4); const field_is_comptime_bits: LoadedStructType.ComptimeBits = if (extra.data.flags.any_comptime_fields) .{ .tid = unwrapped_index.tid, .start = extra_index, - .len = std.math.divCeil(u32, extra.data.fields_len, 32) catch unreachable, + .len = @divCeil(extra.data.fields_len, 32), } else .empty; extra_index += field_is_comptime_bits.len; const field_runtime_order: LoadedStructType.RuntimeOrder.Slice = if (extra.data.flags.layout == .auto) .{ @@ -3737,7 +3737,7 @@ pub fn loadUnionType(ip: *const InternPool, index: Index) LoadedUnionType { .start = extra_index, .len = extra.data.fields_len, } else .empty; - extra_index += std.math.divCeil(u32, field_aligns.len, 4) catch unreachable; + extra_index += @divCeil(field_aligns.len, 4); return .{ .zir_index = extra.data.zir_index, diff --git a/src/Sema.zig b/src/Sema.zig index 923f43414695ef79ebb2d732c349238363259b69..dfd37d70ec9787b7d8ded314ea5314b1e8513b64 100644 --- a/src/Sema.zig +++ b/src/Sema.zig @@ -10305,7 +10305,7 @@ fn finishSwitchBr( fn ensureUnusedCapacity(hints: *@This(), gpa_inner: Allocator, additional_count: u32) Allocator.Error!void { const unused_hints = hints.bags.capacity * hints_per_bag - hints.count; if (unused_hints >= additional_count) return; - const bags_required = std.math.divCeil(u32, hints.count + additional_count, hints_per_bag) catch unreachable; + const bags_required = @divCeil(hints.count + additional_count, hints_per_bag); return hints.bags.ensureUnusedCapacity(gpa_inner, bags_required); } fn appendAssumeCapacity(hints: *@This(), hint: std.lang.BranchHint) void { @@ -10321,7 +10321,7 @@ fn finishSwitchBr( } }; var branch_hints: BranchHints = hints: { - const num_bags = std.math.divCeil(u32, estimated_cases_len, BranchHints.hints_per_bag) catch unreachable; + const num_bags = @divCeil(estimated_cases_len, BranchHints.hints_per_bag); break :hints .{ .bags = try .initCapacity(gpa, num_bags), .count = 0 }; }; defer branch_hints.bags.deinit(gpa); @@ -12212,7 +12212,7 @@ fn analyzeSwitchPayloadCaptureTaggedUnion( { // All branch hints are `.none`, so just add zero elems. comptime assert(@intFromEnum(std.lang.BranchHint.none) == 0); - const need_elems = std.math.divCeil(usize, field_indices.len + 1, 10) catch unreachable; + const need_elems = @divCeil(field_indices.len + 1, 10); try cases_extra.appendNTimes(gpa, 0, need_elems); } @@ -18698,7 +18698,7 @@ fn finishStructInit( return sema.addConstantMaybeRef(sema.resolveValue(final_val_ref).?, is_ref); }, .@"packed" => { - const buf = try sema.arena.alloc(u8, @intCast((struct_ty.bitSize(zcu) + 7) / 8)); + const buf = try sema.arena.alloc(u8, @intCast(@divCeil(struct_ty.bitSize(zcu), 8))); @memset(buf, 0); var bit_offset: u16 = 0; for (field_inits) |field_init| { @@ -29745,7 +29745,7 @@ pub fn bitCastVal( if (val.isUndef(zcu)) { return pt.undefValue(dest_ty); } else { - const buf = try sema.arena.alloc(u8, @intCast((bit_size + 7) / 8)); + const buf = try sema.arena.alloc(u8, @intCast(@divCeil(bit_size, 8))); @memset(buf, 0); val.writeToPackedMemory(zcu, buf, 0); return .readFromPackedMemory(dest_ty, pt, buf, 0); diff --git a/src/Sema/arith.zig b/src/Sema/arith.zig index 3759b65971ea88381e5cd98c2d3398408caf553d..570cd3e533c5ffedae974f4198aedeee1e2268d7 100644 --- a/src/Sema/arith.zig +++ b/src/Sema/arith.zig @@ -2193,12 +2193,12 @@ fn floatDivCeil(sema: *Sema, lhs: Value, rhs: Value, ty: Type) !Value { const pt = sema.pt; const zcu = pt.zcu; const target = zcu.getTarget(); - const storage: InternPool.Key.Float.Storage = switch (ty.floatBits(target)) { // TODO - 16 => .{ .f16 = @ceil(lhs.toFloat(f16, zcu) / rhs.toFloat(f16, zcu)) }, - 32 => .{ .f32 = @ceil(lhs.toFloat(f32, zcu) / rhs.toFloat(f32, zcu)) }, - 64 => .{ .f64 = @ceil(lhs.toFloat(f64, zcu) / rhs.toFloat(f64, zcu)) }, - 80 => .{ .f80 = @ceil(lhs.toFloat(f80, zcu) / rhs.toFloat(f80, zcu)) }, - 128 => .{ .f128 = @ceil(lhs.toFloat(f128, zcu) / rhs.toFloat(f128, zcu)) }, + const storage: InternPool.Key.Float.Storage = switch (ty.floatBits(target)) { + 16 => .{ .f16 = @divCeil(lhs.toFloat(f16, zcu), rhs.toFloat(f16, zcu)) }, + 32 => .{ .f32 = @divCeil(lhs.toFloat(f32, zcu), rhs.toFloat(f32, zcu)) }, + 64 => .{ .f64 = @divCeil(lhs.toFloat(f64, zcu), rhs.toFloat(f64, zcu)) }, + 80 => .{ .f80 = @divCeil(lhs.toFloat(f80, zcu), rhs.toFloat(f80, zcu)) }, + 128 => .{ .f128 = @divCeil(lhs.toFloat(f128, zcu), rhs.toFloat(f128, zcu)) }, else => unreachable, }; return .fromInterned(try pt.intern(.{ .float = .{ @@ -2304,7 +2304,7 @@ fn intValueAa(sema: *Sema, ty: Type) !Value { if (ty.toIntern() == .u0_type) return pt.intValue(ty, 0); const info = ty.intInfo(zcu); - const buf = try sema.arena.alloc(u8, (info.bits + 7) / 8); + const buf = try sema.arena.alloc(u8, @divCeil(info.bits, 8)); @memset(buf, 0xAA); const limbs = try sema.arena.alloc( diff --git a/src/Type.zig b/src/Type.zig index 0e54f7c51f36c9a88558c792b7fed439929f68c7..86f86655143303c00b2eae4b62faed424bef459a 100644 --- a/src/Type.zig +++ b/src/Type.zig @@ -968,7 +968,7 @@ pub fn abiAlignment(ty: Type, zcu: *const Zcu) Alignment { if (vector_type.len > 256 and target.cpu.has(.x86, .avx512f)) return .@"64"; if (vector_type.len > 128 and target.cpu.has(.x86, .avx)) return .@"32"; if (vector_type.len > 64) return .@"16"; - const bytes = std.math.divCeil(u32, vector_type.len, 8) catch unreachable; + const bytes = @divCeil(vector_type.len, 8); return .fromByteUnits(std.math.ceilPowerOfTwoAssert(u32, bytes)); } const elem_bytes: u32 = @intCast(Type.fromInterned(vector_type.child).abiSize(zcu)); @@ -1111,10 +1111,10 @@ pub fn abiSize(ty: Type, zcu: *const Zcu) u64 { .vector_type => |vec| { const elem_ty: Type = .fromInterned(vec.child); const bytes = switch (zcu.comp.getZigBackend()) { - else => std.math.divCeil(u64, vec.len * elem_ty.bitSize(zcu), 8) catch unreachable, + else => @divCeil(vec.len * elem_ty.bitSize(zcu), 8), .stage2_c, .stage2_wasm => vec.len * elem_ty.abiSize(zcu), .stage2_x86_64 => switch (elem_ty.toIntern()) { - .bool_type => std.math.divCeil(u64, vec.len, 8) catch unreachable, + .bool_type => @divCeil(vec.len, 8), else => vec.len * elem_ty.abiSize(zcu), }, }; diff --git a/src/codegen/aarch64/Select.zig b/src/codegen/aarch64/Select.zig index 13a3823d86b13c5e8ca56bac16ec961962dafbff..b74c7fe9ec580071a887498cd8ab0ef04e287257 100644 --- a/src/codegen/aarch64/Select.zig +++ b/src/codegen/aarch64/Select.zig @@ -405,11 +405,11 @@ pub fn analyze(isel: *Select, air_body: []const Air.Inst.Index) !void { .live_registers = undefined, .repeat_list = undefined, }); - try isel.dom.appendNTimes(gpa, 0, std.math.divCeil(usize, isel.dom_len, @bitSizeOf(DomInt)) catch unreachable); + try isel.dom.appendNTimes(gpa, 0, @divCeil(isel.dom_len, @bitSizeOf(DomInt))); try isel.analyze(air_body_block.body); for ( isel.dom.items[initial_dom_start..].ptr, - isel.dom.items[isel.dom_start..][0 .. std.math.divCeil(usize, initial_dom_len, @bitSizeOf(DomInt)) catch unreachable], + isel.dom.items[isel.dom_start..][0..@divCeil(initial_dom_len, @bitSizeOf(DomInt))], ) |*initial_dom, loop_dom| initial_dom.* |= loop_dom; isel.dom_start = initial_dom_start; isel.dom_len = initial_dom_len; @@ -591,7 +591,7 @@ pub fn analyze(isel: *Select, air_body: []const Air.Inst.Index) !void { .live_registers = undefined, .repeat_list = undefined, }); - try isel.dom.appendNTimes(gpa, 0, std.math.divCeil(usize, isel.dom_len, @bitSizeOf(DomInt)) catch unreachable); + try isel.dom.appendNTimes(gpa, 0, @divCeil(isel.dom_len, @bitSizeOf(DomInt))); var cases_it = switch_br.iterateCases(); while (cases_it.next()) |case| try isel.analyze(case.body); @@ -599,7 +599,7 @@ pub fn analyze(isel: *Select, air_body: []const Air.Inst.Index) !void { for ( isel.dom.items[initial_dom_start..].ptr, - isel.dom.items[isel.dom_start..][0 .. std.math.divCeil(usize, initial_dom_len, @bitSizeOf(DomInt)) catch unreachable], + isel.dom.items[isel.dom_start..][0..@divCeil(initial_dom_len, @bitSizeOf(DomInt))], ) |*initial_dom, loop_dom| initial_dom.* |= loop_dom; isel.dom_start = initial_dom_start; isel.dom_len = initial_dom_len; @@ -10196,7 +10196,7 @@ pub const Value = struct { 0 => unreachable, 1...64 => unreachable, 65...256 => |bits| if (offset == 0 and size == ty_size) { - const parts_len = std.math.divCeil(u16, bits, 64) catch unreachable; + const parts_len = @divCeil(bits, 64); vi.setParts(isel, @intCast(parts_len)); for (0..parts_len) |part_index| _ = vi.addPart(isel, 8 * part_index, 8); }, @@ -10240,7 +10240,7 @@ pub const Value = struct { const min_part_log2_stride: u5 = if (size > 16) 4 else if (size > 8) 3 else 0; const array_len = array_type.lenIncludingSentinel(); if (array_len > Value.max_parts and - (std.math.divCeil(u64, size, @as(u64, 1) << min_part_log2_stride) catch unreachable) > Value.max_parts) + (@divCeil(size, @as(u64, 1) << min_part_log2_stride)) > Value.max_parts) return isel.fail("Value.FieldPartIterator.next({f})", .{isel.fmtType(ty)}); const alignment = vi.alignment(isel); const Part = struct { offset: u64, size: u64 }; @@ -10290,7 +10290,7 @@ pub const Value = struct { .anyframe_type => unreachable, .error_union_type => |error_union_type| { const min_part_log2_stride: u5 = if (size > 16) 4 else if (size > 8) 3 else 0; - if ((std.math.divCeil(u64, size, @as(u64, 1) << min_part_log2_stride) catch unreachable) > Value.max_parts) + if ((@divCeil(size, @as(u64, 1) << min_part_log2_stride)) > Value.max_parts) return isel.fail("Value.FieldPartIterator.next({f})", .{isel.fmtType(ty)}); const alignment = vi.alignment(isel); const payload_ty: ZigType = .fromInterned(error_union_type.payload_type); @@ -10397,7 +10397,7 @@ pub const Value = struct { } const min_part_log2_stride: u5 = if (size > 16) 4 else if (size > 8) 3 else 0; if (loaded_struct.field_types.len > Value.max_parts and - (std.math.divCeil(u64, size, @as(u64, 1) << min_part_log2_stride) catch unreachable) > Value.max_parts) + (@divCeil(size, @as(u64, 1) << min_part_log2_stride)) > Value.max_parts) return isel.fail("Value.FieldPartIterator.next({f})", .{isel.fmtType(ty)}); const alignment = vi.alignment(isel); const Part = struct { offset: u64, size: u64, signedness: ?std.lang.Signedness, is_vector: bool }; @@ -10458,7 +10458,7 @@ pub const Value = struct { .tuple_type => |tuple_type| { const min_part_log2_stride: u5 = if (size > 16) 4 else if (size > 8) 3 else 0; if (tuple_type.types.len > Value.max_parts and - (std.math.divCeil(u64, size, @as(u64, 1) << min_part_log2_stride) catch unreachable) > Value.max_parts) + (@divCeil(size, @as(u64, 1) << min_part_log2_stride)) > Value.max_parts) return isel.fail("Value.FieldPartIterator.next({f})", .{isel.fmtType(ty)}); const alignment = vi.alignment(isel); const Part = struct { offset: u64, size: u64, is_vector: bool }; @@ -10513,7 +10513,7 @@ pub const Value = struct { } }, } const min_part_log2_stride: u5 = if (size > 16) 4 else if (size > 8) 3 else 0; - if ((std.math.divCeil(u64, size, @as(u64, 1) << min_part_log2_stride) catch unreachable) > Value.max_parts) + if ((@divCeil(size, @as(u64, 1) << min_part_log2_stride)) > Value.max_parts) return isel.fail("Value.FieldPartIterator.next({f})", .{isel.fmtType(ty)}); const union_layout = ZigType.getUnionLayout(loaded_union, zcu); const alignment = vi.alignment(isel); diff --git a/src/codegen/llvm/FuncGen.zig b/src/codegen/llvm/FuncGen.zig index cac82b6de31150a262e32b0b5c0e0c142270d416..602277a91188d72994ac83b025ecf5c580f5ce2b 100644 --- a/src/codegen/llvm/FuncGen.zig +++ b/src/codegen/llvm/FuncGen.zig @@ -6948,7 +6948,7 @@ const ParamTypeIterator = struct { switch (ip.indexToKey(ty.toIntern())) { .struct_type => { const size = ty.abiSize(zcu); - assert((std.math.divCeil(u64, size, 8) catch unreachable) == types_index); + assert(@divCeil(size, 8) == types_index); if (size % 8 > 0) { it.types_buffer[types_index - 1] = try it.object.builder.intType(@intCast(size % 8 * 8)); @@ -7193,7 +7193,7 @@ fn lowerSystemVFnRetTy(o: *Object, fn_info: InternPool.Key.FuncType) Allocator.E switch (ip.indexToKey(ret_ty.toIntern())) { .struct_type => { const size = ret_ty.abiSize(zcu); - assert((std.math.divCeil(u64, size, 8) catch unreachable) == types_index); + assert(@divCeil(size, 8) == types_index); if (size % 8 > 0) { types_buffer[types_index - 1] = try o.builder.intType(@intCast(size % 8 * 8)); } diff --git a/src/codegen/riscv64/CodeGen.zig b/src/codegen/riscv64/CodeGen.zig index 986e326ec9f62b76aa29c62b99bd08247451b19b..b11b898556c0de6479e0aeaf2fe25d47d31e8445 100644 --- a/src/codegen/riscv64/CodeGen.zig +++ b/src/codegen/riscv64/CodeGen.zig @@ -2217,8 +2217,7 @@ fn airIntCast(func: *Func, inst: Air.Inst.Index) !void { }; const dst_mcv = if (dst_int_info.bits <= src_storage_bits and - math.divCeil(u16, dst_int_info.bits, 64) catch unreachable == - math.divCeil(u32, src_storage_bits, 64) catch unreachable and + @divCeil(dst_int_info.bits, 64) == @divCeil(src_storage_bits, 64) and func.reuseOperand(inst, ty_op.operand, 0, src_mcv)) src_mcv else dst: { const dst_mcv = try func.allocRegOrMem(dst_ty, inst, true); try func.genCopy(min_ty, dst_mcv, src_mcv); diff --git a/src/codegen/spirv/Assembler.zig b/src/codegen/spirv/Assembler.zig index f18f9028212b4916ed70a89d080e28a3bad75f3f..e748f4789b0325f2a4d0309d0fcad4ea3b66771f 100644 --- a/src/codegen/spirv/Assembler.zig +++ b/src/codegen/spirv/Assembler.zig @@ -375,7 +375,7 @@ fn processGenericInstruction(ass: *Assembler) !?AsmValue { }, .string => |offset| { const text = std.mem.sliceTo(ass.inst.string_bytes.items[offset..], 0); - const size = std.math.divCeil(usize, text.len + 1, @sizeOf(Word)) catch unreachable; + const size = @divCeil(text.len + 1, @sizeOf(Word)); try section.ensureUnusedCapacity(cg.gpa, size); section.writeOperand(spec.LiteralString, text); }, diff --git a/src/codegen/spirv/Section.zig b/src/codegen/spirv/Section.zig index c3194a5456370a24f9b9e850e6f5753c1333f332..db338f77db57347d662a20d4c525f61f1b2c18ab 100644 --- a/src/codegen/spirv/Section.zig +++ b/src/codegen/spirv/Section.zig @@ -232,7 +232,7 @@ fn operandSize(comptime Operand: type, operand: Operand) usize { return switch (Operand) { spec.LiteralSpecConstantOpInteger => unreachable, spec.Id, spec.LiteralInteger, spec.LiteralExtInstInteger => 1, - spec.LiteralString => std.math.divCeil(usize, operand.len + 1, @sizeOf(Word)) catch unreachable, + spec.LiteralString => @divCeil(operand.len + 1, @sizeOf(Word)), spec.LiteralContextDependentNumber => switch (operand) { .int32, .uint32, .float32 => 1, .int64, .uint64, .float64 => 2, diff --git a/src/codegen/wasm/CodeGen.zig b/src/codegen/wasm/CodeGen.zig index 75e92651639207755382f03379d4bd90fec1206b..6d42d8d1ff69c9f5270106b8c9c311de3f309586 100644 --- a/src/codegen/wasm/CodeGen.zig +++ b/src/codegen/wasm/CodeGen.zig @@ -3678,7 +3678,7 @@ fn intWrap(cg: *CodeGen, ty: IntType, operand: WValue) InnerError!WValue { const result = try cg.allocInt(ty); - const used_len = (math.divCeil(u16, ty.bits, 64) catch unreachable) * 8; + const used_len = @divCeil(ty.bits, 64) * 8; if (ty.bits % 64 != 0) { try cg.memcpy(result, operand, .{ .imm32 = used_len - 8 }); @@ -3744,7 +3744,7 @@ fn intMaxValue(cg: *CodeGen, int_ty: IntType) InnerError!WValue { } else { const result = try cg.allocInt(int_ty); const full_len = @divExact(cg.intBackingBits(int_ty.bits), 8); - const used_len = (math.divCeil(u16, int_ty.bits, 64) catch unreachable) * 8; + const used_len = @divCeil(int_ty.bits, 64) * 8; try cg.memset(Type.u8, result, .{ .imm32 = used_len - 8 }, .{ .imm32 = 0xFF }); @@ -3778,7 +3778,7 @@ fn intMinValue(cg: *CodeGen, int_ty: IntType) InnerError!WValue { } else { const result = try cg.allocInt(int_ty); const full_len = @divExact(cg.intBackingBits(int_ty.bits), 8); - const used_len = (math.divCeil(u16, int_ty.bits, 64) catch unreachable) * 8; + const used_len = @divCeil(int_ty.bits, 64) * 8; try cg.memset(Type.u8, result, .{ .imm32 = used_len - 8 }, .{ .imm32 = 0 }); try cg.store(result, .{ .imm64 = ~@as(u64, 0) << @intCast(int_ty.bits - (used_len - 8) * 8 - 1) }, Type.u64, used_len - 8); diff --git a/src/codegen/x86_64/CodeGen.zig b/src/codegen/x86_64/CodeGen.zig index 9975fa4d87e0c248bd67a6bd15a8d9d9b0faed59..dbb942eaed207109e57a2f5a39bf7d5d4f21c0d7 100644 --- a/src/codegen/x86_64/CodeGen.zig +++ b/src/codegen/x86_64/CodeGen.zig @@ -174786,7 +174786,7 @@ fn genShiftBinOpMir( try self.spillEflagsIfOccupied(); if (abi_size > 16) { - const limbs_len = std.math.divCeil(u32, abi_size, 8) catch unreachable; + const limbs_len = @divCeil(abi_size, 8); assert(shift_abi_size >= 1 and shift_abi_size <= 2); const rcx_lock: ?RegisterLock = switch (rhs_mcv) { @@ -179598,7 +179598,7 @@ fn genSetReg( if (pack_alias != sign_alias) try cg.asmRegisterRegister(.{ ._dqa, .mov }, pack_alias, sign_alias); try cg.asmRegisterRegister(.{ .p_b, .ackssw }, pack_alias, pack_alias); } - mask_size = std.math.divCeil(u32, mask_size, 2) catch unreachable; + mask_size = @divCeil(mask_size, 2); break :pack_reg pack_reg; }, }; @@ -180162,7 +180162,7 @@ fn airBitCast(self: *CodeGen, inst: Air.Inst.Index) !void { const bit_size = dst_ty.bitSize(zcu); if (abi_size * 8 <= bit_size) break :result dst_mcv; - const dst_limbs_len = std.math.divCeil(u31, @intCast(bit_size), 64) catch unreachable; + const dst_limbs_len: u31 = @intCast(@divCeil(bit_size, 64)); const high_mcv: MCValue = switch (dst_mcv) { .register => |dst_reg| .{ .register = dst_reg }, .register_pair => |dst_regs| .{ .register = dst_regs[1] }, @@ -183555,7 +183555,7 @@ const Temp = struct { const part_ty: Type = if (src_regs.len == 1) src_ty else if (cg.intInfo(src_ty)) |int_info| part_ty: { - assert(src_regs.len == std.math.divCeil(u16, int_info.bits, 64) catch unreachable); + assert(src_regs.len == @divCeil(int_info.bits, 64)); break :part_ty .u64; } else part_ty: switch (ip.indexToKey(src_ty.toIntern())) { else => std.debug.panic("{s}: {f}\n", .{ @src().fn_name, src_ty.fmt(cg.pt) }), @@ -183565,7 +183565,7 @@ const Temp = struct { break :part_ty .usize; }, .array_type => { - assert(src_regs.len - part_index == std.math.divCeil(u32, src_size, 8) catch unreachable); + assert(src_regs.len - part_index == @divCeil(src_size, 8)); break :part_ty try cg.pt.intType(.unsigned, @as(u16, 8) * @min(src_size, 8)); }, .vector_type => |vector_type| switch (@divExact(vector_type.len, src_regs.len)) { @@ -183585,7 +183585,7 @@ const Temp = struct { }, }, .struct_type, .union_type => { - assert(src_regs.len - part_index == std.math.divCeil(u32, src_size, 8) catch unreachable); + assert(src_regs.len - part_index == @divCeil(src_size, 8)); break :part_ty switch (src_size) { 0, 3, 5...7 => unreachable, 1 => .u8, diff --git a/src/codegen/x86_64/Emit.zig b/src/codegen/x86_64/Emit.zig index 1e8e60ffb665fc70709a5291040a32a1bebcb5af..d5ec79ce22a8f650992ae77567b3d9f303dd2b82 100644 --- a/src/codegen/x86_64/Emit.zig +++ b/src/codegen/x86_64/Emit.zig @@ -772,7 +772,7 @@ fn encodeInst(emit: *Emit, lowered_inst: Instruction, reloc_info: []const RelocI const enc_length: u4 = if (is_mem) switch (lowered_inst.ops[op_index].mem.sib.base) { .rip_inst => 4, else => unreachable, - } else @intCast(std.math.divCeil(u7, @intCast(op.immBitSize()), 8) catch unreachable); + } else @intCast(@divCeil(op.immBitSize(), 8)); reloc_offset -= enc_length; if (op_index == reloc.op_index) break :reloc_offset_length .{ reloc_offset, enc_length }; assert(!is_mem); diff --git a/src/link/Dwarf.zig b/src/link/Dwarf.zig index d51c59ed23941283b2de8258db0ad865adf8aa33..b6ff6c754bc97b0efc78522b30dcf302d9ad072d 100644 --- a/src/link/Dwarf.zig +++ b/src/link/Dwarf.zig @@ -2137,7 +2137,7 @@ pub const WipNav = struct { .signed => DW.FORM.sdata, .unsigned => DW.FORM.udata, })); - try wip_nav.debug_info.ensureUnusedCapacity(std.math.divCeil(usize, bits, 7) catch unreachable); + try wip_nav.debug_info.ensureUnusedCapacity(@divCeil(bits, 7)); var bit: usize = 0; var carry: u1 = 1; while (bit < bits) { @@ -2158,7 +2158,7 @@ pub const WipNav = struct { } } else { try diw.writeUleb128(DW.FORM.block); - const bytes = @max(ty.abiSize(zcu), std.math.divCeil(usize, bits, 8) catch unreachable); + const bytes = @max(ty.abiSize(zcu), @divCeil(bits, 8)); try diw.writeUleb128(bytes); try wip_nav.debug_info.ensureUnusedCapacity(@intCast(bytes)); big_int.writeTwosComplement( @@ -4275,7 +4275,7 @@ fn updateConstInner(dwarf: *Dwarf, pt: Zcu.PerThread, debug_const_index: link.Co try wip_nav.abbrevCode(.aggregate_undefined_comptime_value); try wip_nav.refType(.fromInterned(error_union.ty)); var err_buf: [4]u8 = undefined; - const err_bytes = err_buf[0 .. std.math.divCeil(u17, zcu.errorSetBits(), 8) catch unreachable]; + const err_bytes = err_buf[0..@divCeil(zcu.errorSetBits(), 8)]; dwarf.writeInt(err_bytes, switch (error_union.val) { .err_name => |err_name| try pt.getErrorValue(err_name), .payload => 0, -- 2.54.0