| author |  Alex Rønne Petersen <alex@alexrp.com> 2026-10-20 02:19:10+02:00 |
| committer | Alex Rønne Petersen <alex@alexrp.com> 2026-10-20 03:29:36+02:00 |
| log | 77178704d1b1bfc8ce2b7262cba8bb9c462e36a8 |
| tree | 82407d1fd8f442317c2462657569a170bd60b313 |
| parent | 0f09c3c55a2db5b05a38ea431d0b312320a7f178 |
| signature | Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM |
update_cpu_features: add some missing wasm feature dependencies
2 files changed, 13 insertions(+), 2 deletions(-)
lib
std
Target
lib/std/Target/wasm.zig+4-1
| ... | @@ -114,6 +114,7 @@ pub const all_features = blk: { | ... | @@ -114,6 +114,7 @@ pub const all_features = blk: { |
| 114 | .llvm_name = "reference-types", | 114 | .llvm_name = "reference-types", |
| 115 | .description = "Enable reference types", | 115 | .description = "Enable reference types", |
| 116 | .dependencies = featureSet(&[_]Feature{ | 116 | .dependencies = featureSet(&[_]Feature{ |
| 117 | .bulk_memory, | ||
| 117 | .call_indirect_overlong, | 118 | .call_indirect_overlong, |
| 118 | }), | 119 | }), |
| 119 | }; | 120 | }; |
| ... | @@ -125,7 +126,9 @@ pub const all_features = blk: { | ... | @@ -125,7 +126,9 @@ pub const all_features = blk: { |
| 125 | result[@backingInt(Feature.relaxed_simd)] = .{ | 126 | result[@backingInt(Feature.relaxed_simd)] = .{ |
| 126 | .llvm_name = "relaxed-simd", | 127 | .llvm_name = "relaxed-simd", |
| 127 | .description = "Enable relaxed-simd instructions", | 128 | .description = "Enable relaxed-simd instructions", |
| 128 | .dependencies = featureSet(&[_]Feature{}), | 129 | .dependencies = featureSet(&[_]Feature{ |
| 130 | .simd128, | ||
| 131 | }), | ||
| 129 | }; | 132 | }; |
| 130 | result[@backingInt(Feature.sign_ext)] = .{ | 133 | result[@backingInt(Feature.sign_ext)] = .{ |
| 131 | .llvm_name = "sign-ext", | 134 | .llvm_name = "sign-ext", |
tools/update_cpu_features.zig+9-1
| ... | @@ -1751,9 +1751,17 @@ const targets = [_]ArchTarget{ | ... | @@ -1751,9 +1751,17 @@ const targets = [_]ArchTarget{ |
| 1751 | .llvm_name = "bulk-memory", | 1751 | .llvm_name = "bulk-memory", |
| 1752 | .extra_deps = &.{"bulk_memory_opt"}, | 1752 | .extra_deps = &.{"bulk_memory_opt"}, |
| 1753 | }, | 1753 | }, |
| 1754 | .{ | ||
| 1755 | .llvm_name = "f16", | ||
| 1756 | .extra_deps = &.{"simd128"}, | ||
| 1757 | }, | ||
| 1754 | .{ | 1758 | .{ |
| 1755 | .llvm_name = "reference-types", | 1759 | .llvm_name = "reference-types", |
| 1756 | .extra_deps = &.{"call_indirect_overlong"}, | 1760 | .extra_deps = &.{ "bulk_memory", "call_indirect_overlong" }, |
| 1761 | }, | ||
| 1762 | .{ | ||
| 1763 | .llvm_name = "relaxed-simd", | ||
| 1764 | .extra_deps = &.{"simd128"}, | ||
| 1757 | }, | 1765 | }, |
| 1758 | }, | 1766 | }, |
| 1759 | .extra_features = &.{ | 1767 | .extra_features = &.{ |