| author | |
| committer | |
| log | 8647e4d3110dd269f6c377ecd8315a19e094758a |
| tree | 811e663e72965826d3cfe3e812db210b7dcbf4fe |
| parent | cbfa87cbea0274e1e88d6a61bba82a2099e19fd6 |
4 files changed, 10 insertions(+), 23 deletions(-)
lib/std/Io/Writer.zig-4| ... | ... | @@ -2282,10 +2282,6 @@ pub const Discarding = struct { |
| 2282 | 2282 | |
| 2283 | 2283 | pub fn sendFile(w: *Writer, file_reader: *File.Reader, limit: Limit) FileError!usize { |
| 2284 | 2284 | if (File.Handle == void) return error.Unimplemented; |
| 2285 | switch (builtin.zig_backend) { | |
| 2286 | else => {}, | |
| 2287 | .stage2_aarch64 => return error.Unimplemented, | |
| 2288 | } | |
| 2289 | 2285 | const d: *Discarding = @alignCast(@fieldParentPtr("writer", w)); |
| 2290 | 2286 | d.count += w.end; |
| 2291 | 2287 | w.end = 0; |
lib/std/Progress.zig-1| ... | ... | @@ -427,7 +427,6 @@ const noop_impl = builtin.single_threaded or switch (builtin.os.tag) { |
| 427 | 427 | .wasi, .freestanding => true, |
| 428 | 428 | else => false, |
| 429 | 429 | } or switch (builtin.zig_backend) { |
| 430 | .stage2_aarch64 => true, | |
| 431 | 430 | else => false, |
| 432 | 431 | }; |
| 433 | 432 |
lib/std/fs/File.zig+1-4| ... | ... | @@ -739,10 +739,7 @@ pub const Writer = struct { |
| 739 | 739 | return .{ |
| 740 | 740 | .vtable = &.{ |
| 741 | 741 | .drain = drain, |
| 742 | .sendFile = switch (builtin.zig_backend) { | |
| 743 | else => sendFile, | |
| 744 | .stage2_aarch64 => Io.Writer.unimplementedSendFile, | |
| 745 | }, | |
| 742 | .sendFile = sendFile, | |
| 746 | 743 | }, |
| 747 | 744 | .buffer = buffer, |
| 748 | 745 | }; |
src/codegen/aarch64/Select.zig+9-14| ... | ... | @@ -9570,11 +9570,15 @@ pub const Value = struct { |
| 9570 | 9570 | .zr |
| 9571 | 9571 | else |
| 9572 | 9572 | return false; |
| 9573 | if (part_ra != .zr) { | |
| 9574 | const live_vi = isel.live_registers.getPtr(part_ra); | |
| 9575 | assert(live_vi.* == .free); | |
| 9576 | live_vi.* = .allocating; | |
| 9577 | } | |
| 9573 | const part_lock: RegLock = switch (part_ra) { | |
| 9574 | else => isel.lockReg(part_ra), | |
| 9575 | .zr => .empty, | |
| 9576 | }; | |
| 9577 | defer switch (opts.expected_live_registers.get(part_ra)) { | |
| 9578 | _ => {}, | |
| 9579 | .allocating => unreachable, | |
| 9580 | .free => part_lock.unlock(isel), | |
| 9581 | }; | |
| 9578 | 9582 | if (opts.wrap) |int_info| switch (int_info.bits) { |
| 9579 | 9583 | else => unreachable, |
| 9580 | 9584 | 1...7, 9...15, 17...31 => |bits| try isel.emit(switch (int_info.signedness) { |
| ... | ... | @@ -9605,15 +9609,6 @@ pub const Value = struct { |
| 9605 | 9609 | 64 => {}, |
| 9606 | 9610 | }; |
| 9607 | 9611 | try isel.loadReg(part_ra, part_size, part_vi.signedness(isel), base_ra, opts.offset); |
| 9608 | if (part_ra != .zr) { | |
| 9609 | const live_vi = isel.live_registers.getPtr(part_ra); | |
| 9610 | assert(live_vi.* == .allocating); | |
| 9611 | switch (opts.expected_live_registers.get(part_ra)) { | |
| 9612 | _ => {}, | |
| 9613 | .allocating => unreachable, | |
| 9614 | .free => live_vi.* = .free, | |
| 9615 | } | |
| 9616 | } | |
| 9617 | 9612 | return true; |
| 9618 | 9613 | } |
| 9619 | 9614 | var used = false; |