Commit 8b3f7d2ad8953009ecb983dfb466ce3995a4cb38 | zig

author	Koakuma <koachan@protonmail.com> 2022-06-12 23:24:04+07:00
committer	Koakuma <koachan@protonmail.com> 2022-06-24 21:08:40+07:00
log	8b3f7d2ad8953009ecb983dfb466ce3995a4cb38
tree	772194365c6ddbc4212b2554378184ad40db7abc
parent	7c87f9c828282aa12fb2d77c9c6a2318d83b8dff

stage2: sparc64: Merge the compare_flag structs into condition_flags

This follows the design in the aarch64 backend (commit
61844b6bd405b4cca3ab673284609aa6a651d506).

2 files changed, 77 insertions(+), 116 deletions(-)

src
- arch
  - sparc64
    CodeGen.zig
    bits.zig

src/arch/sparc64/CodeGen.zig+53-109

 @@ -93,8 +93,8 @@ register_manager: RegisterManager = .{},
 /// Maps offset to what is stored there.
 stack: std.AutoHashMapUnmanaged(u32, StackAllocation) = .{},
-/// Tracks the current instruction allocated to the compare flags
+/// Tracks the current instruction allocated to the condition flags
-compare_flags_inst: ?Air.Inst.Index = null,
+condition_flags_inst: ?Air.Inst.Index = null,
 /// Offset from the stack base, representing the end of the stack frame.
 max_end_stack: u32 = 0,
 @@ -141,16 +141,11 @@ const MCValue = union(enum) {
     stack_offset: u32,
     /// The value is a pointer to one of the stack variables (payload is stack offset).
     ptr_stack_offset: u32,
-    /// The value is in the specified CCR assuming an unsigned operation,
+    /// The value is in the specified CCR. The value is 1 (if
-    /// with the operator applied on top of it.
+    /// the type is u1) or true (if the type in bool) iff the
-    compare_flags_unsigned: struct {
+    /// specified condition is true.
-        cmp: math.CompareOperator,
+    condition_flags: struct {
-        ccr: Instruction.CCR,
+        cond: Instruction.Condition,
-    },
-    /// The value is in the specified CCR assuming an signed operation,
-    /// with the operator applied on top of it.
-    compare_flags_signed: struct {
-        cmp: math.CompareOperator,
         ccr: Instruction.CCR,
     },
 @@ -738,8 +733,8 @@ fn airAddSubWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
                             else => unreachable,
                         };
-                        try self.spillCompareFlagsIfOccupied();
+                        try self.spillConditionFlagsIfOccupied();
-                        self.compare_flags_inst = inst;
+                        self.condition_flags_inst = inst;
                         const dest = blk: {
                             if (rhs_immediate_ok) {
 @@ -1072,7 +1067,7 @@ fn airCall(self: *Self, inst: Air.Inst.Index, modifier: std.builtin.CallOptions.
     // CCR is volatile across function calls
     // (SCD 2.4.1, page 3P-10)
-    try self.spillCompareFlagsIfOccupied();
+    try self.spillConditionFlagsIfOccupied();
     for (info.args) |mc_arg, arg_i| {
         const arg = args[arg_i];
 @@ -1208,12 +1203,18 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
                 .inst = inst,
             });
-            try self.spillCompareFlagsIfOccupied();
+            try self.spillConditionFlagsIfOccupied();
-            self.compare_flags_inst = inst;
+            self.condition_flags_inst = inst;
             break :result switch (int_info.signedness) {
-                .signed => MCValue{ .compare_flags_signed = .{ .cmp = op, .ccr = .xcc } },
+                .signed => MCValue{ .condition_flags = .{
-                .unsigned => MCValue{ .compare_flags_unsigned = .{ .cmp = op, .ccr = .xcc } },
+                    .cond = .{ .icond = Instruction.ICondition.fromCompareOperatorSigned(op) },
+                    .ccr = .xcc,
+                } },
+                .unsigned => MCValue{ .condition_flags = .{
+                    .cond = .{ .icond = Instruction.ICondition.fromCompareOperatorUnsigned(op) },
+                    .ccr = .xcc,
+                } },
             };
         } else {
             return self.fail("TODO SPARCv9 cmp for ints > 64 bits", .{});
 @@ -1224,7 +1225,7 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
 fn airCondBr(self: *Self, inst: Air.Inst.Index) !void {
     const pl_op = self.air.instructions.items(.data)[inst].pl_op;
-    const cond = try self.resolveInst(pl_op.operand);
+    const condition = try self.resolveInst(pl_op.operand);
     const extra = self.air.extraData(Air.CondBr, pl_op.payload);
     const then_body = self.air.extra[extra.end..][0..extra.data.then_body_len];
     const else_body = self.air.extra[extra.end + then_body.len ..][0..extra.data.else_body_len];
 @@ -1232,39 +1233,22 @@ fn airCondBr(self: *Self, inst: Air.Inst.Index) !void {
     // Here we either emit a BPcc for branching on CCR content,
     // or emit a BPr to branch on register content.
-    const reloc: Mir.Inst.Index = switch (cond) {
+    const reloc: Mir.Inst.Index = switch (condition) {
-        .compare_flags_signed,
+        .condition_flags => |flags| try self.addInst(.{
-        .compare_flags_unsigned,
-        => try self.addInst(.{
             .tag = .bpcc,
             .data = .{
                 .branch_predict_int = .{
-                    .ccr = switch (cond) {
+                    .ccr = flags.ccr,
-                        .compare_flags_signed => |cmp_op| cmp_op.ccr,
+                    // Here we map to the opposite condition because the jump is to the false branch.
-                        .compare_flags_unsigned => |cmp_op| cmp_op.ccr,
+                    .cond = flags.cond.icond.negate(),
-                        else => unreachable,
-                    },
-                    .cond = switch (cond) {
-                        .compare_flags_signed => |cmp_op| blk: {
-                            // Here we map to the opposite condition because the jump is to the false branch.
-                            const condition = Instruction.ICondition.fromCompareOperatorSigned(cmp_op.cmp);
-                            break :blk condition.negate();
-                        },
-                        .compare_flags_unsigned => |cmp_op| blk: {
-                            // Here we map to the opposite condition because the jump is to the false branch.
-                            const condition = Instruction.ICondition.fromCompareOperatorUnsigned(cmp_op.cmp);
-                            break :blk condition.negate();
-                        },
-                        else => unreachable,
-                    },
                     .inst = undefined, // Will be filled by performReloc
                 },
             },
         }),
         else => blk: {
-            const reg = switch (cond) {
+            const reg = switch (condition) {
                 .register => |r| r,
-                else => try self.copyToTmpRegister(Type.bool, cond),
+                else => try self.copyToTmpRegister(Type.bool, condition),
             };
             break :blk try self.addInst(.{
 @@ -1305,7 +1289,7 @@ fn airCondBr(self: *Self, inst: Air.Inst.Index) !void {
     var parent_stack = try self.stack.clone(self.gpa);
     defer parent_stack.deinit(self.gpa);
     const parent_registers = self.register_manager.registers;
-    const parent_compare_flags_inst = self.compare_flags_inst;
+    const parent_condition_flags_inst = self.condition_flags_inst;
     try self.branch_stack.append(.{});
     errdefer {
 @@ -1324,7 +1308,7 @@ fn airCondBr(self: *Self, inst: Air.Inst.Index) !void {
     defer saved_then_branch.deinit(self.gpa);
     self.register_manager.registers = parent_registers;
-    self.compare_flags_inst = parent_compare_flags_inst;
+    self.condition_flags_inst = parent_condition_flags_inst;
     self.stack.deinit(self.gpa);
     self.stack = parent_stack;
 @@ -1537,37 +1521,13 @@ fn airNot(self: *Self, inst: Air.Inst.Index) !void {
         switch (operand) {
             .dead => unreachable,
             .unreach => unreachable,
-            .compare_flags_unsigned => |op| {
+            .condition_flags => |op| {
-                const r = MCValue{
+                break :result MCValue{
-                    .compare_flags_unsigned = .{
+                    .condition_flags = .{
-                        .cmp = switch (op.cmp) {
+                        .cond = op.cond.negate(),
-                            .gte => .lt,
-                            .gt => .lte,
-                            .neq => .eq,
-                            .lt => .gte,
-                            .lte => .gt,
-                            .eq => .neq,
-                        },
                         .ccr = op.ccr,
                     },
                 };
-                break :result r;
-            },
-            .compare_flags_signed => |op| {
-                const r = MCValue{
-                    .compare_flags_signed = .{
-                        .cmp = switch (op.cmp) {
-                            .gte => .lt,
-                            .gt => .lte,
-                            .neq => .eq,
-                            .lt => .gte,
-                            .lte => .gt,
-                            .eq => .neq,
-                        },
-                        .ccr = op.ccr,
-                    },
-                };
-                break :result r;
             },
             else => {
                 switch (operand_ty.zigTypeTag()) {
 @@ -2667,20 +2627,10 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
     switch (mcv) {
         .dead => unreachable,
         .unreach, .none => return, // Nothing to do.
-        .compare_flags_signed,
+        .condition_flags => |op| {
-        .compare_flags_unsigned,
+            const condition = op.cond;
-        => {
+            const ccr = op.ccr;
-            const condition = switch (mcv) {
-                .compare_flags_unsigned => |op| Instruction.ICondition.fromCompareOperatorUnsigned(op.cmp),
-                .compare_flags_signed => |op| Instruction.ICondition.fromCompareOperatorSigned(op.cmp),
-                else => unreachable,
-            };
-            const ccr = switch (mcv) {
-                .compare_flags_unsigned => |op| op.ccr,
-                .compare_flags_signed => |op| op.ccr,
-                else => unreachable,
-            };
             // TODO handle floating point CCRs
             assert(ccr == .xcc or ccr == .icc);
 @@ -2700,7 +2650,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
                 .data = .{
                     .conditional_move = .{
                         .ccr = ccr,
-                        .cond = .{ .icond = condition },
+                        .cond = condition,
                         .is_imm = true,
                         .rd = reg,
                         .rs2_or_imm = .{ .imm = 1 },
 @@ -2874,8 +2824,7 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: u32, mcv: MCValue) InnerErro
                 else => return self.fail("TODO implement memset", .{}),
             }
         },
-        .compare_flags_unsigned,
+        .condition_flags,
-        .compare_flags_signed,
         .immediate,
         .ptr_stack_offset,
         => {
 @@ -3103,7 +3052,7 @@ fn isErr(self: *Self, ty: Type, operand: MCValue) !MCValue {
                 } },
             });
-            return MCValue{ .compare_flags_unsigned = .{ .cmp = .gt, .ccr = .xcc } };
+            return MCValue{ .condition_flags = .{ .cond = .{ .icond = .gu }, .ccr = .xcc } };
         } else {
             return self.fail("TODO isErr for errors with size > 8", .{});
         }
 @@ -3116,9 +3065,8 @@ fn isNonErr(self: *Self, ty: Type, operand: MCValue) !MCValue {
     // Call isErr, then negate the result.
     const is_err_result = try self.isErr(ty, operand);
     switch (is_err_result) {
-        .compare_flags_unsigned => |op| {
+        .condition_flags => |op| {
-            assert(op.cmp == .gt);
+            return MCValue{ .condition_flags = .{ .cond = op.cond.negate(), .ccr = op.ccr } };
-            return MCValue{ .compare_flags_unsigned = .{ .cmp = .lte, .ccr = op.ccr } };
         },
         .immediate => |imm| {
             assert(imm == 0);
 @@ -3168,8 +3116,7 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
         .undef => unreachable,
         .unreach => unreachable,
         .dead => unreachable,
-        .compare_flags_unsigned,
+        .condition_flags,
-        .compare_flags_signed,
         .register_with_overflow,
         => unreachable, // cannot hold an address
         .immediate => |imm| try self.setRegOrMem(elem_ty, dst_mcv, .{ .memory = imm }),
 @@ -3181,7 +3128,7 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
             switch (dst_mcv) {
                 .dead => unreachable,
                 .undef => unreachable,
-                .compare_flags_signed, .compare_flags_unsigned => unreachable,
+                .condition_flags => unreachable,
                 .register => |dst_reg| {
                     try self.genLoad(dst_reg, addr_reg, i13, 0, elem_size);
                 },
 @@ -3277,10 +3224,10 @@ fn processDeath(self: *Self, inst: Air.Inst.Index) void {
         },
         .register_with_overflow => |rwo| {
             self.register_manager.freeReg(rwo.reg);
-            self.compare_flags_inst = null;
+            self.condition_flags_inst = null;
         },
-        .compare_flags_signed, .compare_flags_unsigned => {
+        .condition_flags => {
-            self.compare_flags_inst = null;
+            self.condition_flags_inst = null;
         },
         else => {}, // TODO process stack allocation death
     }
 @@ -3474,15 +3421,13 @@ fn setRegOrMem(self: *Self, ty: Type, loc: MCValue, val: MCValue) !void {
     }
 }
-/// Save the current instruction stored in the compare flags if
+/// Save the current instruction stored in the condition flags if
 /// occupied
-fn spillCompareFlagsIfOccupied(self: *Self) !void {
+fn spillConditionFlagsIfOccupied(self: *Self) !void {
-    if (self.compare_flags_inst) |inst_to_save| {
+    if (self.condition_flags_inst) |inst_to_save| {
         const mcv = self.getResolvedInstValue(inst_to_save);
         const new_mcv = switch (mcv) {
-            .compare_flags_signed,
+            .condition_flags => try self.allocRegOrMem(inst_to_save, true),
-            .compare_flags_unsigned,
-            => try self.allocRegOrMem(inst_to_save, true),
             .register_with_overflow => try self.allocRegOrMem(inst_to_save, false),
             else => unreachable, // mcv doesn't occupy the compare flags
         };
 @@ -3493,7 +3438,7 @@ fn spillCompareFlagsIfOccupied(self: *Self) !void {
         const branch = &self.branch_stack.items[self.branch_stack.items.len - 1];
         try branch.inst_table.put(self.gpa, inst_to_save, new_mcv);
-        self.compare_flags_inst = null;
+        self.condition_flags_inst = null;
         // TODO consolidate with register manager and spillInstruction
         // this call should really belong in the register manager!
 @@ -3522,8 +3467,7 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type
         .undef => unreachable,
         .unreach => unreachable,
         .dead => unreachable,
-        .compare_flags_unsigned,
+        .condition_flags,
-        .compare_flags_signed,
         .register_with_overflow,
         => unreachable, // cannot hold an address
         .immediate => |imm| {

src/arch/sparc64/bits.zig+24-7

...	@@ -673,10 +673,27 @@ pub const Instruction = union(enum) {	...	@@ -673,10 +673,27 @@ pub const Instruction = union(enum) {
673	}	673	}
674	};	674	};
675		675
676	pub const Condition = packed union {	676	pub const ConditionTag = enum { fcond, icond };
		677	pub const Condition = union(ConditionTag) {
677	fcond: FCondition,	678	fcond: FCondition,
678	icond: ICondition,	679	icond: ICondition,
679	encoded: u4,	680
		681	/// Encodes the condition into the instruction bit pattern.
		682	pub fn enc(cond: Condition) u4 {
		683	return switch (cond) {
		684	.icond => \|c\| @enumToInt(c),
		685	.fcond => \|c\| @enumToInt(c),
		686	};
		687	}
		688
		689	/// Returns the condition which is true iff the given condition is
		690	/// false (if such a condition exists).
		691	pub fn negate(cond: Condition) Condition {
		692	return switch (cond) {
		693	.icond => \|c\| .{ .icond = c.negate() },
		694	.fcond => \|c\| .{ .fcond = c.negate() },
		695	};
		696	}
680	};	697	};
681		698
682	pub fn toU32(self: Instruction) u32 {	699	pub fn toU32(self: Instruction) u32 {
...	@@ -755,7 +772,7 @@ pub const Instruction = union(enum) {	...	@@ -755,7 +772,7 @@ pub const Instruction = union(enum) {
755	return Instruction{	772	return Instruction{
756	.format_2b = .{	773	.format_2b = .{
757	.a = @boolToInt(annul),	774	.a = @boolToInt(annul),
758	.cond = cond.encoded,	775	.cond = cond.enc(),
759	.op2 = op2,	776	.op2 = op2,
760	.disp22 = udisp_truncated,	777	.disp22 = udisp_truncated,
761	},	778	},
...	@@ -776,7 +793,7 @@ pub const Instruction = union(enum) {	...	@@ -776,7 +793,7 @@ pub const Instruction = union(enum) {
776	return Instruction{	793	return Instruction{
777	.format_2c = .{	794	.format_2c = .{
778	.a = @boolToInt(annul),	795	.a = @boolToInt(annul),
779	.cond = cond.encoded,	796	.cond = cond.enc(),
780	.op2 = op2,	797	.op2 = op2,
781	.cc1 = ccr_cc1,	798	.cc1 = ccr_cc1,
782	.cc0 = ccr_cc0,	799	.cc0 = ccr_cc0,
...	@@ -1057,7 +1074,7 @@ pub const Instruction = union(enum) {	...	@@ -1057,7 +1074,7 @@ pub const Instruction = union(enum) {
1057	.rd = rd.enc(),	1074	.rd = rd.enc(),
1058	.op3 = op3,	1075	.op3 = op3,
1059	.cc2 = ccr_cc2,	1076	.cc2 = ccr_cc2,
1060	.cond = cond.encoded,	1077	.cond = cond.enc(),
1061	.cc1 = ccr_cc1,	1078	.cc1 = ccr_cc1,
1062	.cc0 = ccr_cc0,	1079	.cc0 = ccr_cc0,
1063	.rs2 = rs2.enc(),	1080	.rs2 = rs2.enc(),
...	@@ -1074,7 +1091,7 @@ pub const Instruction = union(enum) {	...	@@ -1074,7 +1091,7 @@ pub const Instruction = union(enum) {
1074	.rd = rd.enc(),	1091	.rd = rd.enc(),
1075	.op3 = op3,	1092	.op3 = op3,
1076	.cc2 = ccr_cc2,	1093	.cc2 = ccr_cc2,
1077	.cond = cond.encoded,	1094	.cond = cond.enc(),
1078	.cc1 = ccr_cc1,	1095	.cc1 = ccr_cc1,
1079	.cc0 = ccr_cc0,	1096	.cc0 = ccr_cc0,
1080	.simm11 = @bitCast(u11, imm),	1097	.simm11 = @bitCast(u11, imm),
...	@@ -1122,7 +1139,7 @@ pub const Instruction = union(enum) {	...	@@ -1122,7 +1139,7 @@ pub const Instruction = union(enum) {
1122	.format_4g = .{	1139	.format_4g = .{
1123	.rd = rd.enc(),	1140	.rd = rd.enc(),
1124	.op3 = op3,	1141	.op3 = op3,
1125	.cond = cond.encoded,	1142	.cond = cond.enc(),
1126	.opf_cc = opf_cc,	1143	.opf_cc = opf_cc,
1127	.opf_low = opf_low,	1144	.opf_low = opf_low,
1128	.rs2 = rs2.enc(),	1145	.rs2 = rs2.enc(),