| author | |
| committer | |
| log | 8bbb4a2f81b46f2a72a81575b9a9158b0d0bd94c |
| tree | 7a83f18718ab2521cdf28271a40f8b684e001c10 |
| parent | 8f2bb38a097aceb2af9c5109dd109297c890d1dd |
See #136232 files changed, 23 insertions(+), 15 deletions(-)
src/test.zig+7-1| ... | ... | @@ -1816,7 +1816,13 @@ pub const TestContext = struct { |
| 1816 | 1816 | try argv.appendSlice(&.{ "-I", p }); |
| 1817 | 1817 | } |
| 1818 | 1818 | } else switch (host.getExternalExecutor(target_info, .{ .link_libc = case.link_libc })) { |
| 1819 | .native => try argv.append(exe_path), | |
| 1819 | .native => { | |
| 1820 | if (case.backend == .stage2 and case.target.getCpuArch() == .arm) { | |
| 1821 | // https://github.com/ziglang/zig/issues/13623 | |
| 1822 | continue :update; // Pass test. | |
| 1823 | } | |
| 1824 | try argv.append(exe_path); | |
| 1825 | }, | |
| 1820 | 1826 | .bad_dl, .bad_os_or_cpu => continue :update, // Pass test. |
| 1821 | 1827 | |
| 1822 | 1828 | .rosetta => if (enable_rosetta) { |
test/tests.zig+16-14| ... | ... | @@ -81,20 +81,22 @@ const test_targets = blk: { |
| 81 | 81 | .single_threaded = true, |
| 82 | 82 | .backend = .stage2_wasm, |
| 83 | 83 | }, |
| 84 | .{ | |
| 85 | .target = .{ | |
| 86 | .cpu_arch = .arm, | |
| 87 | .os_tag = .linux, | |
| 88 | }, | |
| 89 | .backend = .stage2_arm, | |
| 90 | }, | |
| 91 | .{ | |
| 92 | .target = CrossTarget.parse(.{ | |
| 93 | .arch_os_abi = "arm-linux-none", | |
| 94 | .cpu_features = "generic+v8a", | |
| 95 | }) catch unreachable, | |
| 96 | .backend = .stage2_arm, | |
| 97 | }, | |
| 84 | // https://github.com/ziglang/zig/issues/13623 | |
| 85 | //.{ | |
| 86 | // .target = .{ | |
| 87 | // .cpu_arch = .arm, | |
| 88 | // .os_tag = .linux, | |
| 89 | // }, | |
| 90 | // .backend = .stage2_arm, | |
| 91 | //}, | |
| 92 | // https://github.com/ziglang/zig/issues/13623 | |
| 93 | //.{ | |
| 94 | // .target = CrossTarget.parse(.{ | |
| 95 | // .arch_os_abi = "arm-linux-none", | |
| 96 | // .cpu_features = "generic+v8a", | |
| 97 | // }) catch unreachable, | |
| 98 | // .backend = .stage2_arm, | |
| 99 | //}, | |
| 98 | 100 | .{ |
| 99 | 101 | .target = .{ |
| 100 | 102 | .cpu_arch = .aarch64, |