authorgravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2021-06-15 11:39:53-07:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2021-06-17 20:28:37-07:00
log8be29674a95b8a6dd52b439701180e9e74e221aa
tree4056c802918a9d8cd38418545ac539b11ad8bd24
parent52ead255a27e62e7c33748b04971aca49e06b5d8

fix RISC-V assembly CPU features

Previously, Zig did not properly communicate the target CPU features for RISC-V to clang assembler, because Clang has a different way to pass CPU features for C code and for assembly code. This commit makes Zig pass a RISC-V -march flag in order to communicate CPU features to Clang when compiling assembly files.

1 files changed, 39 insertions(+), 0 deletions(-)

src/Compilation.zig+39
......@@ -2984,11 +2984,50 @@ pub fn addCCArgs(
29842984 // all CPU features here.
29852985 switch (target.cpu.arch) {
29862986 .riscv32, .riscv64 => {
2987 const RvArchFeat = struct { char: u8, feat: std.Target.riscv.Feature };
2988 const letters = [_]RvArchFeat{
2989 .{ .char = 'm', .feat = .m },
2990 .{ .char = 'a', .feat = .a },
2991 .{ .char = 'f', .feat = .f },
2992 .{ .char = 'd', .feat = .d },
2993 .{ .char = 'c', .feat = .c },
2994 };
2995 const prefix: []const u8 = if (target.cpu.arch == .riscv64) "rv64" else "rv32";
2996 const prefix_len = 4;
2997 assert(prefix.len == prefix_len);
2998 var march_buf: [prefix_len + letters.len + 1]u8 = undefined;
2999 var march_index: usize = prefix_len;
3000 mem.copy(u8, &march_buf, prefix);
3001
3002 if (std.Target.riscv.featureSetHas(target.cpu.features, .e)) {
3003 march_buf[march_index] = 'e';
3004 } else {
3005 march_buf[march_index] = 'i';
3006 }
3007 march_index += 1;
3008
3009 for (letters) |letter| {
3010 if (std.Target.riscv.featureSetHas(target.cpu.features, letter.feat)) {
3011 march_buf[march_index] = letter.char;
3012 march_index += 1;
3013 }
3014 }
3015
3016 const march_arg = try std.fmt.allocPrint(arena, "-march={s}", .{
3017 march_buf[0..march_index],
3018 });
3019 try argv.append(march_arg);
3020
29873021 if (std.Target.riscv.featureSetHas(target.cpu.features, .relax)) {
29883022 try argv.append("-mrelax");
29893023 } else {
29903024 try argv.append("-mno-relax");
29913025 }
3026 if (std.Target.riscv.featureSetHas(target.cpu.features, .save_restore)) {
3027 try argv.append("-msave-restore");
3028 } else {
3029 try argv.append("-mno-save-restore");
3030 }
29923031 },
29933032 else => {
29943033 // TODO