authorgravatar for git@vexu.euVeikka Tuominen <git@vexu.eu> 2020-03-10 22:33:32+02:00
committergravatar for git@vexu.euVeikka Tuominen <git@vexu.eu> 2020-03-10 22:33:32+02:00
log8dc188ebe06b5b78dcead521561858fc27e25204
treed5c05dbe81a0afc0a738dec42f2809a569a3f248
parent675f01f1768aa08c307640b53e8a5240fa190fab
signaturelock-open Commit is signed but in an unrecognized format.

support atomic operations with bools

3 files changed, 59 insertions(+), 0 deletions(-)

src/codegen.cpp+43
......@@ -5224,6 +5224,15 @@ static LLVMValueRef ir_render_cmpxchg(CodeGen *g, IrExecutableGen *executable, I
52245224 LLVMValueRef cmp_val = ir_llvm_value(g, instruction->cmp_value);
52255225 LLVMValueRef new_val = ir_llvm_value(g, instruction->new_value);
52265226
5227 ZigType *operand_type = instruction->new_value->value->type;
5228 if (operand_type->id == ZigTypeIdBool) {
5229 // treat bool as u8
5230 ptr_val = LLVMBuildBitCast(g->builder, ptr_val,
5231 LLVMPointerType(g->builtin_types.entry_u8->llvm_type, 0), "");
5232 cmp_val = LLVMConstZExt(cmp_val, g->builtin_types.entry_u8->llvm_type);
5233 new_val = LLVMConstZExt(new_val, g->builtin_types.entry_u8->llvm_type);
5234 }
5235
52275236 LLVMAtomicOrdering success_order = to_LLVMAtomicOrdering(instruction->success_order);
52285237 LLVMAtomicOrdering failure_order = to_LLVMAtomicOrdering(instruction->failure_order);
52295238
......@@ -5236,6 +5245,9 @@ static LLVMValueRef ir_render_cmpxchg(CodeGen *g, IrExecutableGen *executable, I
52365245
52375246 if (!handle_is_ptr(g, optional_type)) {
52385247 LLVMValueRef payload_val = LLVMBuildExtractValue(g->builder, result_val, 0, "");
5248 if (operand_type->id == ZigTypeIdBool) {
5249 payload_val = LLVMBuildTrunc(g->builder, payload_val, g->builtin_types.entry_bool->llvm_type, "");
5250 }
52395251 LLVMValueRef success_bit = LLVMBuildExtractValue(g->builder, result_val, 1, "");
52405252 return LLVMBuildSelect(g->builder, success_bit, LLVMConstNull(get_llvm_type(g, child_type)), payload_val, "");
52415253 }
......@@ -5250,6 +5262,9 @@ static LLVMValueRef ir_render_cmpxchg(CodeGen *g, IrExecutableGen *executable, I
52505262 ir_assert(type_has_bits(g, child_type), &instruction->base);
52515263
52525264 LLVMValueRef payload_val = LLVMBuildExtractValue(g->builder, result_val, 0, "");
5265 if (operand_type->id == ZigTypeIdBool) {
5266 payload_val = LLVMBuildTrunc(g->builder, payload_val, g->builtin_types.entry_bool->llvm_type, "");
5267 }
52535268 LLVMValueRef val_ptr = LLVMBuildStructGEP(g->builder, result_loc, maybe_child_index, "");
52545269 gen_assign_raw(g, val_ptr, get_pointer_to_type(g, child_type, false), payload_val);
52555270
......@@ -5827,6 +5842,16 @@ static LLVMValueRef ir_render_atomic_rmw(CodeGen *g, IrExecutableGen *executable
58275842 LLVMValueRef ptr = ir_llvm_value(g, instruction->ptr);
58285843 LLVMValueRef operand = ir_llvm_value(g, instruction->operand);
58295844
5845 if (operand_type->id == ZigTypeIdBool) {
5846 // treat bool as u8
5847 LLVMValueRef casted_ptr = LLVMBuildBitCast(g->builder, ptr,
5848 LLVMPointerType(g->builtin_types.entry_u8->llvm_type, 0), "");
5849 LLVMValueRef casted_operand = LLVMBuildPtrToInt(g->builder, operand, g->builtin_types.entry_u8->llvm_type, "");
5850 LLVMValueRef uncasted_result = ZigLLVMBuildAtomicRMW(g->builder, op, casted_ptr, casted_operand, ordering,
5851 g->is_single_threaded);
5852 return LLVMBuildTrunc(g->builder, uncasted_result, g->builtin_types.entry_bool->llvm_type, "");
5853 }
5854
58305855 if (get_codegen_ptr_type_bail(g, operand_type) == nullptr) {
58315856 return ZigLLVMBuildAtomicRMW(g->builder, op, ptr, operand, ordering, g->is_single_threaded);
58325857 }
......@@ -5845,6 +5870,16 @@ static LLVMValueRef ir_render_atomic_load(CodeGen *g, IrExecutableGen *executabl
58455870{
58465871 LLVMAtomicOrdering ordering = to_LLVMAtomicOrdering(instruction->ordering);
58475872 LLVMValueRef ptr = ir_llvm_value(g, instruction->ptr);
5873
5874 ZigType *operand_type = instruction->ptr->value->type->data.pointer.child_type;
5875 if (operand_type->id == ZigTypeIdBool) {
5876 // treat bool as u8
5877 ptr = LLVMBuildBitCast(g->builder, ptr,
5878 LLVMPointerType(g->builtin_types.entry_u8->llvm_type, 0), "");
5879 LLVMValueRef load_inst = gen_load(g, ptr, instruction->ptr->value->type, "");
5880 LLVMSetOrdering(load_inst, ordering);
5881 return LLVMBuildTrunc(g->builder, load_inst, g->builtin_types.entry_bool->llvm_type, "");
5882 }
58485883 LLVMValueRef load_inst = gen_load(g, ptr, instruction->ptr->value->type, "");
58495884 LLVMSetOrdering(load_inst, ordering);
58505885 return load_inst;
......@@ -5856,6 +5891,14 @@ static LLVMValueRef ir_render_atomic_store(CodeGen *g, IrExecutableGen *executab
58565891 LLVMAtomicOrdering ordering = to_LLVMAtomicOrdering(instruction->ordering);
58575892 LLVMValueRef ptr = ir_llvm_value(g, instruction->ptr);
58585893 LLVMValueRef value = ir_llvm_value(g, instruction->value);
5894
5895 ZigType *operand_type = instruction->value->value->type;
5896 if (operand_type->id == ZigTypeIdBool) {
5897 // treat bool as u8
5898 ptr = LLVMBuildBitCast(g->builder, ptr,
5899 LLVMPointerType(g->builtin_types.entry_u8->llvm_type, 0), "");
5900 value = LLVMConstZExt(value, g->builtin_types.entry_u8->llvm_type);
5901 }
58595902 LLVMValueRef store_inst = gen_store(g, value, ptr, instruction->ptr->value->type);
58605903 LLVMSetOrdering(store_inst, ordering);
58615904 return nullptr;
src/ir.cpp+6
......@@ -28357,6 +28357,8 @@ static ZigType *ir_resolve_atomic_operand_type(IrAnalyze *ira, IrInstGen *op) {
2835728357 max_atomic_bits, (uint32_t) operand_type->data.floating.bit_count));
2835828358 return ira->codegen->builtin_types.entry_invalid;
2835928359 }
28360 } else if (operand_type->id == ZigTypeIdBool) {
28361 // will be treated as u8
2836028362 } else {
2836128363 Error err;
2836228364 ZigType *operand_ptr_type;
......@@ -28397,6 +28399,10 @@ static IrInstGen *ir_analyze_instruction_atomic_rmw(IrAnalyze *ira, IrInstSrcAto
2839728399 ir_add_error(ira, &instruction->op->base,
2839828400 buf_sprintf("@atomicRmw on enum only works with .Xchg"));
2839928401 return ira->codegen->invalid_inst_gen;
28402 } else if (operand_type->id == ZigTypeIdBool && op != AtomicRmwOp_xchg) {
28403 ir_add_error(ira, &instruction->op->base,
28404 buf_sprintf("@atomicRmw on bool only works with .Xchg"));
28405 return ira->codegen->invalid_inst_gen;
2840028406 } else if (operand_type->id == ZigTypeIdFloat && op > AtomicRmwOp_sub) {
2840128407 ir_add_error(ira, &instruction->op->base,
2840228408 buf_sprintf("@atomicRmw with float only works with .Xchg, .Add and .Sub"));
test/stage1/behavior/atomics.zig+10
......@@ -161,3 +161,13 @@ fn testAtomicRmwFloat() void {
161161 _ = @atomicRmw(f32, &x, .Sub, 2, .SeqCst);
162162 expect(x == 4);
163163}
164
165test "atomics with bool" {
166 var x = false;
167 @atomicStore(bool, &x, true, .SeqCst);
168 expect(x == true);
169 expect(@atomicLoad(bool, &x, .SeqCst) == true);
170 expect(@atomicRmw(bool, &x, .Xchg, false, .SeqCst) == true);
171 expect(@cmpxchgStrong(bool, &x, false, true, .SeqCst, .SeqCst) == null);
172 expect(@cmpxchgStrong(bool, &x, false, true, .SeqCst, .SeqCst).? == true);
173}