diff --git a/lib/compiler_rt/aarch64_outline_atomics.zig b/lib/compiler_rt/aarch64_outline_atomics.zig
index c7ec9fd7aa20fc0c22a6a6df42a2382b31114291..c03306cd1a1cd07e0a450f66c67b985f41a1e0d3 100644
--- a/lib/compiler_rt/aarch64_outline_atomics.zig
+++ b/lib/compiler_rt/aarch64_outline_atomics.zig
@@ -9,7 +9,7 @@ const always_has_lse = builtin.cpu.has(.aarch64, .lse);
 /// It is intentionally not exported in order to make the machine code that
 /// uses it a statically predicted direct branch rather than using the PLT,
 /// which ARM is concerned would have too much overhead.
-pub var __aarch64_have_lse_atomics: u8 = @intFromBool(always_has_lse);
+var __aarch64_have_lse_atomics: u8 = @intFromBool(always_has_lse);
 
 fn __aarch64_cas1_relax() align(16) callconv(.naked) void {
     @setRuntimeSafety(false);
diff --git a/lib/compiler_rt/fmv.zig b/lib/compiler_rt/fmv.zig
index 184fe7046a34b75d2c9079e8bb9da2e43b0c240d..fc05e37246be7ad1956b5b0566d2994c65b6ff4e 100644
--- a/lib/compiler_rt/fmv.zig
+++ b/lib/compiler_rt/fmv.zig
@@ -18,7 +18,7 @@ comptime {
 const aarch64 = struct {
     comptime {
         symbol(&__aarch64_cpu_features, "__aarch64_cpu_features");
-        symbol(&@import("aarch64_outline_atomics.zig").__aarch64_have_lse_atomics, "__aarch64_have_lse_atomics");
+        symbol(&__aarch64_have_lse_atomics, "__aarch64_have_lse_atomics");
         symbol(&__init_cpu_features_resolver, "__init_cpu_features_resolver");
     }
 
@@ -28,6 +28,8 @@ const aarch64 = struct {
         .features = 0,
     };
 
+    var __aarch64_have_lse_atomics: bool = false;
+
     const __init_cpu_features_resolver = switch (builtin.target.os.tag) {
         .fuchsia,
         .driverkit,
diff --git a/tools/gen_outline_atomics.zig b/tools/gen_outline_atomics.zig
index ebbd77a927c3b98611aa1dedd5b72e169cd1dc02..cbeff5ea76406a7756c1a25c342f9a0c31e412f3 100644
--- a/tools/gen_outline_atomics.zig
+++ b/tools/gen_outline_atomics.zig
@@ -32,7 +32,7 @@ pub fn main(init: std.process.Init) !void {
         \\/// It is intentionally not exported in order to make the machine code that
         \\/// uses it a statically predicted direct branch rather than using the PLT,
         \\/// which ARM is concerned would have too much overhead.
-        \\pub var __aarch64_have_lse_atomics: u8 = @intFromBool(always_has_lse);
+        \\var __aarch64_have_lse_atomics: u8 = @intFromBool(always_has_lse);
         \\
         \\
     );