authorgravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2024-02-10 23:09:32+01:00
committergravatar for jacobly@ziglang.orgJacob Young <jacobly@ziglang.org> 2024-02-12 05:25:07+01:00
log9023ff04d0dff0c5eff761c5aa1f8611106767d6
tree7080f7891be1dc6f5a5c75dabdb473c0031d956e
parenta9f738e56b65c8c510da11ec864460f414d82c95

x86_64: fix register clobber

2 files changed, 10 insertions(+), 7 deletions(-)

lib/std/math/nextafter.zig-2
......@@ -102,8 +102,6 @@ fn nextAfterFloat(comptime T: type, x: T, y: T) T {
102102}
103103
104104test "math.nextAfter.int" {
105 if (@import("builtin").zig_backend == .stage2_x86_64) return error.SkipZigTest;
106
107105 try expect(nextAfter(i0, 0, 0) == 0);
108106 try expect(nextAfter(u0, 0, 0) == 0);
109107 try expect(nextAfter(i1, 0, 0) == 0);
src/arch/x86_64/CodeGen.zig+10-5
......@@ -3776,6 +3776,9 @@ fn airAddSubWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
37763776 .Vector => return self.fail("TODO implement add/sub with overflow for Vector type", .{}),
37773777 .Int => {
37783778 try self.spillEflagsIfOccupied();
3779 try self.spillRegisters(&.{ .rcx, .rdi, .rsi });
3780 const reg_locks = self.register_manager.lockRegsAssumeUnused(3, .{ .rcx, .rdi, .rsi });
3781 defer for (reg_locks) |lock| self.register_manager.unlockReg(lock);
37793782
37803783 const partial_mcv = try self.genBinOp(null, switch (tag) {
37813784 .add_with_overflow => .add,
......@@ -3839,8 +3842,10 @@ fn airShlWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
38393842 .Vector => return self.fail("TODO implement shl with overflow for Vector type", .{}),
38403843 .Int => {
38413844 try self.spillEflagsIfOccupied();
3845 try self.spillRegisters(&.{ .rcx, .rdi, .rsi });
3846 const reg_locks = self.register_manager.lockRegsAssumeUnused(3, .{ .rcx, .rdi, .rsi });
3847 defer for (reg_locks) |lock| self.register_manager.unlockReg(lock);
38423848
3843 try self.register_manager.getReg(.rcx, null);
38443849 const lhs = try self.resolveInst(bin_op.lhs);
38453850 const rhs = try self.resolveInst(bin_op.rhs);
38463851
......@@ -4296,8 +4301,8 @@ fn airMulWithOverflow(self: *Self, inst: Air.Inst.Index) !void {
42964301 };
42974302
42984303 try self.spillEflagsIfOccupied();
4299 try self.spillRegisters(&.{ .rax, .rcx, .rdx });
4300 const reg_locks = self.register_manager.lockRegsAssumeUnused(3, .{ .rax, .rcx, .rdx });
4304 try self.spillRegisters(&.{ .rax, .rcx, .rdx, .rdi, .rsi });
4305 const reg_locks = self.register_manager.lockRegsAssumeUnused(5, .{ .rax, .rcx, .rdx, .rdi, .rsi });
43014306 defer for (reg_locks) |lock| self.register_manager.unlockReg(lock);
43024307
43034308 const cc: Condition = switch (dst_info.signedness) {
......@@ -8273,8 +8278,8 @@ fn genShiftBinOp(
82738278 assert(rhs_ty.abiSize(mod) == 1);
82748279
82758280 try self.register_manager.getReg(.rcx, null);
8276 const rcx_lock = self.register_manager.lockRegAssumeUnused(.rcx);
8277 defer self.register_manager.unlockReg(rcx_lock);
8281 const rcx_lock = self.register_manager.lockReg(.rcx);
8282 defer if (rcx_lock) |lock| self.register_manager.unlockReg(lock);
82788283
82798284 const lhs_lock = switch (lhs_mcv) {
82808285 .register => |reg| self.register_manager.lockReg(reg),