authorgravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2021-06-15 11:39:53-07:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2021-06-15 17:12:22-04:00
log90c73d8768bd51c84a5bf3d589d31abce6d93d37
tree3a8cd89a878209178a2c8561d15ef33cb6fb118e
parent515d6430c0298daf304e48b46e6b43802bbfdab4

fix RISC-V assembly CPU features

Previously, Zig did not properly communicate the target CPU features for RISC-V to clang assembler, because Clang has a different way to pass CPU features for C code and for assembly code. This commit makes Zig pass a RISC-V -march flag in order to communicate CPU features to Clang when compiling assembly files.

1 files changed, 39 insertions(+), 0 deletions(-)

src/Compilation.zig+39
...@@ -3004,11 +3004,50 @@ pub fn addCCArgs(...@@ -3004,11 +3004,50 @@ pub fn addCCArgs(
3004 // all CPU features here.3004 // all CPU features here.
3005 switch (target.cpu.arch) {3005 switch (target.cpu.arch) {
3006 .riscv32, .riscv64 => {3006 .riscv32, .riscv64 => {
3007 const RvArchFeat = struct { char: u8, feat: std.Target.riscv.Feature };
3008 const letters = [_]RvArchFeat{
3009 .{ .char = 'm', .feat = .m },
3010 .{ .char = 'a', .feat = .a },
3011 .{ .char = 'f', .feat = .f },
3012 .{ .char = 'd', .feat = .d },
3013 .{ .char = 'c', .feat = .c },
3014 };
3015 const prefix: []const u8 = if (target.cpu.arch == .riscv64) "rv64" else "rv32";
3016 const prefix_len = 4;
3017 assert(prefix.len == prefix_len);
3018 var march_buf: [prefix_len + letters.len]u8 = undefined;
3019 var march_index: usize = prefix_len;
3020 mem.copy(u8, &march_buf, prefix);
3021
3022 if (std.Target.riscv.featureSetHas(target.cpu.features, .e)) {
3023 march_buf[march_index] = 'e';
3024 } else {
3025 march_buf[march_index] = 'i';
3026 }
3027 march_index += 1;
3028
3029 for (letters) |letter| {
3030 if (std.Target.riscv.featureSetHas(target.cpu.features, letter.feat)) {
3031 march_buf[march_index] = letter.char;
3032 march_index += 1;
3033 }
3034 }
3035
3036 const march_arg = try std.fmt.allocPrint(arena, "-march={s}", .{
3037 march_buf[0..march_index],
3038 });
3039 try argv.append(march_arg);
3040
3007 if (std.Target.riscv.featureSetHas(target.cpu.features, .relax)) {3041 if (std.Target.riscv.featureSetHas(target.cpu.features, .relax)) {
3008 try argv.append("-mrelax");3042 try argv.append("-mrelax");
3009 } else {3043 } else {
3010 try argv.append("-mno-relax");3044 try argv.append("-mno-relax");
3011 }3045 }
3046 if (std.Target.riscv.featureSetHas(target.cpu.features, .save_restore)) {
3047 try argv.append("-msave-restore");
3048 } else {
3049 try argv.append("-mno-save-restore");
3050 }
3012 },3051 },
3013 else => {3052 else => {
3014 // TODO3053 // TODO