| author |  Alex Rønne Petersen <alex@alexrp.com> 2026-05-23 05:43:47+02:00 |
| committer | Alex Rønne Petersen <alex@alexrp.com> 2026-05-23 05:43:47+02:00 |
| log | 9e3eaa6be7b2b22d44205012abc4278cdd673526 |
| tree | c88b728f66cea8938805eca716bdbd4b55bb1271 |
| parent | 3140b375fcdec658d14855c2dd2a21d3a1bcd6b3 |
| parent | d70b56429c4f518c92f6419ce369d6098650ff96 |
Merge pull request 'add `spacemit_x100` + `spacemit_x100` RISC-V CPU models; detect more RISC-V CPU models on Linux' (#35392) from alexrp/zig:more-riscv-models into master
Reviewed-on: https://codeberg.org/ziglang/zig/pulls/353923 files changed, 198 insertions(+), 0 deletions(-)
lib/std/Target/riscv.zig+97
| ... | @@ -3370,6 +3370,103 @@ pub const cpu = struct { | ... | @@ -3370,6 +3370,103 @@ pub const cpu = struct { |
| 3370 | .zvl1024b, | 3370 | .zvl1024b, |
| 3371 | }), | 3371 | }), |
| 3372 | }; | 3372 | }; |
| 3373 | pub const spacemit_a100: CpuModel = .{ | ||
| 3374 | .name = "spacemit_a100", | ||
| 3375 | .llvm_name = null, | ||
| 3376 | .features = featureSet(&[_]Feature{ | ||
| 3377 | .@"64bit", | ||
| 3378 | .a, | ||
| 3379 | .b, | ||
| 3380 | .c, | ||
| 3381 | .dlen_factor_2, | ||
| 3382 | .i, | ||
| 3383 | .m, | ||
| 3384 | .optimized_nf2_segment_load_store, | ||
| 3385 | .optimized_nf3_segment_load_store, | ||
| 3386 | .optimized_nf4_segment_load_store, | ||
| 3387 | .smepmp, | ||
| 3388 | .smnpm, | ||
| 3389 | .smstateen, | ||
| 3390 | .ssccptr, | ||
| 3391 | .sscofpmf, | ||
| 3392 | .sscounterenw, | ||
| 3393 | .ssnpm, | ||
| 3394 | .sspm, | ||
| 3395 | .sstc, | ||
| 3396 | .sstvala, | ||
| 3397 | .sstvecd, | ||
| 3398 | .ssu64xl, | ||
| 3399 | .supm, | ||
| 3400 | .svade, | ||
| 3401 | .svbare, | ||
| 3402 | .svinval, | ||
| 3403 | .svnapot, | ||
| 3404 | .svpbmt, | ||
| 3405 | .unaligned_scalar_mem, | ||
| 3406 | .v, | ||
| 3407 | .vxrm_pipeline_flush, | ||
| 3408 | .za64rs, | ||
| 3409 | .zawrs, | ||
| 3410 | .zbc, | ||
| 3411 | .zbkc, | ||
| 3412 | .zcb, | ||
| 3413 | .zcmop, | ||
| 3414 | .zfa, | ||
| 3415 | .zfh, | ||
| 3416 | .zic64b, | ||
| 3417 | .zicbom, | ||
| 3418 | .zicbop, | ||
| 3419 | .zicboz, | ||
| 3420 | .ziccamoa, | ||
| 3421 | .ziccif, | ||
| 3422 | .zicclsm, | ||
| 3423 | .ziccrse, | ||
| 3424 | .zicntr, | ||
| 3425 | .zicond, | ||
| 3426 | .zifencei, | ||
| 3427 | .zihintntl, | ||
| 3428 | .zihintpause, | ||
| 3429 | .zihpm, | ||
| 3430 | .zimop, | ||
| 3431 | .zkt, | ||
| 3432 | .zvbb, | ||
| 3433 | .zvfbfwma, | ||
| 3434 | .zvfh, | ||
| 3435 | .zvkng, | ||
| 3436 | .zvknha, | ||
| 3437 | .zvksc, | ||
| 3438 | .zvksg, | ||
| 3439 | .zvl1024b, | ||
| 3440 | }), | ||
| 3441 | }; | ||
| 3442 | pub const spacemit_x100: CpuModel = .{ | ||
| 3443 | .name = "spacemit_x100", | ||
| 3444 | .llvm_name = null, | ||
| 3445 | .features = featureSet(&[_]Feature{ | ||
| 3446 | .dlen_factor_2, | ||
| 3447 | .optimized_nf2_segment_load_store, | ||
| 3448 | .optimized_nf3_segment_load_store, | ||
| 3449 | .optimized_nf4_segment_load_store, | ||
| 3450 | .rva23s64, | ||
| 3451 | .smepmp, | ||
| 3452 | .smnpm, | ||
| 3453 | .smstateen, | ||
| 3454 | .sspm, | ||
| 3455 | .unaligned_scalar_mem, | ||
| 3456 | .vxrm_pipeline_flush, | ||
| 3457 | .xsmtvdot, | ||
| 3458 | .zbc, | ||
| 3459 | .zbkc, | ||
| 3460 | .zfh, | ||
| 3461 | .zvfbfwma, | ||
| 3462 | .zvfh, | ||
| 3463 | .zvkng, | ||
| 3464 | .zvknha, | ||
| 3465 | .zvksc, | ||
| 3466 | .zvksg, | ||
| 3467 | .zvl256b, | ||
| 3468 | }), | ||
| 3469 | }; | ||
| 3373 | pub const spacemit_x60: CpuModel = .{ | 3470 | pub const spacemit_x60: CpuModel = .{ |
| 3374 | .name = "spacemit_x60", | 3471 | .name = "spacemit_x60", |
| 3375 | .llvm_name = "spacemit-x60", | 3472 | .llvm_name = "spacemit-x60", |
lib/std/zig/system/linux.zig+4
| ... | @@ -70,12 +70,16 @@ const RiscvCpuinfoImpl = struct { | ... | @@ -70,12 +70,16 @@ const RiscvCpuinfoImpl = struct { |
| 70 | model: ?*const Target.Cpu.Model = null, | 70 | model: ?*const Target.Cpu.Model = null, |
| 71 | 71 | ||
| 72 | const cpu_names = .{ | 72 | const cpu_names = .{ |
| 73 | .{ "andestech,ax45mp", &Target.riscv.cpu.andes_ax45 }, | ||
| 74 | .{ "sifive,p550", &Target.riscv.cpu.sifive_p550 }, | ||
| 73 | .{ "sifive,u54", &Target.riscv.cpu.sifive_u54 }, | 75 | .{ "sifive,u54", &Target.riscv.cpu.sifive_u54 }, |
| 74 | .{ "sifive,u54-mc", &Target.riscv.cpu.sifive_u54 }, | 76 | .{ "sifive,u54-mc", &Target.riscv.cpu.sifive_u54 }, |
| 75 | .{ "sifive,u7", &Target.riscv.cpu.sifive_7_series }, | 77 | .{ "sifive,u7", &Target.riscv.cpu.sifive_7_series }, |
| 76 | .{ "sifive,u74", &Target.riscv.cpu.sifive_u74 }, | 78 | .{ "sifive,u74", &Target.riscv.cpu.sifive_u74 }, |
| 77 | .{ "sifive,u74-mc", &Target.riscv.cpu.sifive_u74 }, | 79 | .{ "sifive,u74-mc", &Target.riscv.cpu.sifive_u74 }, |
| 80 | .{ "sifive,x280", &Target.riscv.cpu.sifive_x280 }, | ||
| 78 | .{ "spacemit,x60", &Target.riscv.cpu.spacemit_x60 }, | 81 | .{ "spacemit,x60", &Target.riscv.cpu.spacemit_x60 }, |
| 82 | .{ "spacemit,x100", &Target.riscv.cpu.spacemit_x100 }, | ||
| 79 | }; | 83 | }; |
| 80 | 84 | ||
| 81 | fn line_hook(self: *RiscvCpuinfoImpl, key: []const u8, value: []const u8) !bool { | 85 | fn line_hook(self: *RiscvCpuinfoImpl, key: []const u8, value: []const u8) !bool { |
tools/update_cpu_features.zig+97
| ... | @@ -1548,6 +1548,103 @@ const targets = [_]ArchTarget{ | ... | @@ -1548,6 +1548,103 @@ const targets = [_]ArchTarget{ |
| 1548 | .zig_name = "baseline_rv64", | 1548 | .zig_name = "baseline_rv64", |
| 1549 | .features = &.{ "64bit", "a", "c", "d", "f", "i", "m" }, | 1549 | .features = &.{ "64bit", "a", "c", "d", "f", "i", "m" }, |
| 1550 | }, | 1550 | }, |
| 1551 | .{ | ||
| 1552 | .llvm_name = null, | ||
| 1553 | .zig_name = "spacemit_a100", | ||
| 1554 | .features = &.{ | ||
| 1555 | "64bit", | ||
| 1556 | "a", | ||
| 1557 | "b", | ||
| 1558 | "c", | ||
| 1559 | "dlen_factor_2", | ||
| 1560 | "i", | ||
| 1561 | "m", | ||
| 1562 | "optimized_nf2_segment_load_store", | ||
| 1563 | "optimized_nf3_segment_load_store", | ||
| 1564 | "optimized_nf4_segment_load_store", | ||
| 1565 | "smepmp", | ||
| 1566 | "smnpm", | ||
| 1567 | "smstateen", | ||
| 1568 | "ssccptr", | ||
| 1569 | "sscofpmf", | ||
| 1570 | "sscounterenw", | ||
| 1571 | "ssnpm", | ||
| 1572 | "sspm", | ||
| 1573 | "sstc", | ||
| 1574 | "sstvala", | ||
| 1575 | "sstvecd", | ||
| 1576 | "ssu64xl", | ||
| 1577 | "supm", | ||
| 1578 | "svade", | ||
| 1579 | "svbare", | ||
| 1580 | "svinval", | ||
| 1581 | "svnapot", | ||
| 1582 | "svpbmt", | ||
| 1583 | "unaligned_scalar_mem", | ||
| 1584 | "v", | ||
| 1585 | "vxrm_pipeline_flush", | ||
| 1586 | "za64rs", | ||
| 1587 | "zawrs", | ||
| 1588 | "zbc", | ||
| 1589 | "zbkc", | ||
| 1590 | "zcb", | ||
| 1591 | "zcmop", | ||
| 1592 | "zfa", | ||
| 1593 | "zfh", | ||
| 1594 | "zic64b", | ||
| 1595 | "zicbom", | ||
| 1596 | "zicbop", | ||
| 1597 | "zicboz", | ||
| 1598 | "ziccamoa", | ||
| 1599 | "ziccif", | ||
| 1600 | "zicclsm", | ||
| 1601 | "ziccrse", | ||
| 1602 | "zicntr", | ||
| 1603 | "zicond", | ||
| 1604 | "zifencei", | ||
| 1605 | "zihintntl", | ||
| 1606 | "zihintpause", | ||
| 1607 | "zihpm", | ||
| 1608 | "zimop", | ||
| 1609 | "zkt", | ||
| 1610 | "zvbb", | ||
| 1611 | "zvfbfwma", | ||
| 1612 | "zvfh", | ||
| 1613 | "zvkng", | ||
| 1614 | "zvknha", | ||
| 1615 | "zvksc", | ||
| 1616 | "zvksg", | ||
| 1617 | "zvl1024b", | ||
| 1618 | }, | ||
| 1619 | }, | ||
| 1620 | .{ | ||
| 1621 | .llvm_name = null, | ||
| 1622 | .zig_name = "spacemit_x100", | ||
| 1623 | .features = &.{ | ||
| 1624 | "dlen_factor_2", | ||
| 1625 | "optimized_nf2_segment_load_store", | ||
| 1626 | "optimized_nf3_segment_load_store", | ||
| 1627 | "optimized_nf4_segment_load_store", | ||
| 1628 | "rva23s64", | ||
| 1629 | "smepmp", | ||
| 1630 | "smnpm", | ||
| 1631 | "smstateen", | ||
| 1632 | "sspm", | ||
| 1633 | "unaligned_scalar_mem", | ||
| 1634 | "vxrm_pipeline_flush", | ||
| 1635 | "xsmtvdot", | ||
| 1636 | "zbc", | ||
| 1637 | "zbkc", | ||
| 1638 | "zfh", | ||
| 1639 | "zvfbfwma", | ||
| 1640 | "zvfh", | ||
| 1641 | "zvkng", | ||
| 1642 | "zvknha", | ||
| 1643 | "zvksc", | ||
| 1644 | "zvksg", | ||
| 1645 | "zvl256b", | ||
| 1646 | }, | ||
| 1647 | }, | ||
| 1551 | }, | 1648 | }, |
| 1552 | }, | 1649 | }, |
| 1553 | .{ | 1650 | .{ |