Commit 9e5c8cb008f75c2e570a0e48d5d014e936c103ca | zig

author	Jakub Konka <kubkon@jakubkonka.com> 2022-05-16 19:45:30+02:00
committer	Jakub Konka <kubkon@jakubkonka.com> 2022-05-19 19:37:29+02:00
log	9e5c8cb008f75c2e570a0e48d5d014e936c103ca
tree	af9bf9c8457a4137b1fc534e7eac8a0a4400b8ec
parent	2aee2302515ba444999b82c2e40cbc35dee08baf

x64: merge general purpose with simd register into one bitset

This way, we do not have to tweak the `RegisterManager` to handle
multiple register types - we have one linear space instead. Additionally
we can use the bitset itself to separate the registers into overlapping
(the ones that are aliases of differing bitwidths) and nonoverlapping
classes (for example, AVX registers do not overlap general purpose
registers, thus they can be allocated simultaneously).

Another huge benefit of this simple approach is the fact that we can
still refer to *all* registers regardless of their class via enum
literals which makes the code so much more readable.

Finally, `RegisterLock` is universal across different register classes.

7 files changed, 1158 insertions(+), 1397 deletions(-)

src
- arch
  - x86_64
    CodeGen.zig
    Emit.zig
    Mir.zig
    abi.zig
    bits.zig
- codegen.zig
- register_manager.zig

src/arch/x86_64/CodeGen.zig+427-633

 @@ -35,14 +35,10 @@ const caller_preserved_regs = abi.caller_preserved_regs;
 const allocatable_registers = abi.allocatable_registers;
 const c_abi_int_param_regs = abi.c_abi_int_param_regs;
 const c_abi_int_return_regs = abi.c_abi_int_return_regs;
-const RegisterManager = RegisterManagerFn(Self, Register, &allocatable_registers, spillInstruction);
+const RegisterManager = RegisterManagerFn(Self, Register, &allocatable_registers);
 const RegisterLock = RegisterManager.RegisterLock;
 const Register = bits.Register;
-const AvxRegisterManager = RegisterManagerFn(Self, AvxRegister, &abi.avx_regs, spillInstructionAvx);
-const AvxRegisterLock = AvxRegisterManager.RegisterLock;
-const AvxRegister = bits.AvxRegister;
 const InnerError = error{
     OutOfMemory,
     CodegenFail,
 @@ -92,8 +88,7 @@ branch_stack: *std.ArrayList(Branch),
 // Key is the block instruction
 blocks: std.AutoHashMapUnmanaged(Air.Inst.Index, BlockData) = .{},
-register_manager: RegisterManager,
+register_manager: RegisterManager = .{},
-avx_register_manager: AvxRegisterManager,
 /// Maps offset to what is stored there.
 stack: std.AutoHashMapUnmanaged(u32, StackAllocation) = .{},
 @@ -133,8 +128,6 @@ pub const MCValue = union(enum) {
     /// The value is a tuple { wrapped, overflow } where wrapped value is stored in the GP register,
     /// and the operation is a signed operation.
     register_overflow_signed: Register,
-    /// The value is in an AVX register.
-    avx_register: AvxRegister,
     /// The value is in memory at a hard-coded address.
     /// If the type is a pointer, it means the pointer address is at this memory location.
     memory: u64,
 @@ -202,7 +195,6 @@ pub const MCValue = union(enum) {
     fn isRegister(mcv: MCValue) bool {
         return switch (mcv) {
             .register => true,
-            .avx_register => true,
             else => false,
         };
     }
 @@ -304,11 +296,7 @@ pub fn generate(
         .mir_to_air_map = if (builtin.mode == .Debug)
             std.AutoHashMap(Mir.Inst.Index, Air.Inst.Index).init(bin_file.allocator)
         else {},
-        .register_manager = undefined,
-        .avx_register_manager = undefined,
     };
-    function.register_manager = .{ .function = &function };
-    function.avx_register_manager = .{ .function = &function };
     defer function.stack.deinit(bin_file.allocator);
     defer function.blocks.deinit(bin_file.allocator);
     defer function.exitlude_jump_relocs.deinit(bin_file.allocator);
 @@ -400,17 +388,15 @@ fn gen(self: *Self) InnerError!void {
     if (cc != .Naked) {
         _ = try self.addInst(.{
             .tag = .push,
-            .ops = (Mir.Ops(Register, Register){
+            .ops = Mir.Inst.Ops.encode(.{ .reg1 = .rbp }),
-                .reg1 = .rbp,
-            }).encode(),
             .data = undefined, // unused for push reg,
         });
         _ = try self.addInst(.{
             .tag = .mov,
-            .ops = (Mir.Ops(Register, Register){
+            .ops = Mir.Inst.Ops.encode(.{
                 .reg1 = .rbp,
                 .reg2 = .rsp,
-            }).encode(),
+            }),
             .data = undefined,
         });
         // We want to subtract the aligned stack frame size from rsp here, but we don't
 @@ -447,9 +433,7 @@ fn gen(self: *Self) InnerError!void {
         // push the callee_preserved_regs that were used
         const backpatch_push_callee_preserved_regs_i = try self.addInst(.{
             .tag = .push_regs_from_callee_preserved_regs,
-            .ops = (Mir.Ops(Register, Register){
+            .ops = Mir.Inst.Ops.encode(.{ .reg1 = .rbp }),
-                .reg1 = .rbp,
-            }).encode(),
             .data = .{ .payload = undefined }, // to be backpatched
         });
 @@ -489,9 +473,7 @@ fn gen(self: *Self) InnerError!void {
         // pop the callee_preserved_regs
         _ = try self.addInst(.{
             .tag = .pop_regs_from_callee_preserved_regs,
-            .ops = (Mir.Ops(Register, Register){
+            .ops = Mir.Inst.Ops.encode(.{ .reg1 = .rbp }),
-                .reg1 = .rbp,
-            }).encode(),
             .data = .{ .payload = callee_preserved_regs_payload },
         });
 @@ -510,17 +492,13 @@ fn gen(self: *Self) InnerError!void {
         _ = try self.addInst(.{
             .tag = .pop,
-            .ops = (Mir.Ops(Register, Register){
+            .ops = Mir.Inst.Ops.encode(.{ .reg1 = .rbp }),
-                .reg1 = .rbp,
-            }).encode(),
             .data = undefined,
         });
         _ = try self.addInst(.{
             .tag = .ret,
-            .ops = (Mir.Ops(Register, Register){
+            .ops = Mir.Inst.Ops.encode(.{ .flags = 0b11 }),
-                .flags = 0b11,
-            }).encode(),
             .data = undefined,
         });
 @@ -534,16 +512,12 @@ fn gen(self: *Self) InnerError!void {
         if (aligned_stack_end > 0) {
             self.mir_instructions.set(backpatch_stack_sub, .{
                 .tag = .sub,
-                .ops = (Mir.Ops(Register, Register){
+                .ops = Mir.Inst.Ops.encode(.{ .reg1 = .rsp }),
-                    .reg1 = .rsp,
-                }).encode(),
                 .data = .{ .imm = aligned_stack_end },
             });
             self.mir_instructions.set(backpatch_stack_add, .{
                 .tag = .add,
-                .ops = (Mir.Ops(Register, Register){
+                .ops = Mir.Inst.Ops.encode(.{ .reg1 = .rsp }),
-                    .reg1 = .rsp,
-                }).encode(),
                 .data = .{ .imm = aligned_stack_end },
             });
         }
 @@ -908,8 +882,8 @@ fn allocRegOrMem(self: *Self, inst: Air.Inst.Index, reg_ok: bool) !MCValue {
                 // TODO check if AVX available
                 const ptr_bytes: u64 = 32;
                 if (abi_size <= ptr_bytes) {
-                    if (self.avx_register_manager.tryAllocReg(inst)) |reg| {
+                    if (self.register_manager.tryAllocReg(inst)) |reg| {
-                        return MCValue{ .avx_register = avxRegisterAlias(reg, abi_size) };
+                        return MCValue{ .register = registerAlias(reg, abi_size) };
                     }
                 }
             },
 @@ -947,21 +921,6 @@ pub fn spillInstruction(self: *Self, reg: Register, inst: Air.Inst.Index) !void
     try self.genSetStack(self.air.typeOfIndex(inst), stack_mcv.stack_offset, reg_mcv, .{});
 }
-pub fn spillInstructionAvx(self: *Self, reg: AvxRegister, inst: Air.Inst.Index) !void {
-    const stack_mcv = try self.allocRegOrMem(inst, false);
-    log.debug("spilling {d} to stack mcv {any}", .{ inst, stack_mcv });
-    const reg_mcv = self.getResolvedInstValue(inst);
-    switch (reg_mcv) {
-        .avx_register => |other| {
-            assert(reg.to256() == other.to256());
-        },
-        else => {},
-    }
-    const branch = &self.branch_stack.items[self.branch_stack.items.len - 1];
-    try branch.inst_table.put(self.gpa, inst, stack_mcv);
-    try self.genSetStack(self.air.typeOfIndex(inst), stack_mcv.stack_offset, reg_mcv, .{});
-}
 pub fn spillCompareFlagsIfOccupied(self: *Self) !void {
     if (self.compare_flags_inst) |inst_to_save| {
         const mcv = self.getResolvedInstValue(inst_to_save);
 @@ -972,7 +931,6 @@ pub fn spillCompareFlagsIfOccupied(self: *Self) !void {
             .compare_flags_signed,
             .compare_flags_unsigned,
             => try self.allocRegOrMem(inst_to_save, true),
-            .avx_register => try self.allocRegOrMem(inst_to_save, false),
             else => unreachable,
         };
 @@ -990,7 +948,6 @@ pub fn spillCompareFlagsIfOccupied(self: *Self) !void {
             .register_overflow_signed,
             .register_overflow_unsigned,
             => |reg| self.register_manager.freeReg(reg),
-            .avx_register => |reg| self.avx_register_manager.freeReg(reg),
             else => {},
         }
     }
 @@ -1236,10 +1193,10 @@ fn airMin(self: *Self, inst: Air.Inst.Index) !void {
         const dst_mcv = try self.copyToRegisterWithInstTracking(inst, ty, rhs_mcv);
         _ = try self.addInst(.{
             .tag = if (signedness == .signed) .cond_mov_lt else .cond_mov_below,
-            .ops = (Mir.Ops(Register, Register){
+            .ops = Mir.Inst.Ops.encode(.{
                 .reg1 = dst_mcv.register,
                 .reg2 = lhs_reg,
-            }).encode(),
+            }),
             .data = undefined,
         });
 @@ -1440,10 +1397,10 @@ fn genSetStackTruncatedOverflowCompare(
     };
     _ = try self.addInst(.{
         .tag = .cond_set_byte_overflow,
-        .ops = (Mir.Ops(Register, Register){
+        .ops = Mir.Inst.Ops.encode(.{
             .reg1 = overflow_reg.to8(),
             .flags = flags,
-        }).encode(),
+        }),
         .data = undefined,
     });
 @@ -1460,10 +1417,7 @@ fn genSetStackTruncatedOverflowCompare(
     const eq_reg = temp_regs[2];
     _ = try self.addInst(.{
         .tag = .cond_set_byte_eq_ne,
-        .ops = (Mir.Ops(Register, Register){
+        .ops = Mir.Inst.Ops.encode(.{ .reg1 = eq_reg.to8() }),
-            .reg1 = eq_reg.to8(),
-            .flags = 0b00,
-        }).encode(),
         .data = undefined,
     });
 @@ -1609,19 +1563,17 @@ fn genIntMulDivOpMir(
         .signed => {
             _ = try self.addInst(.{
                 .tag = .cwd,
-                .ops = (Mir.Ops(Register, Register){
+                .ops = Mir.Inst.Ops.encode(.{ .flags = 0b11 }),
-                    .flags = 0b11,
-                }).encode(),
                 .data = undefined,
             });
         },
         .unsigned => {
             _ = try self.addInst(.{
                 .tag = .xor,
-                .ops = (Mir.Ops(Register, Register){
+                .ops = Mir.Inst.Ops.encode(.{
                     .reg1 = .rdx,
                     .reg2 = .rdx,
-                }).encode(),
+                }),
                 .data = undefined,
             });
         },
 @@ -1640,16 +1592,14 @@ fn genIntMulDivOpMir(
         .register => |reg| {
             _ = try self.addInst(.{
                 .tag = tag,
-                .ops = (Mir.Ops(Register, Register){
+                .ops = Mir.Inst.Ops.encode(.{ .reg1 = reg }),
-                    .reg1 = reg,
-                }).encode(),
                 .data = undefined,
             });
         },
         .stack_offset => |off| {
             _ = try self.addInst(.{
                 .tag = tag,
-                .ops = (Mir.Ops(Register, Register){
+                .ops = Mir.Inst.Ops.encode(.{
                     .reg2 = .rbp,
                     .flags = switch (abi_size) {
                         1 => 0b00,
 @@ -1658,7 +1608,7 @@ fn genIntMulDivOpMir(
                         8 => 0b11,
                         else => unreachable,
                     },
-                }).encode(),
+                }),
                 .data = .{ .imm = @bitCast(u32, -off) },
             });
         },
 @@ -1691,34 +1641,34 @@ fn genInlineIntDivFloor(self: *Self, ty: Type, lhs: MCValue, rhs: MCValue) !MCVa
     _ = try self.addInst(.{
         .tag = .xor,
-        .ops = (Mir.Ops(Register, Register){
+        .ops = Mir.Inst.Ops.encode(.{
             .reg1 = divisor.to64(),
             .reg2 = dividend.to64(),
-        }).encode(),
+        }),
         .data = undefined,
     });
     _ = try self.addInst(.{
         .tag = .sar,
-        .ops = (Mir.Ops(Register, Register){
+        .ops = Mir.Inst.Ops.encode(.{
             .reg1 = divisor.to64(),
             .flags = 0b10,
-        }).encode(),
+        }),
         .data = .{ .imm = 63 },
     });
     _ = try self.addInst(.{
         .tag = .@"test",
-        .ops = (Mir.Ops(Register, Register){
+        .ops = Mir.Inst.Ops.encode(.{
             .reg1 = .rdx,
             .reg2 = .rdx,
-        }).encode(),
+        }),
         .data = undefined,
     });
     _ = try self.addInst(.{
         .tag = .cond_mov_eq,
-        .ops = (Mir.Ops(Register, Register){
+        .ops = Mir.Inst.Ops.encode(.{
             .reg1 = divisor.to64(),
             .reg2 = .rdx,
-        }).encode(),
+        }),
         .data = undefined,
     });
     try self.genBinOpMir(.add, Type.isize, .{ .register = divisor }, .{ .register = .rax });
 @@ -2102,11 +2052,11 @@ fn genSliceElemPtr(self: *Self, lhs: Air.Inst.Ref, rhs: Air.Inst.Ref) !MCValue {
             // mov reg, [rbp - 8]
             _ = try self.addInst(.{
                 .tag = .mov,
-                .ops = (Mir.Ops(Register, Register){
+                .ops = Mir.Inst.Ops.encode(.{
                     .reg1 = addr_reg.to64(),
                     .reg2 = .rbp,
                     .flags = 0b01,
-                }).encode(),
+                }),
                 .data = .{ .imm = @bitCast(u32, -@intCast(i32, off)) },
             });
         },
 @@ -2187,10 +2137,10 @@ fn airArrayElemVal(self: *Self, inst: Air.Inst.Index) !void {
             // lea reg, [rbp]
             _ = try self.addInst(.{
                 .tag = .lea,
-                .ops = (Mir.Ops(Register, Register){
+                .ops = Mir.Inst.Ops.encode(.{
                     .reg1 = addr_reg.to64(),
                     .reg2 = .rbp,
-                }).encode(),
+                }),
                 .data = .{ .imm = @bitCast(u32, -off) },
             });
         },
 @@ -2198,10 +2148,10 @@ fn airArrayElemVal(self: *Self, inst: Air.Inst.Index) !void {
             // lea reg, [rbp]
             _ = try self.addInst(.{
                 .tag = .lea,
-                .ops = (Mir.Ops(Register, Register){
+                .ops = Mir.Inst.Ops.encode(.{
                     .reg1 = addr_reg.to64(),
                     .reg2 = .rbp,
-                }).encode(),
+                }),
                 .data = .{ .imm = @bitCast(u32, -off) },
             });
         },
 @@ -2266,11 +2216,11 @@ fn airPtrElemVal(self: *Self, inst: Air.Inst.Index) !void {
             // mov dst_mcv, [dst_mcv]
             _ = try self.addInst(.{
                 .tag = .mov,
-                .ops = (Mir.Ops(Register, Register){
+                .ops = Mir.Inst.Ops.encode(.{
-                    .flags = 0b01,
                     .reg1 = registerAlias(dst_mcv.register, @intCast(u32, elem_abi_size)),
                     .reg2 = dst_mcv.register,
-                }).encode(),
+                    .flags = 0b01,
+                }),
                 .data = .{ .imm = 0 },
             });
             break :result .{ .register = registerAlias(dst_mcv.register, @intCast(u32, elem_abi_size)) };
 @@ -2532,11 +2482,11 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
                     // mov dst_reg, [reg]
                     _ = try self.addInst(.{
                         .tag = .mov,
-                        .ops = (Mir.Ops(Register, Register){
+                        .ops = Mir.Inst.Ops.encode(.{
                             .reg1 = registerAlias(dst_reg, @intCast(u32, abi_size)),
                             .reg2 = reg,
                             .flags = 0b01,
-                        }).encode(),
+                        }),
                         .data = .{ .imm = 0 },
                     });
                 },
 @@ -2552,9 +2502,6 @@ fn load(self: *Self, dst_mcv: MCValue, ptr: MCValue, ptr_ty: Type) InnerError!vo
                 else => return self.fail("TODO implement loading from register into {}", .{dst_mcv}),
             }
         },
-        .avx_register => {
-            return self.fail("TODO load for AVX register", .{});
-        },
         .memory,
         .got_load,
         .direct_load,
 @@ -2606,10 +2553,10 @@ fn loadMemPtrIntoRegister(self: *Self, reg: Register, ptr_ty: Type, ptr: MCValue
             const fn_owner_decl = mod.declPtr(self.mod_fn.owner_decl);
             _ = try self.addInst(.{
                 .tag = .lea_pie,
-                .ops = (Mir.Ops(Register, Register){
+                .ops = Mir.Inst.Ops.encode(.{
                     .reg1 = registerAlias(reg, abi_size),
                     .flags = flags,
-                }).encode(),
+                }),
                 .data = .{
                     .load_reloc = .{
                         .atom_index = fn_owner_decl.link.macho.local_sym_index,
 @@ -2670,7 +2617,7 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type
                             });
                             _ = try self.addInst(.{
                                 .tag = .mov_mem_imm,
-                                .ops = (Mir.Ops(Register, Register){
+                                .ops = Mir.Inst.Ops.encode(.{
                                     .reg1 = reg.to64(),
                                     .flags = switch (abi_size) {
                                         1 => 0b00,
 @@ -2678,7 +2625,7 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type
                                         4 => 0b10,
                                         else => unreachable,
                                     },
-                                }).encode(),
+                                }),
                                 .data = .{ .payload = payload },
                             });
                         },
 @@ -2692,11 +2639,11 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type
                             const tmp_reg = try self.copyToTmpRegister(value_ty, value);
                             _ = try self.addInst(.{
                                 .tag = .mov,
-                                .ops = (Mir.Ops(Register, Register){
+                                .ops = Mir.Inst.Ops.encode(.{
                                     .reg1 = reg.to64(),
                                     .reg2 = tmp_reg.to64(),
                                     .flags = 0b10,
-                                }).encode(),
+                                }),
                                 .data = .{ .imm = 0 },
                             });
                         },
 @@ -2708,11 +2655,11 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type
                 .register => |src_reg| {
                     _ = try self.addInst(.{
                         .tag = .mov,
-                        .ops = (Mir.Ops(Register, Register){
+                        .ops = Mir.Inst.Ops.encode(.{
                             .reg1 = reg.to64(),
                             .reg2 = registerAlias(src_reg, @intCast(u32, abi_size)),
                             .flags = 0b10,
-                        }).encode(),
+                        }),
                         .data = .{ .imm = 0 },
                     });
                 },
 @@ -2736,9 +2683,6 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type
                 },
             }
         },
-        .avx_register => {
-            return self.fail("TODO store for AVX register", .{});
-        },
         .got_load,
         .direct_load,
         .memory,
 @@ -2759,11 +2703,11 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type
             // mov reg, [reg]
             _ = try self.addInst(.{
                 .tag = .mov,
-                .ops = (Mir.Ops(Register, Register){
+                .ops = Mir.Inst.Ops.encode(.{
                     .reg1 = addr_reg.to64(),
                     .reg2 = addr_reg.to64(),
                     .flags = 0b01,
-                }).encode(),
+                }),
                 .data = .{ .imm = 0 },
             });
 @@ -2798,21 +2742,21 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type
                     }
                     _ = try self.addInst(.{
                         .tag = .mov_mem_imm,
-                        .ops = (Mir.Ops(Register, Register){
+                        .ops = Mir.Inst.Ops.encode(.{
                             .reg1 = addr_reg.to64(),
                             .flags = flags,
-                        }).encode(),
+                        }),
                         .data = .{ .payload = payload },
                     });
                 },
                 .register => |reg| {
                     _ = try self.addInst(.{
                         .tag = .mov,
-                        .ops = (Mir.Ops(Register, Register){
+                        .ops = Mir.Inst.Ops.encode(.{
                             .reg1 = addr_reg.to64(),
                             .reg2 = reg,
                             .flags = 0b10,
-                        }).encode(),
+                        }),
                         .data = .{ .imm = 0 },
                     });
                 },
 @@ -2829,20 +2773,20 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type
                         _ = try self.addInst(.{
                             .tag = .mov,
-                            .ops = (Mir.Ops(Register, Register){
+                            .ops = Mir.Inst.Ops.encode(.{
                                 .reg1 = tmp_reg,
                                 .reg2 = tmp_reg,
                                 .flags = 0b01,
-                            }).encode(),
+                            }),
                             .data = .{ .imm = 0 },
                         });
                         _ = try self.addInst(.{
                             .tag = .mov,
-                            .ops = (Mir.Ops(Register, Register){
+                            .ops = Mir.Inst.Ops.encode(.{
                                 .reg1 = addr_reg.to64(),
                                 .reg2 = tmp_reg,
                                 .flags = 0b10,
-                            }).encode(),
+                            }),
                             .data = .{ .imm = 0 },
                         });
                         return;
 @@ -2856,11 +2800,11 @@ fn store(self: *Self, ptr: MCValue, value: MCValue, ptr_ty: Type, value_ty: Type
                         const tmp_reg = try self.copyToTmpRegister(value_ty, value);
                         _ = try self.addInst(.{
                             .tag = .mov,
-                            .ops = (Mir.Ops(Register, Register){
+                            .ops = Mir.Inst.Ops.encode(.{
                                 .reg1 = addr_reg.to64(),
                                 .reg2 = tmp_reg,
                                 .flags = 0b10,
-                            }).encode(),
+                            }),
                             .data = .{ .imm = 0 },
                         });
                         return;
 @@ -3017,10 +2961,10 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void {
                 if (signedness == .signed and field_size < 8) {
                     _ = try self.addInst(.{
                         .tag = .mov_sign_extend,
-                        .ops = (Mir.Ops(Register, Register){
+                        .ops = Mir.Inst.Ops.encode(.{
                             .reg1 = dst_mcv.register,
                             .reg2 = registerAlias(dst_mcv.register, field_size),
-                        }).encode(),
+                        }),
                         .data = undefined,
                     });
                 }
 @@ -3048,10 +2992,10 @@ fn airStructFieldVal(self: *Self, inst: Air.Inst.Index) !void {
                         };
                         _ = try self.addInst(.{
                             .tag = .cond_set_byte_overflow,
-                            .ops = (Mir.Ops(Register, Register){
+                            .ops = Mir.Inst.Ops.encode(.{
                                 .reg1 = dst_reg.to8(),
                                 .flags = flags,
-                            }).encode(),
+                            }),
                             .data = undefined,
                         });
                         break :result MCValue{ .register = dst_reg.to8() };
 @@ -3092,10 +3036,7 @@ fn genShiftBinOpMir(self: *Self, tag: Mir.Inst.Tag, ty: Type, reg: Register, shi
                 1 => {
                     _ = try self.addInst(.{
                         .tag = tag,
-                        .ops = (Mir.Ops(Register, Register){
+                        .ops = Mir.Inst.Ops.encode(.{ .reg1 = registerAlias(reg, abi_size) }),
-                            .reg1 = registerAlias(reg, abi_size),
-                            .flags = 0b00,
-                        }).encode(),
                         .data = undefined,
                     });
                     return;
 @@ -3103,10 +3044,10 @@ fn genShiftBinOpMir(self: *Self, tag: Mir.Inst.Tag, ty: Type, reg: Register, shi
                 else => {
                     _ = try self.addInst(.{
                         .tag = tag,
-                        .ops = (Mir.Ops(Register, Register){
+                        .ops = Mir.Inst.Ops.encode(.{
                             .reg1 = registerAlias(reg, abi_size),
                             .flags = 0b10,
-                        }).encode(),
+                        }),
                         .data = .{ .imm = @intCast(u8, imm) },
                     });
                     return;
 @@ -3124,10 +3065,10 @@ fn genShiftBinOpMir(self: *Self, tag: Mir.Inst.Tag, ty: Type, reg: Register, shi
     _ = try self.addInst(.{
         .tag = tag,
-        .ops = (Mir.Ops(Register, Register){
+        .ops = Mir.Inst.Ops.encode(.{
             .reg1 = registerAlias(reg, abi_size),
             .flags = 0b01,
-        }).encode(),
+        }),
         .data = undefined,
     });
 }
 @@ -3383,32 +3324,6 @@ fn genBinOp(
         return self.fail("TODO implement genBinOp for {}", .{lhs_ty.fmtDebug()});
     }
-    if (lhs_ty.zigTypeTag() == .Float) {
-        switch (tag) {
-            .add => {
-                const dst_reg: AvxRegister = blk: {
-                    const reg = try self.avx_register_manager.allocReg(null);
-                    try self.genSetAvxReg(lhs_ty, reg, lhs);
-                    break :blk reg.to128();
-                };
-                const dst_lock = self.avx_register_manager.lockRegAssumeUnused(dst_reg);
-                defer self.avx_register_manager.unlockReg(dst_lock);
-                const src_reg: AvxRegister = blk: {
-                    const reg = try self.avx_register_manager.allocReg(null);
-                    try self.genSetAvxReg(lhs_ty, reg, rhs);
-                    break :blk reg.to128();
-                };
-                const src_lock = self.avx_register_manager.lockRegAssumeUnused(src_reg);
-                defer self.avx_register_manager.unlockReg(src_lock);
-                try self.genBinOpMir(.add_f64, lhs_ty, .{ .avx_register = dst_reg }, .{ .avx_register = src_reg });
-                return MCValue{ .avx_register = dst_reg };
-            },
-            else => unreachable,
-        }
-    }
     const is_commutative: bool = switch (tag) {
         .add,
         .addwrap,
 @@ -3526,25 +3441,39 @@ fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, dst_ty: Type, dst_mcv: MCValu
                     const reg = try self.copyToTmpRegister(dst_ty, src_mcv);
                     return self.genBinOpMir(mir_tag, dst_ty, dst_mcv, .{ .register = reg });
                 },
-                .register => |src_reg| {
+                .register => |src_reg| switch (dst_ty.zigTypeTag()) {
-                    _ = try self.addInst(.{
+                    .Float => switch (dst_ty.tag()) {
-                        .tag = mir_tag,
+                        .f64 => {
-                        .ops = (Mir.Ops(Register, Register){
+                            _ = try self.addInst(.{
-                            .reg1 = registerAlias(dst_reg, abi_size),
+                                .tag = switch (mir_tag) {
-                            .reg2 = registerAlias(src_reg, abi_size),
+                                    .add => .add_f64,
-                        }).encode(),
+                                    .cmp => .cmp_f64,
-                        .data = undefined,
+                                    else => return self.fail("TODO genBinOpMir for f64 register-register with MIR tag {}", .{mir_tag}),
-                    });
+                                },
-                },
+                                .ops = Mir.Inst.Ops.encode(.{
-                .avx_register => {
+                                    .reg1 = dst_reg.to128(),
-                    return self.fail("TODO genBinOp for AVX register", .{});
+                                    .reg2 = src_reg.to128(),
+                                }),
+                                .data = undefined,
+                            });
+                        },
+                        else => return self.fail("TODO genBinOpMir for float register-register and type {}", .{dst_ty.fmtDebug()}),
+                    },
+                    else => {
+                        _ = try self.addInst(.{
+                            .tag = mir_tag,
+                            .ops = Mir.Inst.Ops.encode(.{
+                                .reg1 = registerAlias(dst_reg, abi_size),
+                                .reg2 = registerAlias(src_reg, abi_size),
+                            }),
+                            .data = undefined,
+                        });
+                    },
                 },
                 .immediate => |imm| {
                     _ = try self.addInst(.{
                         .tag = mir_tag,
-                        .ops = (Mir.Ops(Register, Register){
+                        .ops = Mir.Inst.Ops.encode(.{ .reg1 = registerAlias(dst_reg, abi_size) }),
-                            .reg1 = registerAlias(dst_reg, abi_size),
-                        }).encode(),
                         .data = .{ .imm = @truncate(u32, imm) },
                     });
                 },
 @@ -3567,39 +3496,16 @@ fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, dst_ty: Type, dst_mcv: MCValu
                     }
                     _ = try self.addInst(.{
                         .tag = mir_tag,
-                        .ops = (Mir.Ops(Register, Register){
+                        .ops = Mir.Inst.Ops.encode(.{
                             .reg1 = registerAlias(dst_reg, abi_size),
                             .reg2 = .rbp,
                             .flags = 0b01,
-                        }).encode(),
+                        }),
                         .data = .{ .imm = @bitCast(u32, -off) },
                     });
                 },
             }
         },
-        .avx_register => |dst_reg| {
-            switch (src_mcv) {
-                .avx_register => |src_reg| {
-                    switch (dst_ty.zigTypeTag()) {
-                        .Float => switch (dst_ty.tag()) {
-                            .f64 => {
-                                _ = try self.addInst(.{
-                                    .tag = mir_tag,
-                                    .ops = (Mir.Ops(AvxRegister, AvxRegister){
-                                        .reg1 = dst_reg.to128(),
-                                        .reg2 = src_reg.to128(),
-                                    }).encode(),
-                                    .data = undefined,
-                                });
-                            },
-                            else => return self.fail("TODO genBinOp for AVX register and type {}", .{dst_ty.fmtDebug()}),
-                        },
-                        else => return self.fail("TODO genBinOp for AVX register and type {}", .{dst_ty.fmtDebug()}),
-                    }
-                },
-                else => return self.fail("TODO genBinOp for AVX register", .{}),
-            }
-        },
         .ptr_stack_offset, .stack_offset => |off| {
             if (off > math.maxInt(i32)) {
                 return self.fail("stack offset too large", .{});
 @@ -3617,17 +3523,14 @@ fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, dst_ty: Type, dst_mcv: MCValu
                 .register => |src_reg| {
                     _ = try self.addInst(.{
                         .tag = mir_tag,
-                        .ops = (Mir.Ops(Register, Register){
+                        .ops = Mir.Inst.Ops.encode(.{
                             .reg1 = .rbp,
                             .reg2 = registerAlias(src_reg, abi_size),
                             .flags = 0b10,
-                        }).encode(),
+                        }),
                         .data = .{ .imm = @bitCast(u32, -off) },
                     });
                 },
-                .avx_register => {
-                    return self.fail("TODO genBinOp for AVX register", .{});
-                },
                 .immediate => |imm| {
                     const tag: Mir.Inst.Tag = switch (mir_tag) {
                         .add => .add_mem_imm,
 @@ -3651,10 +3554,10 @@ fn genBinOpMir(self: *Self, mir_tag: Mir.Inst.Tag, dst_ty: Type, dst_mcv: MCValu
                     });
                     _ = try self.addInst(.{
                         .tag = tag,
-                        .ops = (Mir.Ops(Register, Register){
+                        .ops = Mir.Inst.Ops.encode(.{
                             .reg1 = .rbp,
                             .flags = flags,
-                        }).encode(),
+                        }),
                         .data = .{ .payload = payload },
                     });
                 },
 @@ -3697,7 +3600,6 @@ fn genIntMulComplexOpMir(self: *Self, dst_ty: Type, dst_mcv: MCValue, src_mcv: M
         .ptr_stack_offset => unreachable,
         .register_overflow_unsigned => unreachable,
         .register_overflow_signed => unreachable,
-        .avx_register => unreachable,
         .register => |dst_reg| {
             switch (src_mcv) {
                 .none => unreachable,
 @@ -3706,15 +3608,14 @@ fn genIntMulComplexOpMir(self: *Self, dst_ty: Type, dst_mcv: MCValue, src_mcv: M
                 .ptr_stack_offset => unreachable,
                 .register_overflow_unsigned => unreachable,
                 .register_overflow_signed => unreachable,
-                .avx_register => unreachable,
                 .register => |src_reg| {
                     // register, register
                     _ = try self.addInst(.{
                         .tag = .imul_complex,
-                        .ops = (Mir.Ops(Register, Register){
+                        .ops = Mir.Inst.Ops.encode(.{
                             .reg1 = registerAlias(dst_reg, abi_size),
                             .reg2 = registerAlias(src_reg, abi_size),
-                        }).encode(),
+                        }),
                         .data = undefined,
                     });
                 },
 @@ -3724,11 +3625,11 @@ fn genIntMulComplexOpMir(self: *Self, dst_ty: Type, dst_mcv: MCValue, src_mcv: M
                     if (math.minInt(i32) <= imm and imm <= math.maxInt(i32)) {
                         _ = try self.addInst(.{
                             .tag = .imul_complex,
-                            .ops = (Mir.Ops(Register, Register){
+                            .ops = Mir.Inst.Ops.encode(.{
                                 .reg1 = dst_reg.to32(),
                                 .reg2 = dst_reg.to32(),
                                 .flags = 0b10,
-                            }).encode(),
+                            }),
                             .data = .{ .imm = @truncate(u32, imm) },
                         });
                     } else {
 @@ -3740,11 +3641,11 @@ fn genIntMulComplexOpMir(self: *Self, dst_ty: Type, dst_mcv: MCValue, src_mcv: M
                 .stack_offset => |off| {
                     _ = try self.addInst(.{
                         .tag = .imul_complex,
-                        .ops = (Mir.Ops(Register, Register){
+                        .ops = Mir.Inst.Ops.encode(.{
                             .reg1 = registerAlias(dst_reg, abi_size),
                             .reg2 = .rbp,
                             .flags = 0b01,
-                        }).encode(),
+                        }),
                         .data = .{ .imm = @bitCast(u32, -off) },
                     });
                 },
 @@ -3770,7 +3671,6 @@ fn genIntMulComplexOpMir(self: *Self, dst_ty: Type, dst_mcv: MCValue, src_mcv: M
                 .ptr_stack_offset => unreachable,
                 .register_overflow_unsigned => unreachable,
                 .register_overflow_signed => unreachable,
-                .avx_register => unreachable,
                 .register => |src_reg| {
                     // copy dst to a register
                     const dst_reg = try self.copyToTmpRegister(dst_ty, dst_mcv);
 @@ -3778,10 +3678,10 @@ fn genIntMulComplexOpMir(self: *Self, dst_ty: Type, dst_mcv: MCValue, src_mcv: M
                     // register, register
                     _ = try self.addInst(.{
                         .tag = .imul_complex,
-                        .ops = (Mir.Ops(Register, Register){
+                        .ops = Mir.Inst.Ops.encode(.{
                             .reg1 = registerAlias(dst_reg, abi_size),
                             .reg2 = registerAlias(src_reg, abi_size),
-                        }).encode(),
+                        }),
                         .data = undefined,
                     });
                     // copy dst_reg back out
 @@ -3888,9 +3788,7 @@ fn airArg(self: *Self, inst: Air.Inst.Index) !void {
 fn airBreakpoint(self: *Self) !void {
     _ = try self.addInst(.{
         .tag = .interrupt,
-        .ops = (Mir.Ops{
+        .ops = Mir.Inst.Ops.encode(.{}),
-            .flags = 0b00,
-        }).encode(),
         .data = undefined,
     });
     return self.finishAirBookkeeping();
 @@ -3973,9 +3871,6 @@ fn airCall(self: *Self, inst: Air.Inst.Index, modifier: std.builtin.CallOptions.
             .ptr_stack_offset => {
                 return self.fail("TODO implement calling with MCValue.ptr_stack_offset arg", .{});
             },
-            .avx_register => {
-                return self.fail("TODO implement calling with MCValue.avx_register arg", .{});
-            },
             .undef => unreachable,
             .immediate => unreachable,
             .unreach => unreachable,
 @@ -3994,9 +3889,7 @@ fn airCall(self: *Self, inst: Air.Inst.Index, modifier: std.builtin.CallOptions.
         // Adjust the stack
         _ = try self.addInst(.{
             .tag = .sub,
-            .ops = (Mir.Ops(Register, Register){
+            .ops = Mir.Inst.Ops.encode(.{ .reg1 = .rsp }),
-                .reg1 = .rsp,
-            }).encode(),
             .data = .{ .imm = info.stack_byte_count },
         });
     }
 @@ -4020,9 +3913,7 @@ fn airCall(self: *Self, inst: Air.Inst.Index, modifier: std.builtin.CallOptions.
                     unreachable;
                 _ = try self.addInst(.{
                     .tag = .call,
-                    .ops = (Mir.Ops(Register, Register){
+                    .ops = Mir.Inst.Ops.encode(.{ .flags = 0b01 }),
-                        .flags = 0b01,
-                    }).encode(),
                     .data = .{ .imm = @truncate(u32, got_addr) },
                 });
             } else if (func_value.castTag(.extern_fn)) |_| {
 @@ -4036,10 +3927,10 @@ fn airCall(self: *Self, inst: Air.Inst.Index, modifier: std.builtin.CallOptions.
             try self.genSetReg(Type.initTag(.usize), .rax, mcv);
             _ = try self.addInst(.{
                 .tag = .call,
-                .ops = (Mir.Ops(Register, Register){
+                .ops = Mir.Inst.Ops.encode(.{
                     .reg1 = .rax,
                     .flags = 0b01,
-                }).encode(),
+                }),
                 .data = undefined,
             });
         }
 @@ -4054,10 +3945,10 @@ fn airCall(self: *Self, inst: Air.Inst.Index, modifier: std.builtin.CallOptions.
                 // callq *%rax
                 _ = try self.addInst(.{
                     .tag = .call,
-                    .ops = (Mir.Ops(Register, Register){
+                    .ops = Mir.Inst.Ops.encode(.{
                         .reg1 = .rax,
                         .flags = 0b01,
-                    }).encode(),
+                    }),
                     .data = undefined,
                 });
             } else if (func_value.castTag(.extern_fn)) |func_payload| {
 @@ -4089,10 +3980,10 @@ fn airCall(self: *Self, inst: Air.Inst.Index, modifier: std.builtin.CallOptions.
             try self.genSetReg(Type.initTag(.usize), .rax, mcv);
             _ = try self.addInst(.{
                 .tag = .call,
-                .ops = (Mir.Ops(Register, Register){
+                .ops = Mir.Inst.Ops.encode(.{
                     .reg1 = .rax,
                     .flags = 0b01,
-                }).encode(),
+                }),
                 .data = undefined,
             });
         }
 @@ -4107,9 +3998,7 @@ fn airCall(self: *Self, inst: Air.Inst.Index, modifier: std.builtin.CallOptions.
                 const fn_got_addr = got_addr + got_index * ptr_bytes;
                 _ = try self.addInst(.{
                     .tag = .call,
-                    .ops = (Mir.Ops(Register, Register){
+                    .ops = Mir.Inst.Ops.encode(.{ .flags = 0b01 }),
-                        .flags = 0b01,
-                    }).encode(),
                     .data = .{ .imm = @intCast(u32, fn_got_addr) },
                 });
             } else return self.fail("TODO implement calling extern fn on plan9", .{});
 @@ -4119,10 +4008,10 @@ fn airCall(self: *Self, inst: Air.Inst.Index, modifier: std.builtin.CallOptions.
             try self.genSetReg(Type.initTag(.usize), .rax, mcv);
             _ = try self.addInst(.{
                 .tag = .call,
-                .ops = (Mir.Ops(Register, Register){
+                .ops = Mir.Inst.Ops.encode(.{
                     .reg1 = .rax,
                     .flags = 0b01,
-                }).encode(),
+                }),
                 .data = undefined,
             });
         }
 @@ -4132,9 +4021,7 @@ fn airCall(self: *Self, inst: Air.Inst.Index, modifier: std.builtin.CallOptions.
         // Readjust the stack
         _ = try self.addInst(.{
             .tag = .add,
-            .ops = (Mir.Ops(Register, Register){
+            .ops = Mir.Inst.Ops.encode(.{ .reg1 = .rsp }),
-                .reg1 = .rsp,
-            }).encode(),
             .data = .{ .imm = info.stack_byte_count },
         });
     }
 @@ -4192,9 +4079,7 @@ fn airRet(self: *Self, inst: Air.Inst.Index) !void {
     // which is available if the jump is 127 bytes or less forward.
     const jmp_reloc = try self.addInst(.{
         .tag = .jmp,
-        .ops = (Mir.Ops(Register, Register){
+        .ops = Mir.Inst.Ops.encode(.{}),
-            .flags = 0b00,
-        }).encode(),
         .data = .{ .inst = undefined },
     });
     try self.exitlude_jump_relocs.append(self.gpa, jmp_reloc);
 @@ -4227,9 +4112,7 @@ fn airRetLoad(self: *Self, inst: Air.Inst.Index) !void {
     // which is available if the jump is 127 bytes or less forward.
     const jmp_reloc = try self.addInst(.{
         .tag = .jmp,
-        .ops = (Mir.Ops(Register, Register){
+        .ops = Mir.Inst.Ops.encode(.{}),
-            .flags = 0b00,
-        }).encode(),
         .data = .{ .inst = undefined },
     });
     try self.exitlude_jump_relocs.append(self.gpa, jmp_reloc);
 @@ -4256,37 +4139,6 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
     self.compare_flags_inst = inst;
     const result: MCValue = result: {
-        if (ty.zigTypeTag() == .Float) {
-            const lhs = try self.resolveInst(bin_op.lhs);
-            const rhs = try self.resolveInst(bin_op.rhs);
-            const dst_reg: AvxRegister = blk: {
-                const reg = try self.avx_register_manager.allocReg(null);
-                try self.genSetAvxReg(ty, reg, lhs);
-                break :blk reg.to128();
-            };
-            const dst_lock = self.avx_register_manager.lockRegAssumeUnused(dst_reg);
-            defer self.avx_register_manager.unlockReg(dst_lock);
-            const src_reg: AvxRegister = blk: {
-                const reg = try self.avx_register_manager.allocReg(null);
-                try self.genSetAvxReg(ty, reg, rhs);
-                break :blk reg.to128();
-            };
-            const src_lock = self.avx_register_manager.lockRegAssumeUnused(src_reg);
-            defer self.avx_register_manager.unlockReg(src_lock);
-            _ = try self.addInst(.{
-                .tag = .cmp_f64,
-                .ops = (Mir.Ops(AvxRegister, AvxRegister){
-                    .reg1 = dst_reg,
-                    .reg2 = src_reg,
-                }).encode(),
-                .data = undefined,
-            });
-            break :result MCValue{ .compare_flags_unsigned = op };
-        }
         // There are 2 operands, destination and source.
         // Either one, but not both, can be a memory operand.
         // Source operand can be an immediate, 8 bits or 32 bits.
 @@ -4304,8 +4156,28 @@ fn airCmp(self: *Self, inst: Air.Inst.Index, op: math.CompareOperator) !void {
         const dst_mcv = MCValue{ .register = dst_reg };
+        const rhs_ty = self.air.typeOf(bin_op.rhs);
         // This instruction supports only signed 32-bit immediates at most.
-        const src_mcv = try self.limitImmediateType(bin_op.rhs, i32);
+        const src_mcv: MCValue = blk: {
+            switch (rhs_ty.zigTypeTag()) {
+                .Float => {
+                    const rhs = try self.resolveInst(bin_op.rhs);
+                    const rhs_lock: ?RegisterLock = switch (rhs) {
+                        .register => |reg| self.register_manager.lockRegAssumeUnused(reg),
+                        else => null,
+                    };
+                    defer if (rhs_lock) |lock| self.register_manager.unlockReg(lock);
+                    const src_reg = try self.copyToTmpRegister(rhs_ty, rhs);
+                    break :blk MCValue{ .register = src_reg };
+                },
+                else => break :blk try self.limitImmediateType(bin_op.rhs, i32),
+            }
+        };
+        const src_lock: ?RegisterLock = switch (src_mcv) {
+            .register => |reg| self.register_manager.lockReg(reg),
+            else => null,
+        };
+        defer if (src_lock) |lock| self.register_manager.unlockReg(lock);
         try self.genBinOpMir(.cmp, ty, dst_mcv, src_mcv);
         break :result switch (signedness) {
 @@ -4504,9 +4376,7 @@ fn genCondBrMir(self: *Self, ty: Type, mcv: MCValue) !u32 {
                 Mir.Inst.Tag.cond_jmp_greater_less;
             return self.addInst(.{
                 .tag = tag,
-                .ops = (Mir.Ops(Register, Register){
+                .ops = Mir.Inst.Ops.encode(.{ .flags = flags }),
-                    .flags = flags,
-                }).encode(),
                 .data = .{ .inst = undefined },
             });
         },
 @@ -4514,17 +4384,12 @@ fn genCondBrMir(self: *Self, ty: Type, mcv: MCValue) !u32 {
             try self.spillCompareFlagsIfOccupied();
             _ = try self.addInst(.{
                 .tag = .@"test",
-                .ops = (Mir.Ops(Register, Register){
+                .ops = Mir.Inst.Ops.encode(.{ .reg1 = reg }),
-                    .reg1 = reg,
-                    .flags = 0b00,
-                }).encode(),
                 .data = .{ .imm = 1 },
             });
             return self.addInst(.{
                 .tag = .cond_jmp_eq_ne,
-                .ops = (Mir.Ops(Register, Register){
+                .ops = Mir.Inst.Ops.encode(.{ .flags = 0b01 }),
-                    .flags = 0b01,
-                }).encode(),
                 .data = .{ .inst = undefined },
             });
         },
 @@ -4918,9 +4783,7 @@ fn airLoop(self: *Self, inst: Air.Inst.Index) !void {
     try self.genBody(body);
     _ = try self.addInst(.{
         .tag = .jmp,
-        .ops = (Mir.Ops(Register, Register){
+        .ops = Mir.Inst.Ops.encode(.{}),
-            .flags = 0b00,
-        }).encode(),
         .data = .{ .inst = jmp_target },
     });
     return self.finishAirBookkeeping();
 @@ -4971,19 +4834,17 @@ fn genCondSwitchMir(self: *Self, ty: Type, condition: MCValue, case: MCValue) !u
                 .immediate => |imm| {
                     _ = try self.addInst(.{
                         .tag = .xor,
-                        .ops = (Mir.Ops(Register, Register){
+                        .ops = Mir.Inst.Ops.encode(.{ .reg1 = registerAlias(cond_reg, abi_size) }),
-                            .reg1 = registerAlias(cond_reg, abi_size),
-                        }).encode(),
                         .data = .{ .imm = @intCast(u32, imm) },
                     });
                 },
                 .register => |reg| {
                     _ = try self.addInst(.{
                         .tag = .xor,
-                        .ops = (Mir.Ops(Register, Register){
+                        .ops = Mir.Inst.Ops.encode(.{
                             .reg1 = registerAlias(cond_reg, abi_size),
                             .reg2 = registerAlias(reg, abi_size),
-                        }).encode(),
+                        }),
                         .data = undefined,
                     });
                 },
 @@ -5002,17 +4863,15 @@ fn genCondSwitchMir(self: *Self, ty: Type, condition: MCValue, case: MCValue) !u
             _ = try self.addInst(.{
                 .tag = .@"test",
-                .ops = (Mir.Ops(Register, Register){
+                .ops = Mir.Inst.Ops.encode(.{
                     .reg1 = registerAlias(cond_reg, abi_size),
                     .reg2 = registerAlias(cond_reg, abi_size),
-                }).encode(),
+                }),
                 .data = undefined,
             });
             return self.addInst(.{
                 .tag = .cond_jmp_eq_ne,
-                .ops = (Mir.Ops(Register, Register){
+                .ops = Mir.Inst.Ops.encode(.{}),
-                    .flags = 0b00,
-                }).encode(),
                 .data = .{ .inst = undefined },
             });
         },
 @@ -5156,17 +5015,20 @@ fn br(self: *Self, block: Air.Inst.Index, operand: Air.Inst.Ref) !void {
         if (block_mcv == .none) {
             block_data.mcv = switch (operand_mcv) {
                 .none, .dead, .unreach => unreachable,
-                .register, .stack_offset, .memory => operand_mcv,
+                .stack_offset, .memory => operand_mcv,
                 .compare_flags_signed, .compare_flags_unsigned, .immediate => blk: {
                     const new_mcv = try self.allocRegOrMem(block, true);
                     try self.setRegOrMem(self.air.typeOfIndex(block), new_mcv, operand_mcv);
                     break :blk new_mcv;
                 },
-                .avx_register => blk: {
+                .register => blk: {
-                    // TODO not needed; return operand_mcv ones we can transfer between XMM registers
+                    if (self.air.typeOfIndex(block).zigTypeTag() == .Float) {
-                    const new_mcv = try self.allocRegOrMem(block, false);
+                        // TODO not needed; return operand_mcv ones we can transfer between XMM registers
-                    try self.setRegOrMem(self.air.typeOfIndex(block), new_mcv, operand_mcv);
+                        const new_mcv = try self.allocRegOrMem(block, false);
-                    break :blk new_mcv;
+                        try self.setRegOrMem(self.air.typeOfIndex(block), new_mcv, operand_mcv);
+                        break :blk new_mcv;
+                    }
+                    break :blk operand_mcv;
                 },
                 else => return self.fail("TODO implement block_data.mcv = operand_mcv for {}", .{operand_mcv}),
             };
 @@ -5184,9 +5046,7 @@ fn brVoid(self: *Self, block: Air.Inst.Index) !void {
     // Leave the jump offset undefined
     const jmp_reloc = try self.addInst(.{
         .tag = .jmp,
-        .ops = (Mir.Ops(Register, Register){
+        .ops = Mir.Inst.Ops.encode(.{}),
-            .flags = 0b00,
-        }).encode(),
         .data = .{ .inst = undefined },
     });
     block_data.relocs.appendAssumeCapacity(jmp_reloc);
 @@ -5274,9 +5134,7 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
                         };
                         _ = try self.addInst(.{
                             .tag = .push,
-                            .ops = (Mir.Ops(Register, Register){
+                            .ops = Mir.Inst.Ops.encode(.{ .flags = 0b10 }),
-                                .flags = 0b10,
-                            }).encode(),
                             .data = .{ .imm = n },
                         });
                     } else if (mem.indexOf(u8, arg, "%%")) |l| {
 @@ -5285,9 +5143,7 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
                             return self.fail("unrecognized register: '{s}'", .{reg_name});
                         _ = try self.addInst(.{
                             .tag = .push,
-                            .ops = (Mir.Ops(Register, Register){
+                            .ops = Mir.Inst.Ops.encode(.{ .reg1 = reg }),
-                                .reg1 = reg,
-                            }).encode(),
                             .data = undefined,
                         });
                     } else return self.fail("TODO more push operands", .{});
 @@ -5299,9 +5155,7 @@ fn airAsm(self: *Self, inst: Air.Inst.Index) !void {
                             return self.fail("unrecognized register: '{s}'", .{reg_name});
                         _ = try self.addInst(.{
                             .tag = .pop,
-                            .ops = (Mir.Ops(Register, Register){
+                            .ops = Mir.Inst.Ops.encode(.{ .reg1 = reg }),
-                                .reg1 = reg,
-                            }).encode(),
                             .data = undefined,
                         });
                     } else return self.fail("TODO more pop operands", .{});
 @@ -5365,7 +5219,6 @@ fn setRegOrMem(self: *Self, ty: Type, loc: MCValue, val: MCValue) !void {
         .none => return,
         .immediate => unreachable,
         .register => |reg| return self.genSetReg(ty, reg, val),
-        .avx_register => |reg| return self.genSetAvxReg(ty, reg, val),
         .stack_offset => |off| return self.genSetStack(ty, off, val, .{}),
         .memory => {
             return self.fail("TODO implement setRegOrMem for memory", .{});
 @@ -5396,9 +5249,6 @@ fn genSetStackArg(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue) InnerE
         .register_overflow_unsigned,
         .register_overflow_signed,
         => return self.fail("TODO genSetStackArg for register with overflow bit", .{}),
-        .avx_register => {
-            return self.fail("TODO genSetStackArg for AVX register", .{});
-        },
         .compare_flags_unsigned,
         .compare_flags_signed,
         => {
 @@ -5417,7 +5267,7 @@ fn genSetStackArg(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue) InnerE
                     });
                     _ = try self.addInst(.{
                         .tag = .mov_mem_imm,
-                        .ops = (Mir.Ops(Register, Register){
+                        .ops = Mir.Inst.Ops.encode(.{
                             .reg1 = .rsp,
                             .flags = switch (abi_size) {
                                 1 => 0b00,
 @@ -5425,7 +5275,7 @@ fn genSetStackArg(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue) InnerE
                                 4 => 0b10,
                                 else => unreachable,
                             },
-                        }).encode(),
+                        }),
                         .data = .{ .payload = payload },
                     });
                 },
 @@ -5453,11 +5303,11 @@ fn genSetStackArg(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue) InnerE
         .register => |reg| {
             _ = try self.addInst(.{
                 .tag = .mov,
-                .ops = (Mir.Ops(Register, Register){
+                .ops = Mir.Inst.Ops.encode(.{
                     .reg1 = .rsp,
                     .reg2 = registerAlias(reg, @intCast(u32, abi_size)),
                     .flags = 0b10,
-                }).encode(),
+                }),
                 .data = .{ .imm = @bitCast(u32, -stack_offset) },
             });
         },
 @@ -5520,10 +5370,10 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue, opts: Inl
             };
             _ = try self.addInst(.{
                 .tag = .cond_set_byte_overflow,
-                .ops = (Mir.Ops(Register, Register){
+                .ops = Mir.Inst.Ops.encode(.{
                     .reg1 = tmp_reg.to8(),
                     .flags = flags,
-                }).encode(),
+                }),
                 .data = undefined,
             });
 @@ -5550,7 +5400,7 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue, opts: Inl
                     });
                     _ = try self.addInst(.{
                         .tag = .mov_mem_imm,
-                        .ops = (Mir.Ops(Register, Register){
+                        .ops = Mir.Inst.Ops.encode(.{
                             .reg1 = base_reg,
                             .flags = switch (abi_size) {
                                 1 => 0b00,
 @@ -5558,7 +5408,7 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue, opts: Inl
                                 4 => 0b10,
                                 else => unreachable,
                             },
-                        }).encode(),
+                        }),
                         .data = .{ .payload = payload },
                     });
                 },
 @@ -5572,10 +5422,10 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue, opts: Inl
                         });
                         _ = try self.addInst(.{
                             .tag = .mov_mem_imm,
-                            .ops = (Mir.Ops(Register, Register){
+                            .ops = Mir.Inst.Ops.encode(.{
                                 .reg1 = base_reg,
                                 .flags = 0b10,
-                            }).encode(),
+                            }),
                             .data = .{ .payload = payload },
                         });
                     }
 @@ -5586,10 +5436,10 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue, opts: Inl
                         });
                         _ = try self.addInst(.{
                             .tag = .mov_mem_imm,
-                            .ops = (Mir.Ops(Register, Register){
+                            .ops = Mir.Inst.Ops.encode(.{
                                 .reg1 = base_reg,
                                 .flags = 0b10,
-                            }).encode(),
+                            }),
                             .data = .{ .payload = payload },
                         });
                     }
 @@ -5605,65 +5455,64 @@ fn genSetStack(self: *Self, ty: Type, stack_offset: i32, mcv: MCValue, opts: Inl
             }
             const base_reg = opts.dest_stack_base orelse .rbp;
-            if (!math.isPowerOfTwo(abi_size)) {
-                const reg_lock = self.register_manager.lockReg(reg);
-                defer if (reg_lock) |lock| self.register_manager.unlockReg(lock);
-                const tmp_reg = try self.copyToTmpRegister(ty, mcv);
-                var next_offset = stack_offset;
-                var remainder = abi_size;
-                while (remainder > 0) {
-                    const nearest_power_of_two = @as(u6, 1) << math.log2_int(u3, @intCast(u3, remainder));
-                    _ = try self.addInst(.{
-                        .tag = .mov,
-                        .ops = (Mir.Ops(Register, Register){
-                            .reg1 = base_reg,
-                            .reg2 = registerAlias(tmp_reg, nearest_power_of_two),
-                            .flags = 0b10,
-                        }).encode(),
-                        .data = .{ .imm = @bitCast(u32, -next_offset) },
-                    });
-                    if (nearest_power_of_two > 1) {
-                        try self.genShiftBinOpMir(.shr, ty, tmp_reg, .{ .immediate = nearest_power_of_two * 8 });
-                    }
-                    remainder -= nearest_power_of_two;
-                    next_offset -= nearest_power_of_two;
-                }
-            } else {
-                _ = try self.addInst(.{
-                    .tag = .mov,
-                    .ops = (Mir.Ops(Register, Register){
-                        .reg1 = base_reg,
-                        .reg2 = registerAlias(reg, @intCast(u32, abi_size)),
-                        .flags = 0b10,
-                    }).encode(),
-                    .data = .{ .imm = @bitCast(u32, -stack_offset) },
-                });
-            }
-        },
-        .avx_register => |reg| {
-            const base_reg = opts.dest_stack_base orelse .rbp;
             switch (ty.zigTypeTag()) {
                 .Float => switch (ty.tag()) {
-                    .f32 => return self.fail("TODO genSetStack for AVX register for f32", .{}),
+                    .f32 => return self.fail("TODO genSetStack for register for f32", .{}),
                     .f64 => {
                         _ = try self.addInst(.{
                             .tag = .mov_f64,
-                            .ops = (Mir.Ops(Register, AvxRegister){
+                            .ops = Mir.Inst.Ops.encode(.{
                                 .reg1 = base_reg,
                                 .reg2 = reg.to128(),
                                 .flags = 0b01,
-                            }).encode(),
+                            }),
                             .data = .{ .imm = @bitCast(u32, -stack_offset) },
                         });
                     },
-                    else => return self.fail("TODO genSetStack for AVX register for type {}", .{ty.fmtDebug()}),
+                    else => return self.fail("TODO genSetStack for register for type {}", .{ty.fmtDebug()}),
+                },
+                else => {
+                    if (!math.isPowerOfTwo(abi_size)) {
+                        const reg_lock = self.register_manager.lockReg(reg);
+                        defer if (reg_lock) |lock| self.register_manager.unlockReg(lock);
+                        const tmp_reg = try self.copyToTmpRegister(ty, mcv);
+                        var next_offset = stack_offset;
+                        var remainder = abi_size;
+                        while (remainder > 0) {
+                            const nearest_power_of_two = @as(u6, 1) << math.log2_int(u3, @intCast(u3, remainder));
+                            _ = try self.addInst(.{
+                                .tag = .mov,
+                                .ops = Mir.Inst.Ops.encode(.{
+                                    .reg1 = base_reg,
+                                    .reg2 = registerAlias(tmp_reg, nearest_power_of_two),
+                                    .flags = 0b10,
+                                }),
+                                .data = .{ .imm = @bitCast(u32, -next_offset) },
+                            });
+                            if (nearest_power_of_two > 1) {
+                                try self.genShiftBinOpMir(.shr, ty, tmp_reg, .{ .immediate = nearest_power_of_two * 8 });
+                            }
+                            remainder -= nearest_power_of_two;
+                            next_offset -= nearest_power_of_two;
+                        }
+                    } else {
+                        _ = try self.addInst(.{
+                            .tag = .mov,
+                            .ops = Mir.Inst.Ops.encode(.{
+                                .reg1 = base_reg,
+                                .reg2 = registerAlias(reg, @intCast(u32, abi_size)),
+                                .flags = 0b10,
+                            }),
+                            .data = .{ .imm = @bitCast(u32, -stack_offset) },
+                        });
+                    }
                 },
-                else => return self.fail("TODO genSetStack for AVX register for type {}", .{ty.fmtDebug()}),
             }
         },
         .memory,
 @@ -5742,20 +5591,20 @@ fn genInlineMemcpy(
         .ptr_stack_offset, .stack_offset => |off| {
             _ = try self.addInst(.{
                 .tag = .lea,
-                .ops = (Mir.Ops(Register, Register){
+                .ops = Mir.Inst.Ops.encode(.{
                     .reg1 = dst_addr_reg.to64(),
                     .reg2 = opts.dest_stack_base orelse .rbp,
-                }).encode(),
+                }),
                 .data = .{ .imm = @bitCast(u32, -off) },
             });
         },
         .register => |reg| {
             _ = try self.addInst(.{
                 .tag = .mov,
-                .ops = (Mir.Ops(Register, Register){
+                .ops = Mir.Inst.Ops.encode(.{
                     .reg1 = registerAlias(dst_addr_reg, @divExact(reg.size(), 8)),
                     .reg2 = reg,
-                }).encode(),
+                }),
                 .data = undefined,
             });
         },
 @@ -5777,20 +5626,20 @@ fn genInlineMemcpy(
         .ptr_stack_offset, .stack_offset => |off| {
             _ = try self.addInst(.{
                 .tag = .lea,
-                .ops = (Mir.Ops(Register, Register){
+                .ops = Mir.Inst.Ops.encode(.{
                     .reg1 = src_addr_reg.to64(),
                     .reg2 = opts.source_stack_base orelse .rbp,
-                }).encode(),
+                }),
                 .data = .{ .imm = @bitCast(u32, -off) },
             });
         },
         .register => |reg| {
             _ = try self.addInst(.{
                 .tag = .mov,
-                .ops = (Mir.Ops(Register, Register){
+                .ops = Mir.Inst.Ops.encode(.{
                     .reg1 = registerAlias(src_addr_reg, @divExact(reg.size(), 8)),
                     .reg2 = reg,
-                }).encode(),
+                }),
                 .data = undefined,
             });
         },
 @@ -5810,18 +5659,14 @@ fn genInlineMemcpy(
     // mov rcx, 0
     _ = try self.addInst(.{
         .tag = .mov,
-        .ops = (Mir.Ops(Register, Register){
+        .ops = Mir.Inst.Ops.encode(.{ .reg1 = .rcx }),
-            .reg1 = .rcx,
-        }).encode(),
         .data = .{ .imm = 0 },
     });
     // mov rax, 0
     _ = try self.addInst(.{
         .tag = .mov,
-        .ops = (Mir.Ops(Register, Register){
+        .ops = Mir.Inst.Ops.encode(.{ .reg1 = .rax }),
-            .reg1 = .rax,
-        }).encode(),
         .data = .{ .imm = 0 },
     });
 @@ -5829,70 +5674,62 @@ fn genInlineMemcpy(
     // cmp count, 0
     const loop_start = try self.addInst(.{
         .tag = .cmp,
-        .ops = (Mir.Ops(Register, Register){
+        .ops = Mir.Inst.Ops.encode(.{ .reg1 = count_reg }),
-            .reg1 = count_reg,
-        }).encode(),
         .data = .{ .imm = 0 },
     });
     // je end
     const loop_reloc = try self.addInst(.{
         .tag = .cond_jmp_eq_ne,
-        .ops = (Mir.Ops(Register, Register){ .flags = 0b01 }).encode(),
+        .ops = Mir.Inst.Ops.encode(.{ .flags = 0b01 }),
         .data = .{ .inst = undefined },
     });
     // mov tmp, [addr + rcx]
     _ = try self.addInst(.{
         .tag = .mov_scale_src,
-        .ops = (Mir.Ops(Register, Register){
+        .ops = Mir.Inst.Ops.encode(.{
             .reg1 = tmp_reg.to8(),
             .reg2 = src_addr_reg,
-        }).encode(),
+        }),
         .data = .{ .imm = 0 },
     });
     // mov [stack_offset + rax], tmp
     _ = try self.addInst(.{
         .tag = .mov_scale_dst,
-        .ops = (Mir.Ops(Register, Register){
+        .ops = Mir.Inst.Ops.encode(.{
             .reg1 = dst_addr_reg,
             .reg2 = tmp_reg.to8(),
-        }).encode(),
+        }),
         .data = .{ .imm = 0 },
     });
     // add rcx, 1
     _ = try self.addInst(.{
         .tag = .add,
-        .ops = (Mir.Ops(Register, Register){
+        .ops = Mir.Inst.Ops.encode(.{ .reg1 = .rcx }),
-            .reg1 = .rcx,
-        }).encode(),
         .data = .{ .imm = 1 },
     });
     // add rax, 1
     _ = try self.addInst(.{
         .tag = .add,
-        .ops = (Mir.Ops(Register, Register){
+        .ops = Mir.Inst.Ops.encode(.{ .reg1 = .rax }),
-            .reg1 = .rax,
-        }).encode(),
         .data = .{ .imm = 1 },
     });
     // sub count, 1
     _ = try self.addInst(.{
         .tag = .sub,
-        .ops = (Mir.Ops(Register, Register){
+        .ops = Mir.Inst.Ops.encode(.{ .reg1 = count_reg }),
-            .reg1 = count_reg,
-        }).encode(),
         .data = .{ .imm = 1 },
     });
     // jmp loop
     _ = try self.addInst(.{
         .tag = .jmp,
-        .ops = (Mir.Ops(Register, Register){ .flags = 0b00 }).encode(),
+        .ops = Mir.Inst.Ops.encode(.{}),
         .data = .{ .inst = loop_start },
     });
 @@ -5924,20 +5761,20 @@ fn genInlineMemset(
         .ptr_stack_offset, .stack_offset => |off| {
             _ = try self.addInst(.{
                 .tag = .lea,
-                .ops = (Mir.Ops(Register, Register){
+                .ops = Mir.Inst.Ops.encode(.{
                     .reg1 = addr_reg.to64(),
                     .reg2 = opts.dest_stack_base orelse .rbp,
-                }).encode(),
+                }),
                 .data = .{ .imm = @bitCast(u32, -off) },
             });
         },
         .register => |reg| {
             _ = try self.addInst(.{
                 .tag = .mov,
-                .ops = (Mir.Ops(Register, Register){
+                .ops = Mir.Inst.Ops.encode(.{
                     .reg1 = registerAlias(addr_reg, @divExact(reg.size(), 8)),
                     .reg2 = reg,
-                }).encode(),
+                }),
                 .data = undefined,
             });
         },
 @@ -5955,16 +5792,14 @@ fn genInlineMemset(
     // cmp rax, -1
     const loop_start = try self.addInst(.{
         .tag = .cmp,
-        .ops = (Mir.Ops(Register, Register){
+        .ops = Mir.Inst.Ops.encode(.{ .reg1 = .rax }),
-            .reg1 = .rax,
-        }).encode(),
         .data = .{ .imm = @bitCast(u32, @as(i32, -1)) },
     });
     // je end
     const loop_reloc = try self.addInst(.{
         .tag = .cond_jmp_eq_ne,
-        .ops = (Mir.Ops(Register, Register){ .flags = 0b01 }).encode(),
+        .ops = Mir.Inst.Ops.encode(.{ .flags = 0b01 }),
         .data = .{ .inst = undefined },
     });
 @@ -5980,9 +5815,7 @@ fn genInlineMemset(
             });
             _ = try self.addInst(.{
                 .tag = .mov_mem_index_imm,
-                .ops = (Mir.Ops(Register, Register){
+                .ops = Mir.Inst.Ops.encode(.{ .reg1 = addr_reg }),
-                    .reg1 = addr_reg,
-                }).encode(),
                 .data = .{ .payload = payload },
             });
         },
 @@ -5992,16 +5825,14 @@ fn genInlineMemset(
     // sub rax, 1
     _ = try self.addInst(.{
         .tag = .sub,
-        .ops = (Mir.Ops(Register, Register){
+        .ops = Mir.Inst.Ops.encode(.{ .reg1 = .rax }),
-            .reg1 = .rax,
-        }).encode(),
         .data = .{ .imm = 1 },
     });
     // jmp loop
     _ = try self.addInst(.{
         .tag = .jmp,
-        .ops = (Mir.Ops(Register, Register){ .flags = 0b00 }).encode(),
+        .ops = Mir.Inst.Ops.encode(.{}),
         .data = .{ .inst = loop_start },
     });
 @@ -6009,88 +5840,6 @@ fn genInlineMemset(
     try self.performReloc(loop_reloc);
 }
-fn genSetAvxReg(self: *Self, ty: Type, reg: AvxRegister, mcv: MCValue) InnerError!void {
-    switch (mcv) {
-        .dead => unreachable,
-        .register_overflow_unsigned,
-        .register_overflow_signed,
-        => unreachable,
-        .stack_offset => |off| {
-            if (off < std.math.minInt(i32) or off > std.math.maxInt(i32)) {
-                return self.fail("stack offset too large", .{});
-            }
-            switch (ty.zigTypeTag()) {
-                .Float => {
-                    switch (ty.tag()) {
-                        .f32 => return self.fail("TODO genSetAvxReg from stack offset for f32", .{}),
-                        .f64 => {
-                            _ = try self.addInst(.{
-                                .tag = .mov_f64,
-                                .ops = (Mir.Ops(AvxRegister, Register){
-                                    .reg1 = reg.to128(),
-                                    .reg2 = .rbp,
-                                }).encode(),
-                                .data = .{ .imm = @bitCast(u32, -off) },
-                            });
-                        },
-                        else => return self.fail("TODO genSetAvxReg from stack offset for {}", .{ty.fmtDebug()}),
-                    }
-                },
-                else => return self.fail("TODO genSetAvxReg from stack offset for type {}", .{ty.fmtDebug()}),
-            }
-        },
-        .avx_register => |src_reg| {
-            switch (ty.zigTypeTag()) {
-                .Float => {
-                    switch (ty.tag()) {
-                        .f32 => return self.fail("TODO genSetAvxReg from register for f32", .{}),
-                        .f64 => {
-                            _ = try self.addInst(.{
-                                .tag = .mov_f64,
-                                .ops = (Mir.Ops(AvxRegister, AvxRegister){
-                                    .reg1 = reg.to128(),
-                                    .reg2 = src_reg.to128(),
-                                    .flags = 0b10,
-                                }).encode(),
-                                .data = undefined,
-                            });
-                        },
-                        else => return self.fail("TODO genSetAvxReg from register for {}", .{ty.fmtDebug()}),
-                    }
-                },
-                else => return self.fail("TODO genSetAvxReg from register for type {}", .{ty.fmtDebug()}),
-            }
-        },
-        .memory => {
-            switch (ty.zigTypeTag()) {
-                .Float => {
-                    switch (ty.tag()) {
-                        .f32 => return self.fail("TODO genSetAvxReg from memory for f32", .{}),
-                        .f64 => {
-                            const base_reg = try self.register_manager.allocReg(null);
-                            try self.loadMemPtrIntoRegister(base_reg, Type.usize, mcv);
-                            _ = try self.addInst(.{
-                                .tag = .mov_f64,
-                                .ops = (Mir.Ops(AvxRegister, Register){
-                                    .reg1 = reg.to128(),
-                                    .reg2 = base_reg.to64(),
-                                }).encode(),
-                                .data = .{ .imm = 0 },
-                            });
-                        },
-                        else => return self.fail("TODO genSetAvxReg from memory for {}", .{ty.fmtDebug()}),
-                    }
-                },
-                else => return self.fail("TODO genSetAvxReg from memory for type {}", .{ty.fmtDebug()}),
-            }
-        },
-        else => |other| {
-            return self.fail("TODO genSetAvxReg from {}", .{other});
-        },
-    }
-}
 fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void {
     const abi_size = @intCast(u32, ty.abiSize(self.target.*));
     switch (mcv) {
 @@ -6098,17 +5847,16 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
         .register_overflow_unsigned,
         .register_overflow_signed,
         => unreachable,
-        .avx_register => unreachable,
         .ptr_stack_offset => |off| {
             if (off < std.math.minInt(i32) or off > std.math.maxInt(i32)) {
                 return self.fail("stack offset too large", .{});
             }
             _ = try self.addInst(.{
                 .tag = .lea,
-                .ops = (Mir.Ops(Register, Register){
+                .ops = Mir.Inst.Ops.encode(.{
                     .reg1 = registerAlias(reg, abi_size),
                     .reg2 = .rbp,
-                }).encode(),
+                }),
                 .data = .{ .imm = @bitCast(u32, -off) },
             });
         },
 @@ -6145,10 +5893,10 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
             };
             _ = try self.addInst(.{
                 .tag = tag,
-                .ops = (Mir.Ops(Register, Register){
+                .ops = Mir.Inst.Ops.encode(.{
                     .reg1 = reg.to8(),
                     .flags = flags,
-                }).encode(),
+                }),
                 .data = undefined,
             });
         },
 @@ -6158,10 +5906,10 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
             if (x == 0) {
                 _ = try self.addInst(.{
                     .tag = .xor,
-                    .ops = (Mir.Ops(Register, Register){
+                    .ops = Mir.Inst.Ops.encode(.{
                         .reg1 = reg.to32(),
                         .reg2 = reg.to32(),
-                    }).encode(),
+                    }),
                     .data = undefined,
                 });
                 return;
 @@ -6170,9 +5918,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
                 // Next best case: if we set the lower four bytes, the upper four will be zeroed.
                 _ = try self.addInst(.{
                     .tag = .mov,
-                    .ops = (Mir.Ops(Register, Register){
+                    .ops = Mir.Inst.Ops.encode(.{ .reg1 = registerAlias(reg, abi_size) }),
-                        .reg1 = registerAlias(reg, abi_size),
-                    }).encode(),
                     .data = .{ .imm = @truncate(u32, x) },
                 });
                 return;
 @@ -6187,9 +5933,7 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
             const payload = try self.addExtra(Mir.Imm64.encode(x));
             _ = try self.addInst(.{
                 .tag = .movabs,
-                .ops = (Mir.Ops(Register, Register){
+                .ops = Mir.Inst.Ops.encode(.{ .reg1 = reg.to64() }),
-                    .reg1 = reg.to64(),
-                }).encode(),
                 .data = .{ .payload = payload },
             });
         },
 @@ -6198,40 +5942,60 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
             if (src_reg.id() == reg.id())
                 return;
-            if (ty.zigTypeTag() == .Int) blk: {
+            switch (ty.zigTypeTag()) {
-                switch (ty.intInfo(self.target.*).signedness) {
+                .Int => switch (ty.intInfo(self.target.*).signedness) {
                     .signed => {
-                        if (abi_size > 4) break :blk;
+                        if (abi_size <= 4) {
-                        _ = try self.addInst(.{
+                            _ = try self.addInst(.{
-                            .tag = .mov_sign_extend,
+                                .tag = .mov_sign_extend,
-                            .ops = (Mir.Ops(Register, Register){
+                                .ops = Mir.Inst.Ops.encode(.{
-                                .reg1 = reg.to64(),
+                                    .reg1 = reg.to64(),
-                                .reg2 = registerAlias(src_reg, abi_size),
+                                    .reg2 = registerAlias(src_reg, abi_size),
-                            }).encode(),
+                                }),
-                            .data = undefined,
+                                .data = undefined,
-                        });
+                            });
+                            return;
+                        }
                     },
                     .unsigned => {
-                        if (abi_size > 2) break :blk;
+                        if (abi_size <= 2) {
+                            _ = try self.addInst(.{
+                                .tag = .mov_zero_extend,
+                                .ops = Mir.Inst.Ops.encode(.{
+                                    .reg1 = reg.to64(),
+                                    .reg2 = registerAlias(src_reg, abi_size),
+                                }),
+                                .data = undefined,
+                            });
+                            return;
+                        }
+                    },
+                },
+                .Float => switch (ty.tag()) {
+                    .f32 => return self.fail("TODO genSetReg from register for f32", .{}),
+                    .f64 => {
                         _ = try self.addInst(.{
-                            .tag = .mov_zero_extend,
+                            .tag = .mov_f64,
-                            .ops = (Mir.Ops(Register, Register){
+                            .ops = Mir.Inst.Ops.encode(.{
-                                .reg1 = reg.to64(),
+                                .reg1 = reg.to128(),
-                                .reg2 = registerAlias(src_reg, abi_size),
+                                .reg2 = src_reg.to128(),
-                            }).encode(),
+                                .flags = 0b10,
+                            }),
                             .data = undefined,
                         });
+                        return;
                     },
-                }
+                    else => return self.fail("TODO genSetReg from register for {}", .{ty.fmtDebug()}),
-                return;
+                },
+                else => {},
             }
             _ = try self.addInst(.{
                 .tag = .mov,
-                .ops = (Mir.Ops(Register, Register){
+                .ops = Mir.Inst.Ops.encode(.{
                     .reg1 = registerAlias(reg, abi_size),
                     .reg2 = registerAlias(src_reg, abi_size),
-                }).encode(),
+                }),
                 .data = undefined,
             });
         },
 @@ -6241,107 +6005,148 @@ fn genSetReg(self: *Self, ty: Type, reg: Register, mcv: MCValue) InnerError!void
             try self.loadMemPtrIntoRegister(reg, Type.usize, mcv);
             _ = try self.addInst(.{
                 .tag = .mov,
-                .ops = (Mir.Ops(Register, Register){
+                .ops = Mir.Inst.Ops.encode(.{
                     .reg1 = registerAlias(reg, abi_size),
                     .reg2 = reg.to64(),
                     .flags = 0b01,
-                }).encode(),
+                }),
                 .data = .{ .imm = 0 },
             });
         },
-        .memory => |x| {
+        .memory => |x| switch (ty.zigTypeTag()) {
-            if (x <= math.maxInt(i32)) {
+            .Float => {
-                // mov reg, [ds:imm32]
+                switch (ty.tag()) {
-                _ = try self.addInst(.{
+                    .f32 => return self.fail("TODO genSetReg from memory for f32", .{}),
-                    .tag = .mov,
+                    .f64 => {
-                    .ops = (Mir.Ops(Register, Register){
+                        const base_reg = try self.register_manager.allocReg(null);
-                        .reg1 = registerAlias(reg, abi_size),
+                        try self.loadMemPtrIntoRegister(base_reg, Type.usize, mcv);
-                        .flags = 0b01,
+                        _ = try self.addInst(.{
-                    }).encode(),
+                            .tag = .mov_f64,
-                    .data = .{ .imm = @truncate(u32, x) },
+                            .ops = Mir.Inst.Ops.encode(.{
-                });
+                                .reg1 = reg.to128(),
-            } else {
+                                .reg2 = base_reg.to64(),
-                // If this is RAX, we can use a direct load.
+                            }),
-                // Otherwise, we need to load the address, then indirectly load the value.
+                            .data = .{ .imm = 0 },
-                if (reg.id() == 0) {
+                        });
-                    // movabs rax, ds:moffs64
+                    },
-                    const payload = try self.addExtra(Mir.Imm64.encode(x));
+                    else => return self.fail("TODO genSetReg from memory for {}", .{ty.fmtDebug()}),
-                    _ = try self.addInst(.{
+                }
-                        .tag = .movabs,
+            },
-                        .ops = (Mir.Ops(Register, Register){
+            else => {
-                            .reg1 = .rax,
+                if (x <= math.maxInt(i32)) {
-                            .flags = 0b01, // imm64 will become moffs64
+                    // mov reg, [ds:imm32]
-                        }).encode(),
-                        .data = .{ .payload = payload },
-                    });
-                } else {
-                    // Rather than duplicate the logic used for the move, we just use a self-call with a new MCValue.
-                    try self.genSetReg(ty, reg, MCValue{ .immediate = x });
-                    // mov reg, [reg + 0x0]
                     _ = try self.addInst(.{
                         .tag = .mov,
-                        .ops = (Mir.Ops(Register, Register){
+                        .ops = Mir.Inst.Ops.encode(.{
                             .reg1 = registerAlias(reg, abi_size),
-                            .reg2 = reg.to64(),
                             .flags = 0b01,
-                        }).encode(),
+                        }),
-                        .data = .{ .imm = 0 },
+                        .data = .{ .imm = @truncate(u32, x) },
                     });
+                } else {
+                    // If this is RAX, we can use a direct load.
+                    // Otherwise, we need to load the address, then indirectly load the value.
+                    if (reg.id() == 0) {
+                        // movabs rax, ds:moffs64
+                        const payload = try self.addExtra(Mir.Imm64.encode(x));
+                        _ = try self.addInst(.{
+                            .tag = .movabs,
+                            .ops = Mir.Inst.Ops.encode(.{
+                                .reg1 = .rax,
+                                .flags = 0b01, // imm64 will become moffs64
+                            }),
+                            .data = .{ .payload = payload },
+                        });
+                    } else {
+                        // Rather than duplicate the logic used for the move, we just use a self-call with a new MCValue.
+                        try self.genSetReg(ty, reg, MCValue{ .immediate = x });
+                        // mov reg, [reg + 0x0]
+                        _ = try self.addInst(.{
+                            .tag = .mov,
+                            .ops = Mir.Inst.Ops.encode(.{
+                                .reg1 = registerAlias(reg, abi_size),
+                                .reg2 = reg.to64(),
+                                .flags = 0b01,
+                            }),
+                            .data = .{ .imm = 0 },
+                        });
+                    }
                 }
-            }
+            },
         },
         .stack_offset => |off| {
             if (off < std.math.minInt(i32) or off > std.math.maxInt(i32)) {
                 return self.fail("stack offset too large", .{});
             }
-            if (ty.zigTypeTag() == .Int) blk: {
+            switch (ty.zigTypeTag()) {
-                switch (ty.intInfo(self.target.*).signedness) {
+                .Int => switch (ty.intInfo(self.target.*).signedness) {
                     .signed => {
-                        const flags: u2 = switch (abi_size) {
+                        if (abi_size <= 4) {
-                            1 => 0b01,
+                            const flags: u2 = switch (abi_size) {
-                            2 => 0b10,
+                                1 => 0b01,
-                            4 => 0b11,
+                                2 => 0b10,
-                            else => break :blk,
+                                4 => 0b11,
-                        };
+                                else => unreachable,
-                        _ = try self.addInst(.{
+                            };
-                            .tag = .mov_sign_extend,
+                            _ = try self.addInst(.{
-                            .ops = (Mir.Ops(Register, Register){
+                                .tag = .mov_sign_extend,
-                                .reg1 = reg.to64(),
+                                .ops = Mir.Inst.Ops.encode(.{
-                                .reg2 = .rbp,
+                                    .reg1 = reg.to64(),
-                                .flags = flags,
+                                    .reg2 = .rbp,
-                            }).encode(),
+                                    .flags = flags,
-                            .data = .{ .imm = @bitCast(u32, -off) },
+                                }),
-                        });
+                                .data = .{ .imm = @bitCast(u32, -off) },
+                            });
+                            return;
+                        }
                     },
                     .unsigned => {
-                        const flags: u2 = switch (abi_size) {
+                        if (abi_size <= 2) {
-                            1 => 0b01,
+                            const flags: u2 = switch (abi_size) {
-                            2 => 0b10,
+                                1 => 0b01,
-                            else => break :blk,
+                                2 => 0b10,
-                        };
+                                else => unreachable,
+                            };
+                            _ = try self.addInst(.{
+                                .tag = .mov_zero_extend,
+                                .ops = Mir.Inst.Ops.encode(.{
+                                    .reg1 = reg.to64(),
+                                    .reg2 = .rbp,
+                                    .flags = flags,
+                                }),
+                                .data = .{ .imm = @bitCast(u32, -off) },
+                            });
+                            return;
+                        }
+                    },
+                },
+                .Float => switch (ty.tag()) {
+                    .f32 => return self.fail("TODO genSetReg from stack offset for f32", .{}),
+                    .f64 => {
                         _ = try self.addInst(.{
-                            .tag = .mov_zero_extend,
+                            .tag = .mov_f64,
-                            .ops = (Mir.Ops(Register, Register){
+                            .ops = Mir.Inst.Ops.encode(.{
-                                .reg1 = reg.to64(),
+                                .reg1 = reg.to128(),
                                 .reg2 = .rbp,
-                                .flags = flags,
+                            }),
-                            }).encode(),
                             .data = .{ .imm = @bitCast(u32, -off) },
                         });
+                        return;
                     },
-                }
+                    else => return self.fail("TODO genSetReg from stack offset for {}", .{ty.fmtDebug()}),
-                return;
+                },
+                else => {},
             }
             _ = try self.addInst(.{
                 .tag = .mov,
-                .ops = (Mir.Ops(Register, Register){
+                .ops = Mir.Inst.Ops.encode(.{
                     .reg1 = registerAlias(reg, abi_size),
                     .reg2 = .rbp,
                     .flags = 0b01,
-                }).encode(),
+                }),
                 .data = .{ .imm = @bitCast(u32, -off) },
             });
         },
 @@ -6408,14 +6213,14 @@ fn airFloatToInt(self: *Self, inst: Air.Inst.Index) !void {
     };
     _ = try self.addInst(.{
         .tag = .fld,
-        .ops = (Mir.Ops(Register, Register){
+        .ops = Mir.Inst.Ops.encode(.{
+            .reg1 = .rbp,
             .flags = switch (src_ty.abiSize(self.target.*)) {
                 4 => 0b01,
                 8 => 0b10,
                 else => |size| return self.fail("TODO load ST(0) with abiSize={}", .{size}),
             },
-            .reg1 = .rbp,
+        }),
-        }).encode(),
         .data = .{ .imm = @bitCast(u32, -stack_offset) },
     });
 @@ -6423,15 +6228,15 @@ fn airFloatToInt(self: *Self, inst: Air.Inst.Index) !void {
     const stack_dst = try self.allocRegOrMem(inst, false);
     _ = try self.addInst(.{
         .tag = .fisttp,
-        .ops = (Mir.Ops(Register, Register){
+        .ops = Mir.Inst.Ops.encode(.{
+            .reg1 = .rbp,
             .flags = switch (dst_ty.abiSize(self.target.*)) {
                 1...2 => 0b00,
                 3...4 => 0b01,
                 5...8 => 0b10,
                 else => |size| return self.fail("TODO convert float with abiSize={}", .{size}),
             },
-            .reg1 = .rbp,
+        }),
-        }).encode(),
         .data = .{ .imm = @bitCast(u32, -stack_dst.stack_offset) },
     });
 @@ -6527,11 +6332,11 @@ fn airMemcpy(self: *Self, inst: Air.Inst.Index) !void {
                 try self.loadMemPtrIntoRegister(reg, src_ty, src_ptr);
                 _ = try self.addInst(.{
                     .tag = .mov,
-                    .ops = (Mir.Ops(Register, Register){
+                    .ops = Mir.Inst.Ops.encode(.{
                         .reg1 = reg,
                         .reg2 = reg,
                         .flags = 0b01,
-                    }).encode(),
+                    }),
                     .data = .{ .imm = 0 },
                 });
                 break :blk MCValue{ .register = reg };
 @@ -7095,22 +6900,11 @@ fn registerAlias(reg: Register, size_bytes: u32) Register {
         return reg.to32();
     } else if (size_bytes <= 8) {
         return reg.to64();
-    } else {
-        unreachable;
-    }
-}
-/// Returns AVX register wide enough to hold at least `size_bytes`.
-fn avxRegisterAlias(reg: AvxRegister, size_bytes: u32) AvxRegister {
-    if (size_bytes == 0) {
-        unreachable; // should be comptime known
     } else if (size_bytes <= 16) {
         return reg.to128();
     } else if (size_bytes <= 32) {
         return reg.to256();
-    } else {
+    } else unreachable;
-        unreachable;
-    }
 }
 /// Truncates the value in the register in place.

src/arch/x86_64/Emit.zig+383-389

...	@@ -25,9 +25,8 @@ const MCValue = @import("CodeGen.zig").MCValue;	...	@@ -25,9 +25,8 @@ const MCValue = @import("CodeGen.zig").MCValue;
25	const Mir = @import("Mir.zig");	25	const Mir = @import("Mir.zig");
26	const Module = @import("../../Module.zig");	26	const Module = @import("../../Module.zig");
27	const Instruction = bits.Instruction;	27	const Instruction = bits.Instruction;
28	const GpRegister = bits.Register;
29	const AvxRegister = bits.AvxRegister;
30	const Type = @import("../../type.zig").Type;	28	const Type = @import("../../type.zig").Type;
		29	const Register = bits.Register;
31		30
32	mir: Mir,	31	mir: Mir,
33	bin_file: *link.File,	32	bin_file: *link.File,
...	@@ -238,7 +237,7 @@ fn fixupRelocs(emit: *Emit) InnerError!void {	...	@@ -238,7 +237,7 @@ fn fixupRelocs(emit: *Emit) InnerError!void {
238	fn mirInterrupt(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {	237	fn mirInterrupt(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
239	const tag = emit.mir.instructions.items(.tag)[inst];	238	const tag = emit.mir.instructions.items(.tag)[inst];
240	assert(tag == .interrupt);	239	assert(tag == .interrupt);
241	const ops = Mir.Ops.decode(emit.mir.instructions.items(.ops)[inst]);	240	const ops = emit.mir.instructions.items(.ops)[inst].decode();
242	switch (ops.flags) {	241	switch (ops.flags) {
243	0b00 => return lowerToZoEnc(.int3, emit.code),	242	0b00 => return lowerToZoEnc(.int3, emit.code),
244	else => return emit.fail("TODO handle variant 0b{b} of interrupt instruction", .{ops.flags}),	243	else => return emit.fail("TODO handle variant 0b{b} of interrupt instruction", .{ops.flags}),
...	@@ -254,11 +253,11 @@ fn mirSyscall(emit: *Emit) InnerError!void {	...	@@ -254,11 +253,11 @@ fn mirSyscall(emit: *Emit) InnerError!void {
254	}	253	}
255		254
256	fn mirPushPop(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {	255	fn mirPushPop(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
257	const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);	256	const ops = emit.mir.instructions.items(.ops)[inst].decode();
258	switch (ops.flags) {	257	switch (ops.flags) {
259	0b00 => {	258	0b00 => {
260	// PUSH/POP reg	259	// PUSH/POP reg
261	return lowerToOEnc(tag, Register.reg(ops.reg1), emit.code);	260	return lowerToOEnc(tag, ops.reg1, emit.code);
262	},	261	},
263	0b01 => {	262	0b01 => {
264	// PUSH/POP r/m64	263	// PUSH/POP r/m64
...	@@ -283,7 +282,7 @@ fn mirPushPop(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {	...	@@ -283,7 +282,7 @@ fn mirPushPop(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
283	}	282	}
284		283
285	fn mirPushPopRegsFromCalleePreservedRegs(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {	284	fn mirPushPopRegsFromCalleePreservedRegs(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
286	const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);	285	const ops = emit.mir.instructions.items(.ops)[inst].decode();
287	const payload = emit.mir.instructions.items(.data)[inst].payload;	286	const payload = emit.mir.instructions.items(.data)[inst].payload;
288	const data = emit.mir.extraData(Mir.RegsToPushOrPop, payload).data;	287	const data = emit.mir.extraData(Mir.RegsToPushOrPop, payload).data;
289	const regs = data.regs;	288	const regs = data.regs;
...	@@ -294,9 +293,9 @@ fn mirPushPopRegsFromCalleePreservedRegs(emit: *Emit, tag: Tag, inst: Mir.Inst.I	...	@@ -294,9 +293,9 @@ fn mirPushPopRegsFromCalleePreservedRegs(emit: *Emit, tag: Tag, inst: Mir.Inst.I
294	try lowerToMrEnc(.mov, RegisterOrMemory.mem(.qword_ptr, .{	293	try lowerToMrEnc(.mov, RegisterOrMemory.mem(.qword_ptr, .{
295	.disp = @bitCast(u32, -@intCast(i32, disp)),	294	.disp = @bitCast(u32, -@intCast(i32, disp)),
296	.base = ops.reg1,	295	.base = ops.reg1,
297	}), Register.reg(reg.to64()), emit.code);	296	}), reg.to64(), emit.code);
298	} else {	297	} else {
299	try lowerToRmEnc(.mov, Register.reg(reg.to64()), RegisterOrMemory.mem(.qword_ptr, .{	298	try lowerToRmEnc(.mov, reg.to64(), RegisterOrMemory.mem(.qword_ptr, .{
300	.disp = @bitCast(u32, -@intCast(i32, disp)),	299	.disp = @bitCast(u32, -@intCast(i32, disp)),
301	.base = ops.reg1,	300	.base = ops.reg1,
302	}), emit.code);	301	}), emit.code);
...	@@ -306,7 +305,7 @@ fn mirPushPopRegsFromCalleePreservedRegs(emit: *Emit, tag: Tag, inst: Mir.Inst.I	...	@@ -306,7 +305,7 @@ fn mirPushPopRegsFromCalleePreservedRegs(emit: *Emit, tag: Tag, inst: Mir.Inst.I
306	}	305	}
307		306
308	fn mirJmpCall(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {	307	fn mirJmpCall(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
309	const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);	308	const ops = emit.mir.instructions.items(.ops)[inst].decode();
310	switch (ops.flags) {	309	switch (ops.flags) {
311	0b00 => {	310	0b00 => {
312	const target = emit.mir.instructions.items(.data)[inst].inst;	311	const target = emit.mir.instructions.items(.data)[inst].inst;
...	@@ -335,7 +334,7 @@ fn mirJmpCall(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {	...	@@ -335,7 +334,7 @@ fn mirJmpCall(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
335	0b10 => {	334	0b10 => {
336	// JMP/CALL r/m64	335	// JMP/CALL r/m64
337	const imm = emit.mir.instructions.items(.data)[inst].imm;	336	const imm = emit.mir.instructions.items(.data)[inst].imm;
338	return lowerToMEnc(tag, RegisterOrMemory.mem(Memory.PtrSize.fromBits(ops.reg1.size()), .{	337	return lowerToMEnc(tag, RegisterOrMemory.mem(Memory.PtrSize.new(ops.reg1.size()), .{
339	.disp = imm,	338	.disp = imm,
340	.base = ops.reg1,	339	.base = ops.reg1,
341	}), emit.code);	340	}), emit.code);
...	@@ -345,7 +344,7 @@ fn mirJmpCall(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {	...	@@ -345,7 +344,7 @@ fn mirJmpCall(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
345	}	344	}
346		345
347	fn mirCondJmp(emit: *Emit, mir_tag: Mir.Inst.Tag, inst: Mir.Inst.Index) InnerError!void {	346	fn mirCondJmp(emit: *Emit, mir_tag: Mir.Inst.Tag, inst: Mir.Inst.Index) InnerError!void {
348	const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);	347	const ops = emit.mir.instructions.items(.ops)[inst].decode();
349	const target = emit.mir.instructions.items(.data)[inst].inst;	348	const target = emit.mir.instructions.items(.data)[inst].inst;
350	const tag = switch (mir_tag) {	349	const tag = switch (mir_tag) {
351	.cond_jmp_greater_less => switch (ops.flags) {	350	.cond_jmp_greater_less => switch (ops.flags) {
...	@@ -377,7 +376,7 @@ fn mirCondJmp(emit: *Emit, mir_tag: Mir.Inst.Tag, inst: Mir.Inst.Index) InnerErr	...	@@ -377,7 +376,7 @@ fn mirCondJmp(emit: *Emit, mir_tag: Mir.Inst.Tag, inst: Mir.Inst.Index) InnerErr
377	}	376	}
378		377
379	fn mirCondSetByte(emit: *Emit, mir_tag: Mir.Inst.Tag, inst: Mir.Inst.Index) InnerError!void {	378	fn mirCondSetByte(emit: *Emit, mir_tag: Mir.Inst.Tag, inst: Mir.Inst.Index) InnerError!void {
380	const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);	379	const ops = emit.mir.instructions.items(.ops)[inst].decode();
381	const tag = switch (mir_tag) {	380	const tag = switch (mir_tag) {
382	.cond_set_byte_greater_less => switch (ops.flags) {	381	.cond_set_byte_greater_less => switch (ops.flags) {
383	0b00 => Tag.setge,	382	0b00 => Tag.setge,
...	@@ -407,9 +406,9 @@ fn mirCondSetByte(emit: *Emit, mir_tag: Mir.Inst.Tag, inst: Mir.Inst.Index) Inne	...	@@ -407,9 +406,9 @@ fn mirCondSetByte(emit: *Emit, mir_tag: Mir.Inst.Tag, inst: Mir.Inst.Index) Inne
407	}	406	}
408		407
409	fn mirCondMov(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {	408	fn mirCondMov(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
410	const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);	409	const ops = emit.mir.instructions.items(.ops)[inst].decode();
411	if (ops.flags == 0b00) {	410	if (ops.flags == 0b00) {
412	return lowerToRmEnc(tag, Register.reg(ops.reg1), RegisterOrMemory.reg(ops.reg2), emit.code);	411	return lowerToRmEnc(tag, ops.reg1, RegisterOrMemory.reg(ops.reg2), emit.code);
413	}	412	}
414	const imm = emit.mir.instructions.items(.data)[inst].imm;	413	const imm = emit.mir.instructions.items(.data)[inst].imm;
415	const ptr_size: Memory.PtrSize = switch (ops.flags) {	414	const ptr_size: Memory.PtrSize = switch (ops.flags) {
...	@@ -418,7 +417,7 @@ fn mirCondMov(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {	...	@@ -418,7 +417,7 @@ fn mirCondMov(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
418	0b10 => .dword_ptr,	417	0b10 => .dword_ptr,
419	0b11 => .qword_ptr,	418	0b11 => .qword_ptr,
420	};	419	};
421	return lowerToRmEnc(tag, Register.reg(ops.reg1), RegisterOrMemory.mem(ptr_size, .{	420	return lowerToRmEnc(tag, ops.reg1, RegisterOrMemory.mem(ptr_size, .{
422	.disp = imm,	421	.disp = imm,
423	.base = ops.reg2,	422	.base = ops.reg2,
424	}), emit.code);	423	}), emit.code);
...	@@ -427,7 +426,7 @@ fn mirCondMov(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {	...	@@ -427,7 +426,7 @@ fn mirCondMov(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
427	fn mirTest(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {	426	fn mirTest(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
428	const tag = emit.mir.instructions.items(.tag)[inst];	427	const tag = emit.mir.instructions.items(.tag)[inst];
429	assert(tag == .@"test");	428	assert(tag == .@"test");
430	const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);	429	const ops = emit.mir.instructions.items(.ops)[inst].decode();
431	switch (ops.flags) {	430	switch (ops.flags) {
432	0b00 => {	431	0b00 => {
433	if (ops.reg2 == .none) {	432	if (ops.reg2 == .none) {
...	@@ -442,12 +441,7 @@ fn mirTest(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {	...	@@ -442,12 +441,7 @@ fn mirTest(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
442	return lowerToMiEnc(.@"test", RegisterOrMemory.reg(ops.reg1), imm, emit.code);	441	return lowerToMiEnc(.@"test", RegisterOrMemory.reg(ops.reg1), imm, emit.code);
443	}	442	}
444	// TEST r/m64, r64	443	// TEST r/m64, r64
445	return lowerToMrEnc(	444	return lowerToMrEnc(.@"test", RegisterOrMemory.reg(ops.reg1), ops.reg2, emit.code);
446	.@"test",
447	RegisterOrMemory.reg(ops.reg1),
448	Register.reg(ops.reg2),
449	emit.code,
450	);
451	},	445	},
452	else => return emit.fail("TODO more TEST alternatives", .{}),	446	else => return emit.fail("TODO more TEST alternatives", .{}),
453	}	447	}
...	@@ -456,7 +450,7 @@ fn mirTest(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {	...	@@ -456,7 +450,7 @@ fn mirTest(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
456	fn mirRet(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {	450	fn mirRet(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
457	const tag = emit.mir.instructions.items(.tag)[inst];	451	const tag = emit.mir.instructions.items(.tag)[inst];
458	assert(tag == .ret);	452	assert(tag == .ret);
459	const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);	453	const ops = emit.mir.instructions.items(.ops)[inst].decode();
460	switch (ops.flags) {	454	switch (ops.flags) {
461	0b00 => {	455	0b00 => {
462	// RETF imm16	456	// RETF imm16
...	@@ -480,7 +474,7 @@ fn mirRet(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {	...	@@ -480,7 +474,7 @@ fn mirRet(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
480	}	474	}
481		475
482	fn mirArith(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {	476	fn mirArith(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
483	const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);	477	const ops = emit.mir.instructions.items(.ops)[inst].decode();
484	switch (ops.flags) {	478	switch (ops.flags) {
485	0b00 => {	479	0b00 => {
486	if (ops.reg2 == .none) {	480	if (ops.reg2 == .none) {
...	@@ -491,14 +485,14 @@ fn mirArith(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {	...	@@ -491,14 +485,14 @@ fn mirArith(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
491	}	485	}
492	// mov reg1, reg2	486	// mov reg1, reg2
493	// RM	487	// RM
494	return lowerToRmEnc(tag, Register.reg(ops.reg1), RegisterOrMemory.reg(ops.reg2), emit.code);	488	return lowerToRmEnc(tag, ops.reg1, RegisterOrMemory.reg(ops.reg2), emit.code);
495	},	489	},
496	0b01 => {	490	0b01 => {
497	// mov reg1, [reg2 + imm32]	491	// mov reg1, [reg2 + imm32]
498	// RM	492	// RM
499	const imm = emit.mir.instructions.items(.data)[inst].imm;	493	const imm = emit.mir.instructions.items(.data)[inst].imm;
500	const src_reg: ?GpRegister = if (ops.reg2 == .none) null else ops.reg2;	494	const src_reg: ?Register = if (ops.reg2 != .none) ops.reg2 else null;
501	return lowerToRmEnc(tag, Register.reg(ops.reg1), RegisterOrMemory.mem(Memory.PtrSize.fromBits(ops.reg1.size()), .{	495	return lowerToRmEnc(tag, ops.reg1, RegisterOrMemory.mem(Memory.PtrSize.new(ops.reg1.size()), .{
502	.disp = imm,	496	.disp = imm,
503	.base = src_reg,	497	.base = src_reg,
504	}), emit.code);	498	}), emit.code);
...	@@ -510,10 +504,10 @@ fn mirArith(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {	...	@@ -510,10 +504,10 @@ fn mirArith(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
510	// mov [reg1 + imm32], reg2	504	// mov [reg1 + imm32], reg2
511	// MR	505	// MR
512	const imm = emit.mir.instructions.items(.data)[inst].imm;	506	const imm = emit.mir.instructions.items(.data)[inst].imm;
513	return lowerToMrEnc(tag, RegisterOrMemory.mem(Memory.PtrSize.fromBits(ops.reg2.size()), .{	507	return lowerToMrEnc(tag, RegisterOrMemory.mem(Memory.PtrSize.new(ops.reg2.size()), .{
514	.disp = imm,	508	.disp = imm,
515	.base = ops.reg1,	509	.base = ops.reg1,
516	}), Register.reg(ops.reg2), emit.code);	510	}), ops.reg2, emit.code);
517	},	511	},
518	0b11 => {	512	0b11 => {
519	return emit.fail("TODO unused variant: mov reg1, reg2, 0b11", .{});	513	return emit.fail("TODO unused variant: mov reg1, reg2, 0b11", .{});
...	@@ -522,7 +516,7 @@ fn mirArith(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {	...	@@ -522,7 +516,7 @@ fn mirArith(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
522	}	516	}
523		517
524	fn mirArithMemImm(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {	518	fn mirArithMemImm(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
525	const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);	519	const ops = emit.mir.instructions.items(.ops)[inst].decode();
526	assert(ops.reg2 == .none);	520	assert(ops.reg2 == .none);
527	const payload = emit.mir.instructions.items(.data)[inst].payload;	521	const payload = emit.mir.instructions.items(.data)[inst].payload;
528	const imm_pair = emit.mir.extraData(Mir.ImmPair, payload).data;	522	const imm_pair = emit.mir.extraData(Mir.ImmPair, payload).data;
...	@@ -539,19 +533,14 @@ fn mirArithMemImm(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {	...	@@ -539,19 +533,14 @@ fn mirArithMemImm(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
539	}	533	}
540		534
541	inline fn setRexWRegister(reg: Register) bool {	535	inline fn setRexWRegister(reg: Register) bool {
542	switch (reg) {	536	if (reg.size() == 64) return true;
543	.avx_register => return false,	537	return switch (reg) {
544	.register => \|r\| {	538	.ah, .ch, .dh, .bh => true,
545	if (r.size() == 64) return true;	539	else => false,
546	return switch (r) {	540	};
547	.ah, .bh, .ch, .dh => true,
548	else => false,
549	};
550	},
551	}
552	}	541	}
553		542
554	inline fn immOpSize(u_imm: u32) u8 {	543	inline fn immOpSize(u_imm: u32) u6 {
555	const imm = @bitCast(i32, u_imm);	544	const imm = @bitCast(i32, u_imm);
556	if (math.minInt(i8) <= imm and imm <= math.maxInt(i8)) {	545	if (math.minInt(i8) <= imm and imm <= math.maxInt(i8)) {
557	return 8;	546	return 8;
...	@@ -563,7 +552,7 @@ inline fn immOpSize(u_imm: u32) u8 {	...	@@ -563,7 +552,7 @@ inline fn immOpSize(u_imm: u32) u8 {
563	}	552	}
564		553
565	fn mirArithScaleSrc(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {	554	fn mirArithScaleSrc(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
566	const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);	555	const ops = emit.mir.instructions.items(.ops)[inst].decode();
567	const scale = ops.flags;	556	const scale = ops.flags;
568	const imm = emit.mir.instructions.items(.data)[inst].imm;	557	const imm = emit.mir.instructions.items(.data)[inst].imm;
569	// OP reg1, [reg2 + scale*rcx + imm32]	558	// OP reg1, [reg2 + scale*rcx + imm32]
...	@@ -571,7 +560,7 @@ fn mirArithScaleSrc(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void	...	@@ -571,7 +560,7 @@ fn mirArithScaleSrc(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void
571	.scale = scale,	560	.scale = scale,
572	.index = .rcx,	561	.index = .rcx,
573	};	562	};
574	return lowerToRmEnc(tag, Register.reg(ops.reg1), RegisterOrMemory.mem(Memory.PtrSize.fromBits(ops.reg1.size()), .{	563	return lowerToRmEnc(tag, ops.reg1, RegisterOrMemory.mem(Memory.PtrSize.new(ops.reg1.size()), .{
575	.disp = imm,	564	.disp = imm,
576	.base = ops.reg2,	565	.base = ops.reg2,
577	.scale_index = scale_index,	566	.scale_index = scale_index,
...	@@ -579,7 +568,7 @@ fn mirArithScaleSrc(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void	...	@@ -579,7 +568,7 @@ fn mirArithScaleSrc(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void
579	}	568	}
580		569
581	fn mirArithScaleDst(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {	570	fn mirArithScaleDst(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
582	const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);	571	const ops = emit.mir.instructions.items(.ops)[inst].decode();
583	const scale = ops.flags;	572	const scale = ops.flags;
584	const imm = emit.mir.instructions.items(.data)[inst].imm;	573	const imm = emit.mir.instructions.items(.data)[inst].imm;
585	const scale_index = ScaleIndex{	574	const scale_index = ScaleIndex{
...	@@ -595,15 +584,15 @@ fn mirArithScaleDst(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void	...	@@ -595,15 +584,15 @@ fn mirArithScaleDst(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void
595	}), imm, emit.code);	584	}), imm, emit.code);
596	}	585	}
597	// OP [reg1 + scale*rax + imm32], reg2	586	// OP [reg1 + scale*rax + imm32], reg2
598	return lowerToMrEnc(tag, RegisterOrMemory.mem(Memory.PtrSize.fromBits(ops.reg2.size()), .{	587	return lowerToMrEnc(tag, RegisterOrMemory.mem(Memory.PtrSize.new(ops.reg2.size()), .{
599	.disp = imm,	588	.disp = imm,
600	.base = ops.reg1,	589	.base = ops.reg1,
601	.scale_index = scale_index,	590	.scale_index = scale_index,
602	}), Register.reg(ops.reg2), emit.code);	591	}), ops.reg2, emit.code);
603	}	592	}
604		593
605	fn mirArithScaleImm(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {	594	fn mirArithScaleImm(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
606	const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);	595	const ops = emit.mir.instructions.items(.ops)[inst].decode();
607	const scale = ops.flags;	596	const scale = ops.flags;
608	const payload = emit.mir.instructions.items(.data)[inst].payload;	597	const payload = emit.mir.instructions.items(.data)[inst].payload;
609	const imm_pair = emit.mir.extraData(Mir.ImmPair, payload).data;	598	const imm_pair = emit.mir.extraData(Mir.ImmPair, payload).data;
...	@@ -620,7 +609,7 @@ fn mirArithScaleImm(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void	...	@@ -620,7 +609,7 @@ fn mirArithScaleImm(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void
620	}	609	}
621		610
622	fn mirArithMemIndexImm(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {	611	fn mirArithMemIndexImm(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
623	const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);	612	const ops = emit.mir.instructions.items(.ops)[inst].decode();
624	assert(ops.reg2 == .none);	613	assert(ops.reg2 == .none);
625	const payload = emit.mir.instructions.items(.data)[inst].payload;	614	const payload = emit.mir.instructions.items(.data)[inst].payload;
626	const imm_pair = emit.mir.extraData(Mir.ImmPair, payload).data;	615	const imm_pair = emit.mir.extraData(Mir.ImmPair, payload).data;
...	@@ -645,27 +634,27 @@ fn mirArithMemIndexImm(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!v	...	@@ -645,27 +634,27 @@ fn mirArithMemIndexImm(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!v
645	fn mirMovSignExtend(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {	634	fn mirMovSignExtend(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
646	const mir_tag = emit.mir.instructions.items(.tag)[inst];	635	const mir_tag = emit.mir.instructions.items(.tag)[inst];
647	assert(mir_tag == .mov_sign_extend);	636	assert(mir_tag == .mov_sign_extend);
648	const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);	637	const ops = emit.mir.instructions.items(.ops)[inst].decode();
649	const imm = if (ops.flags != 0b00) emit.mir.instructions.items(.data)[inst].imm else undefined;	638	const imm = if (ops.flags != 0b00) emit.mir.instructions.items(.data)[inst].imm else undefined;
650	switch (ops.flags) {	639	switch (ops.flags) {
651	0b00 => {	640	0b00 => {
652	const tag: Tag = if (ops.reg2.size() == 32) .movsxd else .movsx;	641	const tag: Tag = if (ops.reg2.size() == 32) .movsxd else .movsx;
653	return lowerToRmEnc(tag, Register.reg(ops.reg1), RegisterOrMemory.reg(ops.reg2), emit.code);	642	return lowerToRmEnc(tag, ops.reg1, RegisterOrMemory.reg(ops.reg2), emit.code);
654	},	643	},
655	0b01 => {	644	0b01 => {
656	return lowerToRmEnc(.movsx, Register.reg(ops.reg1), RegisterOrMemory.mem(.byte_ptr, .{	645	return lowerToRmEnc(.movsx, ops.reg1, RegisterOrMemory.mem(.byte_ptr, .{
657	.disp = imm,	646	.disp = imm,
658	.base = ops.reg2,	647	.base = ops.reg2,
659	}), emit.code);	648	}), emit.code);
660	},	649	},
661	0b10 => {	650	0b10 => {
662	return lowerToRmEnc(.movsx, Register.reg(ops.reg1), RegisterOrMemory.mem(.word_ptr, .{	651	return lowerToRmEnc(.movsx, ops.reg1, RegisterOrMemory.mem(.word_ptr, .{
663	.disp = imm,	652	.disp = imm,
664	.base = ops.reg2,	653	.base = ops.reg2,
665	}), emit.code);	654	}), emit.code);
666	},	655	},
667	0b11 => {	656	0b11 => {
668	return lowerToRmEnc(.movsxd, Register.reg(ops.reg1), RegisterOrMemory.mem(.dword_ptr, .{	657	return lowerToRmEnc(.movsxd, ops.reg1, RegisterOrMemory.mem(.dword_ptr, .{
669	.disp = imm,	658	.disp = imm,
670	.base = ops.reg2,	659	.base = ops.reg2,
671	}), emit.code);	660	}), emit.code);
...	@@ -676,20 +665,20 @@ fn mirMovSignExtend(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {	...	@@ -676,20 +665,20 @@ fn mirMovSignExtend(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
676	fn mirMovZeroExtend(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {	665	fn mirMovZeroExtend(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
677	const mir_tag = emit.mir.instructions.items(.tag)[inst];	666	const mir_tag = emit.mir.instructions.items(.tag)[inst];
678	assert(mir_tag == .mov_zero_extend);	667	assert(mir_tag == .mov_zero_extend);
679	const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);	668	const ops = emit.mir.instructions.items(.ops)[inst].decode();
680	const imm = if (ops.flags != 0b00) emit.mir.instructions.items(.data)[inst].imm else undefined;	669	const imm = if (ops.flags != 0b00) emit.mir.instructions.items(.data)[inst].imm else undefined;
681	switch (ops.flags) {	670	switch (ops.flags) {
682	0b00 => {	671	0b00 => {
683	return lowerToRmEnc(.movzx, Register.reg(ops.reg1), RegisterOrMemory.reg(ops.reg2), emit.code);	672	return lowerToRmEnc(.movzx, ops.reg1, RegisterOrMemory.reg(ops.reg2), emit.code);
684	},	673	},
685	0b01 => {	674	0b01 => {
686	return lowerToRmEnc(.movzx, Register.reg(ops.reg1), RegisterOrMemory.mem(.byte_ptr, .{	675	return lowerToRmEnc(.movzx, ops.reg1, RegisterOrMemory.mem(.byte_ptr, .{
687	.disp = imm,	676	.disp = imm,
688	.base = ops.reg2,	677	.base = ops.reg2,
689	}), emit.code);	678	}), emit.code);
690	},	679	},
691	0b10 => {	680	0b10 => {
692	return lowerToRmEnc(.movzx, Register.reg(ops.reg1), RegisterOrMemory.mem(.word_ptr, .{	681	return lowerToRmEnc(.movzx, ops.reg1, RegisterOrMemory.mem(.word_ptr, .{
693	.disp = imm,	682	.disp = imm,
694	.base = ops.reg2,	683	.base = ops.reg2,
695	}), emit.code);	684	}), emit.code);
...	@@ -703,31 +692,46 @@ fn mirMovZeroExtend(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {	...	@@ -703,31 +692,46 @@ fn mirMovZeroExtend(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
703	fn mirMovabs(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {	692	fn mirMovabs(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
704	const tag = emit.mir.instructions.items(.tag)[inst];	693	const tag = emit.mir.instructions.items(.tag)[inst];
705	assert(tag == .movabs);	694	assert(tag == .movabs);
706	const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);	695	const ops = emit.mir.instructions.items(.ops)[inst].decode();
707	const imm: u64 = if (ops.reg1.size() == 64) blk: {	696	switch (ops.flags) {
708	const payload = emit.mir.instructions.items(.data)[inst].payload;	697	0b00 => {
709	const imm = emit.mir.extraData(Mir.Imm64, payload).data;	698	const imm: u64 = if (ops.reg1.size() == 64) blk: {
710	break :blk imm.decode();	699	const payload = emit.mir.instructions.items(.data)[inst].payload;
711	} else emit.mir.instructions.items(.data)[inst].imm;	700	const imm = emit.mir.extraData(Mir.Imm64, payload).data;
712	if (ops.flags == 0b00) {	701	break :blk imm.decode();
713	// movabs reg, imm64	702	} else emit.mir.instructions.items(.data)[inst].imm;
714	// OI	703	// movabs reg, imm64
715	return lowerToOiEnc(.mov, Register.reg(ops.reg1), imm, emit.code);	704	// OI
716	}	705	return lowerToOiEnc(.mov, ops.reg1, imm, emit.code);
717	if (ops.reg1 == .none) {	706	},
718	// movabs moffs64, rax	707	0b01 => {
719	// TD	708	if (ops.reg1 == .none) {
720	return lowerToTdEnc(.mov, imm, Register.reg(ops.reg2), emit.code);	709	const imm: u64 = if (ops.reg2.size() == 64) blk: {
		710	const payload = emit.mir.instructions.items(.data)[inst].payload;
		711	const imm = emit.mir.extraData(Mir.Imm64, payload).data;
		712	break :blk imm.decode();
		713	} else emit.mir.instructions.items(.data)[inst].imm;
		714	// movabs moffs64, rax
		715	// TD
		716	return lowerToTdEnc(.mov, imm, ops.reg2, emit.code);
		717	}
		718	const imm: u64 = if (ops.reg1.size() == 64) blk: {
		719	const payload = emit.mir.instructions.items(.data)[inst].payload;
		720	const imm = emit.mir.extraData(Mir.Imm64, payload).data;
		721	break :blk imm.decode();
		722	} else emit.mir.instructions.items(.data)[inst].imm;
		723	// movabs rax, moffs64
		724	// FD
		725	return lowerToFdEnc(.mov, ops.reg1, imm, emit.code);
		726	},
		727	else => return emit.fail("TODO unused variant: movabs 0b{b}", .{ops.flags}),
721	}	728	}
722	// movabs rax, moffs64
723	// FD
724	return lowerToFdEnc(.mov, Register.reg(ops.reg1), imm, emit.code);
725	}	729	}
726		730
727	fn mirFisttp(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {	731	fn mirFisttp(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
728	const tag = emit.mir.instructions.items(.tag)[inst];	732	const tag = emit.mir.instructions.items(.tag)[inst];
729	assert(tag == .fisttp);	733	assert(tag == .fisttp);
730	const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);	734	const ops = emit.mir.instructions.items(.ops)[inst].decode();
731		735
732	// the selecting between operand sizes for this particular `fisttp` instruction	736	// the selecting between operand sizes for this particular `fisttp` instruction
733	// is done via opcode instead of the usual prefixes.	737	// is done via opcode instead of the usual prefixes.
...	@@ -749,7 +753,7 @@ fn mirFisttp(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {	...	@@ -749,7 +753,7 @@ fn mirFisttp(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
749	fn mirFld(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {	753	fn mirFld(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
750	const tag = emit.mir.instructions.items(.tag)[inst];	754	const tag = emit.mir.instructions.items(.tag)[inst];
751	assert(tag == .fld);	755	assert(tag == .fld);
752	const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);	756	const ops = emit.mir.instructions.items(.ops)[inst].decode();
753		757
754	// the selecting between operand sizes for this particular `fisttp` instruction	758	// the selecting between operand sizes for this particular `fisttp` instruction
755	// is done via opcode instead of the usual prefixes.	759	// is done via opcode instead of the usual prefixes.
...	@@ -768,7 +772,7 @@ fn mirFld(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {	...	@@ -768,7 +772,7 @@ fn mirFld(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
768	}	772	}
769		773
770	fn mirShift(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {	774	fn mirShift(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
771	const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);	775	const ops = emit.mir.instructions.items(.ops)[inst].decode();
772	switch (ops.flags) {	776	switch (ops.flags) {
773	0b00 => {	777	0b00 => {
774	// sal reg1, 1	778	// sal reg1, 1
...	@@ -793,12 +797,11 @@ fn mirShift(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {	...	@@ -793,12 +797,11 @@ fn mirShift(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
793	}	797	}
794		798
795	fn mirMulDiv(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {	799	fn mirMulDiv(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
796	const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);	800	const ops = emit.mir.instructions.items(.ops)[inst].decode();
797	if (ops.reg1 != .none) {	801	if (ops.reg1 != .none) {
798	assert(ops.reg2 == .none);	802	assert(ops.reg2 == .none);
799	return lowerToMEnc(tag, RegisterOrMemory.reg(ops.reg1), emit.code);	803	return lowerToMEnc(tag, RegisterOrMemory.reg(ops.reg1), emit.code);
800	}	804	}
801	assert(ops.reg1 == .none);
802	assert(ops.reg2 != .none);	805	assert(ops.reg2 != .none);
803	const imm = emit.mir.instructions.items(.data)[inst].imm;	806	const imm = emit.mir.instructions.items(.data)[inst].imm;
804	const ptr_size: Memory.PtrSize = switch (ops.flags) {	807	const ptr_size: Memory.PtrSize = switch (ops.flags) {
...	@@ -816,27 +819,27 @@ fn mirMulDiv(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {	...	@@ -816,27 +819,27 @@ fn mirMulDiv(emit: *Emit, tag: Tag, inst: Mir.Inst.Index) InnerError!void {
816	fn mirIMulComplex(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {	819	fn mirIMulComplex(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
817	const tag = emit.mir.instructions.items(.tag)[inst];	820	const tag = emit.mir.instructions.items(.tag)[inst];
818	assert(tag == .imul_complex);	821	assert(tag == .imul_complex);
819	const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);	822	const ops = emit.mir.instructions.items(.ops)[inst].decode();
820	switch (ops.flags) {	823	switch (ops.flags) {
821	0b00 => {	824	0b00 => {
822	return lowerToRmEnc(.imul, Register.reg(ops.reg1), RegisterOrMemory.reg(ops.reg2), emit.code);	825	return lowerToRmEnc(.imul, ops.reg1, RegisterOrMemory.reg(ops.reg2), emit.code);
823	},	826	},
824	0b01 => {	827	0b01 => {
825	const imm = emit.mir.instructions.items(.data)[inst].imm;	828	const imm = emit.mir.instructions.items(.data)[inst].imm;
826	const src_reg: ?GpRegister = if (ops.reg2 == .none) null else ops.reg2;	829	const src_reg: ?Register = if (ops.reg2 != .none) ops.reg2 else null;
827	return lowerToRmEnc(.imul, Register.reg(ops.reg1), RegisterOrMemory.mem(.qword_ptr, .{	830	return lowerToRmEnc(.imul, ops.reg1, RegisterOrMemory.mem(.qword_ptr, .{
828	.disp = imm,	831	.disp = imm,
829	.base = src_reg,	832	.base = src_reg,
830	}), emit.code);	833	}), emit.code);
831	},	834	},
832	0b10 => {	835	0b10 => {
833	const imm = emit.mir.instructions.items(.data)[inst].imm;	836	const imm = emit.mir.instructions.items(.data)[inst].imm;
834	return lowerToRmiEnc(.imul, Register.reg(ops.reg1), RegisterOrMemory.reg(ops.reg2), imm, emit.code);	837	return lowerToRmiEnc(.imul, ops.reg1, RegisterOrMemory.reg(ops.reg2), imm, emit.code);
835	},	838	},
836	0b11 => {	839	0b11 => {
837	const payload = emit.mir.instructions.items(.data)[inst].payload;	840	const payload = emit.mir.instructions.items(.data)[inst].payload;
838	const imm_pair = emit.mir.extraData(Mir.ImmPair, payload).data;	841	const imm_pair = emit.mir.extraData(Mir.ImmPair, payload).data;
839	return lowerToRmiEnc(.imul, Register.reg(ops.reg1), RegisterOrMemory.mem(.qword_ptr, .{	842	return lowerToRmiEnc(.imul, ops.reg1, RegisterOrMemory.mem(.qword_ptr, .{
840	.disp = imm_pair.dest_off,	843	.disp = imm_pair.dest_off,
841	.base = ops.reg2,	844	.base = ops.reg2,
842	}), imm_pair.operand, emit.code);	845	}), imm_pair.operand, emit.code);
...	@@ -845,7 +848,7 @@ fn mirIMulComplex(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {	...	@@ -845,7 +848,7 @@ fn mirIMulComplex(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
845	}	848	}
846		849
847	fn mirCwd(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {	850	fn mirCwd(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
848	const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);	851	const ops = emit.mir.instructions.items(.ops)[inst].decode();
849	const tag: Tag = switch (ops.flags) {	852	const tag: Tag = switch (ops.flags) {
850	0b00 => .cbw,	853	0b00 => .cbw,
851	0b01 => .cwd,	854	0b01 => .cwd,
...	@@ -858,17 +861,17 @@ fn mirCwd(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {	...	@@ -858,17 +861,17 @@ fn mirCwd(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
858	fn mirLea(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {	861	fn mirLea(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
859	const tag = emit.mir.instructions.items(.tag)[inst];	862	const tag = emit.mir.instructions.items(.tag)[inst];
860	assert(tag == .lea);	863	assert(tag == .lea);
861	const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);	864	const ops = emit.mir.instructions.items(.ops)[inst].decode();
862	switch (ops.flags) {	865	switch (ops.flags) {
863	0b00 => {	866	0b00 => {
864	// lea reg1, [reg2 + imm32]	867	// lea reg1, [reg2 + imm32]
865	// RM	868	// RM
866	const imm = emit.mir.instructions.items(.data)[inst].imm;	869	const imm = emit.mir.instructions.items(.data)[inst].imm;
867	const src_reg: ?GpRegister = if (ops.reg2 == .none) null else ops.reg2;	870	const src_reg: ?Register = if (ops.reg2 != .none) ops.reg2 else null;
868	return lowerToRmEnc(	871	return lowerToRmEnc(
869	.lea,	872	.lea,
870	Register.reg(ops.reg1),	873	ops.reg1,
871	RegisterOrMemory.mem(Memory.PtrSize.fromBits(ops.reg1.size()), .{	874	RegisterOrMemory.mem(Memory.PtrSize.new(ops.reg1.size()), .{
872	.disp = imm,	875	.disp = imm,
873	.base = src_reg,	876	.base = src_reg,
874	}),	877	}),
...	@@ -881,8 +884,8 @@ fn mirLea(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {	...	@@ -881,8 +884,8 @@ fn mirLea(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
881	const start_offset = emit.code.items.len;	884	const start_offset = emit.code.items.len;
882	try lowerToRmEnc(	885	try lowerToRmEnc(
883	.lea,	886	.lea,
884	Register.reg(ops.reg1),	887	ops.reg1,
885	RegisterOrMemory.rip(Memory.PtrSize.fromBits(ops.reg1.size()), 0),	888	RegisterOrMemory.rip(Memory.PtrSize.new(ops.reg1.size()), 0),
886	emit.code,	889	emit.code,
887	);	890	);
888	const end_offset = emit.code.items.len;	891	const end_offset = emit.code.items.len;
...	@@ -895,15 +898,15 @@ fn mirLea(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {	...	@@ -895,15 +898,15 @@ fn mirLea(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
895	0b10 => {	898	0b10 => {
896	// lea reg, [rbp + rcx + imm32]	899	// lea reg, [rbp + rcx + imm32]
897	const imm = emit.mir.instructions.items(.data)[inst].imm;	900	const imm = emit.mir.instructions.items(.data)[inst].imm;
898	const src_reg: ?GpRegister = if (ops.reg2 == .none) null else ops.reg2;	901	const src_reg: ?Register = if (ops.reg2 != .none) ops.reg2 else null;
899	const scale_index = ScaleIndex{	902	const scale_index = ScaleIndex{
900	.scale = 0,	903	.scale = 0,
901	.index = .rcx,	904	.index = .rcx,
902	};	905	};
903	return lowerToRmEnc(	906	return lowerToRmEnc(
904	.lea,	907	.lea,
905	Register.reg(ops.reg1),	908	ops.reg1,
906	RegisterOrMemory.mem(Memory.PtrSize.fromBits(ops.reg1.size()), .{	909	RegisterOrMemory.mem(Memory.PtrSize.new(ops.reg1.size()), .{
907	.disp = imm,	910	.disp = imm,
908	.base = src_reg,	911	.base = src_reg,
909	.scale_index = scale_index,	912	.scale_index = scale_index,
...	@@ -918,15 +921,15 @@ fn mirLea(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {	...	@@ -918,15 +921,15 @@ fn mirLea(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
918	fn mirLeaPie(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {	921	fn mirLeaPie(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
919	const tag = emit.mir.instructions.items(.tag)[inst];	922	const tag = emit.mir.instructions.items(.tag)[inst];
920	assert(tag == .lea_pie);	923	assert(tag == .lea_pie);
921	const ops = Mir.Ops(GpRegister, GpRegister).decode(emit.mir.instructions.items(.ops)[inst]);	924	const ops = emit.mir.instructions.items(.ops)[inst].decode();
922	const load_reloc = emit.mir.instructions.items(.data)[inst].load_reloc;	925	const load_reloc = emit.mir.instructions.items(.data)[inst].load_reloc;
923		926
924	// lea reg1, [rip + reloc]	927	// lea reg1, [rip + reloc]
925	// RM	928	// RM
926	try lowerToRmEnc(	929	try lowerToRmEnc(
927	.lea,	930	.lea,
928	Register.reg(ops.reg1),	931	ops.reg1,
929	RegisterOrMemory.rip(Memory.PtrSize.fromBits(ops.reg1.size()), 0),	932	RegisterOrMemory.rip(Memory.PtrSize.new(ops.reg1.size()), 0),
930	emit.code,	933	emit.code,
931	);	934	);
932		935
...	@@ -962,78 +965,70 @@ fn mirLeaPie(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {	...	@@ -962,78 +965,70 @@ fn mirLeaPie(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
962	fn mirMovF64(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {	965	fn mirMovF64(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
963	const tag = emit.mir.instructions.items(.tag)[inst];	966	const tag = emit.mir.instructions.items(.tag)[inst];
964	assert(tag == .mov_f64);	967	assert(tag == .mov_f64);
965	const ops = emit.mir.instructions.items(.ops)[inst];	968	const ops = emit.mir.instructions.items(.ops)[inst].decode();
966	const flags = @truncate(u2, ops);
967		969
968	switch (flags) {	970	switch (ops.flags) {
969	0b00 => {	971	0b00 => {
970	const decoded = Mir.Ops(AvxRegister, GpRegister).decode(ops);
971	const imm = emit.mir.instructions.items(.data)[inst].imm;	972	const imm = emit.mir.instructions.items(.data)[inst].imm;
972	return lowerToRmEnc(.vmovsd, Register.avxReg(decoded.reg1), RegisterOrMemory.mem(.qword_ptr, .{	973	return lowerToVmEnc(.vmovsd, ops.reg1, RegisterOrMemory.mem(.qword_ptr, .{
973	.disp = imm,	974	.disp = imm,
974	.base = decoded.reg2,	975	.base = ops.reg2,
975	}), emit.code);	976	}), emit.code);
976	},	977	},
977	0b01 => {	978	0b01 => {
978	const decoded = Mir.Ops(GpRegister, AvxRegister).decode(ops);
979	const imm = emit.mir.instructions.items(.data)[inst].imm;	979	const imm = emit.mir.instructions.items(.data)[inst].imm;
980	return lowerToMrEnc(.vmovsd, RegisterOrMemory.mem(.qword_ptr, .{	980	return lowerToMvEnc(.vmovsd, RegisterOrMemory.mem(.qword_ptr, .{
981	.disp = imm,	981	.disp = imm,
982	.base = decoded.reg1,	982	.base = ops.reg1,
983	}), Register.avxReg(decoded.reg2), emit.code);	983	}), ops.reg2, emit.code);
984	},	984	},
985	0b10 => {	985	0b10 => {
986	const decoded = Mir.Ops(AvxRegister, AvxRegister).decode(ops);
987	return lowerToRvmEnc(	986	return lowerToRvmEnc(
988	.vmovsd,	987	.vmovsd,
989	Register.avxReg(decoded.reg1),	988	ops.reg1,
990	Register.avxReg(decoded.reg1),	989	ops.reg1,
991	RegisterOrMemory.avxReg(decoded.reg2),	990	RegisterOrMemory.reg(ops.reg2),
992	emit.code,	991	emit.code,
993	);	992	);
994	},	993	},
995	else => return emit.fail("TODO unused variant 0b{b} for mov_f64", .{flags}),	994	else => return emit.fail("TODO unused variant 0b{b} for mov_f64", .{ops.flags}),
996	}	995	}
997	}	996	}
998		997
999	fn mirAddF64(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {	998	fn mirAddF64(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
1000	const tag = emit.mir.instructions.items(.tag)[inst];	999	const tag = emit.mir.instructions.items(.tag)[inst];
1001	assert(tag == .add_f64);	1000	assert(tag == .add_f64);
1002	const ops = emit.mir.instructions.items(.ops)[inst];	1001	const ops = emit.mir.instructions.items(.ops)[inst].decode();
1003	const flags = @truncate(u2, ops);
1004		1002
1005	switch (flags) {	1003	switch (ops.flags) {
1006	0b00 => {	1004	0b00 => {
1007	const decoded = Mir.Ops(AvxRegister, AvxRegister).decode(ops);
1008	return lowerToRvmEnc(	1005	return lowerToRvmEnc(
1009	.vaddsd,	1006	.vaddsd,
1010	Register.avxReg(decoded.reg1),	1007	ops.reg1,
1011	Register.avxReg(decoded.reg1),	1008	ops.reg1,
1012	RegisterOrMemory.avxReg(decoded.reg2),	1009	RegisterOrMemory.reg(ops.reg2),
1013	emit.code,	1010	emit.code,
1014	);	1011	);
1015	},	1012	},
1016	else => return emit.fail("TODO unused variant 0b{b} for mov_f64", .{flags}),	1013	else => return emit.fail("TODO unused variant 0b{b} for mov_f64", .{ops.flags}),
1017	}	1014	}
1018	}	1015	}
1019		1016
1020	fn mirCmpF64(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {	1017	fn mirCmpF64(emit: *Emit, inst: Mir.Inst.Index) InnerError!void {
1021	const tag = emit.mir.instructions.items(.tag)[inst];	1018	const tag = emit.mir.instructions.items(.tag)[inst];
1022	assert(tag == .cmp_f64);	1019	assert(tag == .cmp_f64);
1023	const ops = emit.mir.instructions.items(.ops)[inst];	1020	const ops = emit.mir.instructions.items(.ops)[inst].decode();
1024	const flags = @truncate(u2, ops);
1025		1021
1026	switch (flags) {	1022	switch (ops.flags) {
1027	0b00 => {	1023	0b00 => {
1028	const decoded = Mir.Ops(AvxRegister, AvxRegister).decode(ops);	1024	return lowerToVmEnc(
1029	return lowerToRmEnc(
1030	.vucomisd,	1025	.vucomisd,
1031	Register.avxReg(decoded.reg1),	1026	ops.reg1,
1032	RegisterOrMemory.avxReg(decoded.reg2),	1027	RegisterOrMemory.reg(ops.reg2),
1033	emit.code,	1028	emit.code,
1034	);	1029	);
1035	},	1030	},
1036	else => return emit.fail("TODO unused variant 0b{b} for mov_f64", .{flags}),	1031	else => return emit.fail("TODO unused variant 0b{b} for mov_f64", .{ops.flags}),
1037	}	1032	}
1038	}	1033	}
1039		1034
...	@@ -1277,6 +1272,18 @@ const Tag = enum {	...	@@ -1277,6 +1272,18 @@ const Tag = enum {
1277	vcmpsd,	1272	vcmpsd,
1278	vucomisd,	1273	vucomisd,
1279		1274
		1275	fn isAvx(tag: Tag) bool {
		1276	return switch (tag) {
		1277	.vmovsd,
		1278	.vaddsd,
		1279	.vcmpsd,
		1280	.vucomisd,
		1281	=> true,
		1282
		1283	else => false,
		1284	};
		1285	}
		1286
1280	fn isSetCC(tag: Tag) bool {	1287	fn isSetCC(tag: Tag) bool {
1281	return switch (tag) {	1288	return switch (tag) {
1282	.seto,	1289	.seto,
...	@@ -1361,6 +1368,12 @@ const Encoding = enum {	...	@@ -1361,6 +1368,12 @@ const Encoding = enum {
1361	/// OP r64, r/m64, imm32	1368	/// OP r64, r/m64, imm32
1362	rmi,	1369	rmi,
1363		1370
		1371	/// OP xmm1, xmm2/m64
		1372	vm,
		1373
		1374	/// OP m64, xmm1
		1375	mv,
		1376
1364	/// OP xmm1, xmm2, xmm3/m64	1377	/// OP xmm1, xmm2, xmm3/m64
1365	rvm,	1378	rvm,
1366		1379
...	@@ -1389,7 +1402,7 @@ const OpCode = union(enum) {	...	@@ -1389,7 +1402,7 @@ const OpCode = union(enum) {
1389		1402
1390	fn encodeWithReg(opc: OpCode, encoder: Encoder, reg: Register) void {	1403	fn encodeWithReg(opc: OpCode, encoder: Encoder, reg: Register) void {
1391	assert(opc == .one_byte);	1404	assert(opc == .one_byte);
1392	encoder.opcode_withReg(opc.one_byte, reg.lowId());	1405	encoder.opcode_withReg(opc.one_byte, reg.lowEnc());
1393	}	1406	}
1394	};	1407	};
1395		1408
...	@@ -1536,6 +1549,15 @@ inline fn getOpCode(tag: Tag, enc: Encoding, is_one_byte: bool) ?OpCode {	...	@@ -1536,6 +1549,15 @@ inline fn getOpCode(tag: Tag, enc: Encoding, is_one_byte: bool) ?OpCode {
1536	.imul => OpCode.oneByte(if (is_one_byte) 0x6b else 0x69),	1549	.imul => OpCode.oneByte(if (is_one_byte) 0x6b else 0x69),
1537	else => null,	1550	else => null,
1538	},	1551	},
		1552	.mv => return switch (tag) {
		1553	.vmovsd => OpCode.oneByte(0x11),
		1554	else => null,
		1555	},
		1556	.vm => return switch (tag) {
		1557	.vmovsd => OpCode.oneByte(0x10),
		1558	.vucomisd => OpCode.oneByte(0x2e),
		1559	else => null,
		1560	},
1539	.rvm => return switch (tag) {	1561	.rvm => return switch (tag) {
1540	.vaddsd => OpCode.oneByte(0x58),	1562	.vaddsd => OpCode.oneByte(0x58),
1541	.vmovsd => OpCode.oneByte(0x10),	1563	.vmovsd => OpCode.oneByte(0x10),
...	@@ -1647,11 +1669,11 @@ inline fn getVexPrefix(tag: Tag, enc: Encoding) ?VexPrefix {	...	@@ -1647,11 +1669,11 @@ inline fn getVexPrefix(tag: Tag, enc: Encoding) ?VexPrefix {
1647	} = .none,	1669	} = .none,
1648	} = blk: {	1670	} = blk: {
1649	switch (enc) {	1671	switch (enc) {
1650	.mr => switch (tag) {	1672	.mv => switch (tag) {
1651	.vmovsd => break :blk .{ .lig = true, .simd_prefix = .p_f2, .wig = true },	1673	.vmovsd => break :blk .{ .lig = true, .simd_prefix = .p_f2, .wig = true },
1652	else => return null,	1674	else => return null,
1653	},	1675	},
1654	.rm => switch (tag) {	1676	.vm => switch (tag) {
1655	.vmovsd => break :blk .{ .lig = true, .simd_prefix = .p_f2, .wig = true },	1677	.vmovsd => break :blk .{ .lig = true, .simd_prefix = .p_f2, .wig = true },
1656	.vucomisd => break :blk .{ .lig = true, .simd_prefix = .p_66, .wig = true },	1678	.vucomisd => break :blk .{ .lig = true, .simd_prefix = .p_66, .wig = true },
1657	else => return null,	1679	else => return null,
...	@@ -1697,61 +1719,50 @@ inline fn getVexPrefix(tag: Tag, enc: Encoding) ?VexPrefix {	...	@@ -1697,61 +1719,50 @@ inline fn getVexPrefix(tag: Tag, enc: Encoding) ?VexPrefix {
1697	} };	1719	} };
1698	}	1720	}
1699		1721
1700	const ScaleIndex = struct {	1722	const ScaleIndex = packed struct {
1701	scale: u2,	1723	scale: u2,
1702	index: GpRegister,	1724	index: Register,
1703	};	1725	};
1704		1726
1705	const Memory = struct {	1727	const Memory = struct {
1706	base: ?GpRegister,	1728	base: ?Register,
1707	rip: bool = false,	1729	rip: bool = false,
1708	disp: u32,	1730	disp: u32,
1709	ptr_size: PtrSize,	1731	ptr_size: PtrSize,
1710	scale_index: ?ScaleIndex = null,	1732	scale_index: ?ScaleIndex = null,
1711		1733
1712	const PtrSize = enum {	1734	const PtrSize = enum(u2) {
1713	byte_ptr,	1735	byte_ptr = 0b00,
1714	word_ptr,	1736	word_ptr = 0b01,
1715	dword_ptr,	1737	dword_ptr = 0b10,
1716	qword_ptr,	1738	qword_ptr = 0b11,
1717		1739
1718	fn fromBits(in_bits: u64) PtrSize {	1740	fn new(bit_size: u64) PtrSize {
1719	return switch (in_bits) {	1741	return @intToEnum(PtrSize, math.log2_int(u4, @intCast(u4, @divExact(bit_size, 8))));
1720	8 => .byte_ptr,
1721	16 => .word_ptr,
1722	32 => .dword_ptr,
1723	64 => .qword_ptr,
1724	else => unreachable,
1725	};
1726	}	1742	}
1727		1743
1728	/// Returns size in bits.	1744	/// Returns size in bits.
1729	fn size(ptr_size: PtrSize) u64 {	1745	fn size(ptr_size: PtrSize) u64 {
1730	return switch (ptr_size) {	1746	return 8 * (math.powi(u8, 2, @enumToInt(ptr_size)) catch unreachable);
1731	.byte_ptr => 8,
1732	.word_ptr => 16,
1733	.dword_ptr => 32,
1734	.qword_ptr => 64,
1735	};
1736	}	1747	}
1737	};	1748	};
1738		1749
1739	fn encode(mem_op: Memory, encoder: Encoder, operand: u3) void {	1750	fn encode(mem_op: Memory, encoder: Encoder, operand: u3) void {
1740	if (mem_op.base) \|base\| {	1751	if (mem_op.base) \|base\| {
1741	const dst = base.lowId();	1752	const dst = base.lowEnc();
1742	const src = operand;	1753	const src = operand;
1743	if (dst == 4 or mem_op.scale_index != null) {	1754	if (dst == 4 or mem_op.scale_index != null) {
1744	if (mem_op.disp == 0 and dst != 5) {	1755	if (mem_op.disp == 0 and dst != 5) {
1745	encoder.modRm_SIBDisp0(src);	1756	encoder.modRm_SIBDisp0(src);
1746	if (mem_op.scale_index) \|si\| {	1757	if (mem_op.scale_index) \|si\| {
1747	encoder.sib_scaleIndexBase(si.scale, si.index.lowId(), dst);	1758	encoder.sib_scaleIndexBase(si.scale, si.index.lowEnc(), dst);
1748	} else {	1759	} else {
1749	encoder.sib_base(dst);	1760	encoder.sib_base(dst);
1750	}	1761	}
1751	} else if (immOpSize(mem_op.disp) == 8) {	1762	} else if (immOpSize(mem_op.disp) == 8) {
1752	encoder.modRm_SIBDisp8(src);	1763	encoder.modRm_SIBDisp8(src);
1753	if (mem_op.scale_index) \|si\| {	1764	if (mem_op.scale_index) \|si\| {
1754	encoder.sib_scaleIndexBaseDisp8(si.scale, si.index.lowId(), dst);	1765	encoder.sib_scaleIndexBaseDisp8(si.scale, si.index.lowEnc(), dst);
1755	} else {	1766	} else {
1756	encoder.sib_baseDisp8(dst);	1767	encoder.sib_baseDisp8(dst);
1757	}	1768	}
...	@@ -1759,7 +1770,7 @@ const Memory = struct {	...	@@ -1759,7 +1770,7 @@ const Memory = struct {
1759	} else {	1770	} else {
1760	encoder.modRm_SIBDisp32(src);	1771	encoder.modRm_SIBDisp32(src);
1761	if (mem_op.scale_index) \|si\| {	1772	if (mem_op.scale_index) \|si\| {
1762	encoder.sib_scaleIndexBaseDisp32(si.scale, si.index.lowId(), dst);	1773	encoder.sib_scaleIndexBaseDisp32(si.scale, si.index.lowEnc(), dst);
1763	} else {	1774	} else {
1764	encoder.sib_baseDisp32(dst);	1775	encoder.sib_baseDisp32(dst);
1765	}	1776	}
...	@@ -1782,7 +1793,7 @@ const Memory = struct {	...	@@ -1782,7 +1793,7 @@ const Memory = struct {
1782	} else {	1793	} else {
1783	encoder.modRm_SIBDisp0(operand);	1794	encoder.modRm_SIBDisp0(operand);
1784	if (mem_op.scale_index) \|si\| {	1795	if (mem_op.scale_index) \|si\| {
1785	encoder.sib_scaleIndexDisp32(si.scale, si.index.lowId());	1796	encoder.sib_scaleIndexDisp32(si.scale, si.index.lowEnc());
1786	} else {	1797	} else {
1787	encoder.sib_disp32();	1798	encoder.sib_disp32();
1788	}	1799	}
...	@@ -1791,6 +1802,7 @@ const Memory = struct {	...	@@ -1791,6 +1802,7 @@ const Memory = struct {
1791	}	1802	}
1792	}	1803	}
1793		1804
		1805	/// Returns size in bits.
1794	fn size(memory: Memory) u64 {	1806	fn size(memory: Memory) u64 {
1795	return memory.ptr_size.size();	1807	return memory.ptr_size.size();
1796	}	1808	}
...	@@ -1805,55 +1817,17 @@ fn encodeImm(encoder: Encoder, imm: u32, size: u64) void {	...	@@ -1805,55 +1817,17 @@ fn encodeImm(encoder: Encoder, imm: u32, size: u64) void {
1805	}	1817	}
1806	}	1818	}
1807		1819
1808	const Register = union(enum) {
1809	register: GpRegister,
1810	avx_register: AvxRegister,
1811
1812	fn reg(register: GpRegister) Register {
1813	return .{ .register = register };
1814	}
1815
1816	fn avxReg(register: AvxRegister) Register {
1817	return .{ .avx_register = register };
1818	}
1819
1820	fn lowId(register: Register) u3 {
1821	return switch (register) {
1822	.register => \|r\| r.lowId(),
1823	.avx_register => \|r\| r.lowId(),
1824	};
1825	}
1826
1827	fn size(register: Register) u64 {
1828	return switch (register) {
1829	.register => \|r\| r.size(),
1830	.avx_register => \|r\| r.size(),
1831	};
1832	}
1833
1834	fn isExtended(register: Register) bool {
1835	return switch (register) {
1836	.register => \|r\| r.isExtended(),
1837	.avx_register => \|r\| r.isExtended(),
1838	};
1839	}
1840	};
1841
1842	const RegisterOrMemory = union(enum) {	1820	const RegisterOrMemory = union(enum) {
1843	register: Register,	1821	register: Register,
1844	memory: Memory,	1822	memory: Memory,
1845		1823
1846	fn reg(register: GpRegister) RegisterOrMemory {	1824	fn reg(register: Register) RegisterOrMemory {
1847	return .{ .register = Register.reg(register) };	1825	return .{ .register = register };
1848	}
1849
1850	fn avxReg(register: AvxRegister) RegisterOrMemory {
1851	return .{ .register = Register.avxReg(register) };
1852	}	1826	}
1853		1827
1854	fn mem(ptr_size: Memory.PtrSize, args: struct {	1828	fn mem(ptr_size: Memory.PtrSize, args: struct {
1855	disp: u32,	1829	disp: u32,
1856	base: ?GpRegister = null,	1830	base: ?Register = null,
1857	scale_index: ?ScaleIndex = null,	1831	scale_index: ?ScaleIndex = null,
1858	}) RegisterOrMemory {	1832	}) RegisterOrMemory {
1859	return .{	1833	return .{
...	@@ -1877,6 +1851,7 @@ const RegisterOrMemory = union(enum) {	...	@@ -1877,6 +1851,7 @@ const RegisterOrMemory = union(enum) {
1877	};	1851	};
1878	}	1852	}
1879		1853
		1854	/// Returns size in bits.
1880	fn size(reg_or_mem: RegisterOrMemory) u64 {	1855	fn size(reg_or_mem: RegisterOrMemory) u64 {
1881	return switch (reg_or_mem) {	1856	return switch (reg_or_mem) {
1882	.register => \|reg\| reg.size(),	1857	.register => \|reg\| reg.size(),
...	@@ -1886,6 +1861,7 @@ const RegisterOrMemory = union(enum) {	...	@@ -1886,6 +1861,7 @@ const RegisterOrMemory = union(enum) {
1886	};	1861	};
1887		1862
1888	fn lowerToZoEnc(tag: Tag, code: *std.ArrayList(u8)) InnerError!void {	1863	fn lowerToZoEnc(tag: Tag, code: *std.ArrayList(u8)) InnerError!void {
		1864	assert(!tag.isAvx());
1889	const opc = getOpCode(tag, .zo, false).?;	1865	const opc = getOpCode(tag, .zo, false).?;
1890	const encoder = try Encoder.init(code, 2);	1866	const encoder = try Encoder.init(code, 2);
1891	switch (tag) {	1867	switch (tag) {
...	@@ -1900,6 +1876,7 @@ fn lowerToZoEnc(tag: Tag, code: *std.ArrayList(u8)) InnerError!void {	...	@@ -1900,6 +1876,7 @@ fn lowerToZoEnc(tag: Tag, code: *std.ArrayList(u8)) InnerError!void {
1900	}	1876	}
1901		1877
1902	fn lowerToIEnc(tag: Tag, imm: u32, code: *std.ArrayList(u8)) InnerError!void {	1878	fn lowerToIEnc(tag: Tag, imm: u32, code: *std.ArrayList(u8)) InnerError!void {
		1879	assert(!tag.isAvx());
1903	if (tag == .ret_far or tag == .ret_near) {	1880	if (tag == .ret_far or tag == .ret_near) {
1904	const encoder = try Encoder.init(code, 3);	1881	const encoder = try Encoder.init(code, 3);
1905	const opc = getOpCode(tag, .i, false).?;	1882	const opc = getOpCode(tag, .i, false).?;
...	@@ -1917,6 +1894,7 @@ fn lowerToIEnc(tag: Tag, imm: u32, code: *std.ArrayList(u8)) InnerError!void {	...	@@ -1917,6 +1894,7 @@ fn lowerToIEnc(tag: Tag, imm: u32, code: *std.ArrayList(u8)) InnerError!void {
1917	}	1894	}
1918		1895
1919	fn lowerToOEnc(tag: Tag, reg: Register, code: *std.ArrayList(u8)) InnerError!void {	1896	fn lowerToOEnc(tag: Tag, reg: Register, code: *std.ArrayList(u8)) InnerError!void {
		1897	assert(!tag.isAvx());
1920	const opc = getOpCode(tag, .o, false).?;	1898	const opc = getOpCode(tag, .o, false).?;
1921	const encoder = try Encoder.init(code, 3);	1899	const encoder = try Encoder.init(code, 3);
1922	if (reg.size() == 16) {	1900	if (reg.size() == 16) {
...	@@ -1930,6 +1908,7 @@ fn lowerToOEnc(tag: Tag, reg: Register, code: *std.ArrayList(u8)) InnerError!voi	...	@@ -1930,6 +1908,7 @@ fn lowerToOEnc(tag: Tag, reg: Register, code: *std.ArrayList(u8)) InnerError!voi
1930	}	1908	}
1931		1909
1932	fn lowerToDEnc(tag: Tag, imm: u32, code: *std.ArrayList(u8)) InnerError!void {	1910	fn lowerToDEnc(tag: Tag, imm: u32, code: *std.ArrayList(u8)) InnerError!void {
		1911	assert(!tag.isAvx());
1933	const opc = getOpCode(tag, .d, false).?;	1912	const opc = getOpCode(tag, .d, false).?;
1934	const encoder = try Encoder.init(code, 6);	1913	const encoder = try Encoder.init(code, 6);
1935	opc.encode(encoder);	1914	opc.encode(encoder);
...	@@ -1937,6 +1916,7 @@ fn lowerToDEnc(tag: Tag, imm: u32, code: *std.ArrayList(u8)) InnerError!void {	...	@@ -1937,6 +1916,7 @@ fn lowerToDEnc(tag: Tag, imm: u32, code: *std.ArrayList(u8)) InnerError!void {
1937	}	1916	}
1938		1917
1939	fn lowerToMxEnc(tag: Tag, reg_or_mem: RegisterOrMemory, enc: Encoding, code: *std.ArrayList(u8)) InnerError!void {	1918	fn lowerToMxEnc(tag: Tag, reg_or_mem: RegisterOrMemory, enc: Encoding, code: *std.ArrayList(u8)) InnerError!void {
		1919	assert(!tag.isAvx());
1940	const opc = getOpCode(tag, enc, reg_or_mem.size() == 8).?;	1920	const opc = getOpCode(tag, enc, reg_or_mem.size() == 8).?;
1941	const modrm_ext = getModRmExt(tag).?;	1921	const modrm_ext = getModRmExt(tag).?;
1942	switch (reg_or_mem) {	1922	switch (reg_or_mem) {
...	@@ -1951,7 +1931,7 @@ fn lowerToMxEnc(tag: Tag, reg_or_mem: RegisterOrMemory, enc: Encoding, code: *st	...	@@ -1951,7 +1931,7 @@ fn lowerToMxEnc(tag: Tag, reg_or_mem: RegisterOrMemory, enc: Encoding, code: *st
1951	.b = reg.isExtended(),	1931	.b = reg.isExtended(),
1952	});	1932	});
1953	opc.encode(encoder);	1933	opc.encode(encoder);
1954	encoder.modRm_direct(modrm_ext, reg.lowId());	1934	encoder.modRm_direct(modrm_ext, reg.lowEnc());
1955	},	1935	},
1956	.memory => \|mem_op\| {	1936	.memory => \|mem_op\| {
1957	const encoder = try Encoder.init(code, 8);	1937	const encoder = try Encoder.init(code, 8);
...	@@ -1992,6 +1972,7 @@ fn lowerToFdEnc(tag: Tag, reg: Register, moffs: u64, code: *std.ArrayList(u8)) I	...	@@ -1992,6 +1972,7 @@ fn lowerToFdEnc(tag: Tag, reg: Register, moffs: u64, code: *std.ArrayList(u8)) I
1992	}	1972	}
1993		1973
1994	fn lowerToTdFdEnc(tag: Tag, reg: Register, moffs: u64, code: *std.ArrayList(u8), td: bool) InnerError!void {	1974	fn lowerToTdFdEnc(tag: Tag, reg: Register, moffs: u64, code: *std.ArrayList(u8), td: bool) InnerError!void {
		1975	assert(!tag.isAvx());
1995	const opc = if (td)	1976	const opc = if (td)
1996	getOpCode(tag, .td, reg.size() == 8).?	1977	getOpCode(tag, .td, reg.size() == 8).?
1997	else	1978	else
...	@@ -2014,6 +1995,7 @@ fn lowerToTdFdEnc(tag: Tag, reg: Register, moffs: u64, code: *std.ArrayList(u8),	...	@@ -2014,6 +1995,7 @@ fn lowerToTdFdEnc(tag: Tag, reg: Register, moffs: u64, code: *std.ArrayList(u8),
2014	}	1995	}
2015		1996
2016	fn lowerToOiEnc(tag: Tag, reg: Register, imm: u64, code: *std.ArrayList(u8)) InnerError!void {	1997	fn lowerToOiEnc(tag: Tag, reg: Register, imm: u64, code: *std.ArrayList(u8)) InnerError!void {
		1998	assert(!tag.isAvx());
2017	const opc = getOpCode(tag, .oi, reg.size() == 8).?;	1999	const opc = getOpCode(tag, .oi, reg.size() == 8).?;
2018	const encoder = try Encoder.init(code, 10);	2000	const encoder = try Encoder.init(code, 10);
2019	if (reg.size() == 16) {	2001	if (reg.size() == 16) {
...	@@ -2040,6 +2022,7 @@ fn lowerToMiXEnc(	...	@@ -2040,6 +2022,7 @@ fn lowerToMiXEnc(
2040	enc: Encoding,	2022	enc: Encoding,
2041	code: *std.ArrayList(u8),	2023	code: *std.ArrayList(u8),
2042	) InnerError!void {	2024	) InnerError!void {
		2025	assert(!tag.isAvx());
2043	const modrm_ext = getModRmExt(tag).?;	2026	const modrm_ext = getModRmExt(tag).?;
2044	const opc = getOpCode(tag, enc, reg_or_mem.size() == 8).?;	2027	const opc = getOpCode(tag, enc, reg_or_mem.size() == 8).?;
2045	switch (reg_or_mem) {	2028	switch (reg_or_mem) {
...	@@ -2056,7 +2039,7 @@ fn lowerToMiXEnc(	...	@@ -2056,7 +2039,7 @@ fn lowerToMiXEnc(
2056	.b = dst_reg.isExtended(),	2039	.b = dst_reg.isExtended(),
2057	});	2040	});
2058	opc.encode(encoder);	2041	opc.encode(encoder);
2059	encoder.modRm_direct(modrm_ext, dst_reg.lowId());	2042	encoder.modRm_direct(modrm_ext, dst_reg.lowEnc());
2060	encodeImm(encoder, imm, if (enc == .mi8) 8 else dst_reg.size());	2043	encodeImm(encoder, imm, if (enc == .mi8) 8 else dst_reg.size());
2061	},	2044	},
2062	.memory => \|dst_mem\| {	2045	.memory => \|dst_mem\| {
...	@@ -2095,84 +2078,43 @@ fn lowerToRmEnc(	...	@@ -2095,84 +2078,43 @@ fn lowerToRmEnc(
2095	reg_or_mem: RegisterOrMemory,	2078	reg_or_mem: RegisterOrMemory,
2096	code: *std.ArrayList(u8),	2079	code: *std.ArrayList(u8),
2097	) InnerError!void {	2080	) InnerError!void {
		2081	assert(!tag.isAvx());
2098	const opc = getOpCode(tag, .rm, reg.size() == 8 or reg_or_mem.size() == 8).?;	2082	const opc = getOpCode(tag, .rm, reg.size() == 8 or reg_or_mem.size() == 8).?;
2099	switch (reg_or_mem) {	2083	switch (reg_or_mem) {
2100	.register => \|src_reg\| {	2084	.register => \|src_reg\| {
2101	const encoder: Encoder = blk: {	2085	const encoder = try Encoder.init(code, 5);
2102	switch (reg) {	2086	if (reg.size() == 16) {
2103	.register => {	2087	encoder.prefix16BitMode();
2104	const encoder = try Encoder.init(code, 4);	2088	}
2105	if (reg.size() == 16) {	2089	encoder.rex(.{
2106	encoder.prefix16BitMode();	2090	.w = setRexWRegister(reg) or setRexWRegister(src_reg),
2107	}	2091	.r = reg.isExtended(),
2108	encoder.rex(.{	2092	.b = src_reg.isExtended(),
2109	.w = setRexWRegister(reg) or setRexWRegister(src_reg),	2093	});
2110	.r = reg.isExtended(),
2111	.b = src_reg.isExtended(),
2112	});
2113	break :blk encoder;
2114	},
2115	.avx_register => {
2116	const encoder = try Encoder.init(code, 5);
2117	var vex_prefix = getVexPrefix(tag, .rm).?;
2118	const vex = &vex_prefix.prefix;
2119	vex.rex(.{
2120	.r = reg.isExtended(),
2121	.b = src_reg.isExtended(),
2122	});
2123	encoder.vex(vex_prefix.prefix);
2124	break :blk encoder;
2125	},
2126	}
2127	};
2128	opc.encode(encoder);	2094	opc.encode(encoder);
2129	encoder.modRm_direct(reg.lowId(), src_reg.lowId());	2095	encoder.modRm_direct(reg.lowEnc(), src_reg.lowEnc());
2130	},	2096	},
2131	.memory => \|src_mem\| {	2097	.memory => \|src_mem\| {
2132	const encoder: Encoder = blk: {	2098	const encoder = try Encoder.init(code, 9);
2133	switch (reg) {	2099	if (reg.size() == 16) {
2134	.register => {	2100	encoder.prefix16BitMode();
2135	const encoder = try Encoder.init(code, 9);	2101	}
2136	if (reg.size() == 16) {	2102	if (src_mem.base) \|base\| {
2137	encoder.prefix16BitMode();	2103	// TODO handle 32-bit base register - requires prefix 0x67
2138	}	2104	// Intel Manual, Vol 1, chapter 3.6 and 3.6.1
2139	if (src_mem.base) \|base\| {	2105	encoder.rex(.{
2140	// TODO handle 32-bit base register - requires prefix 0x67	2106	.w = setRexWRegister(reg),
2141	// Intel Manual, Vol 1, chapter 3.6 and 3.6.1	2107	.r = reg.isExtended(),
2142	encoder.rex(.{	2108	.b = base.isExtended(),
2143	.w = setRexWRegister(reg),	2109	});
2144	.r = reg.isExtended(),	2110	} else {
2145	.b = base.isExtended(),	2111	encoder.rex(.{
2146	});	2112	.w = setRexWRegister(reg),
2147	} else {	2113	.r = reg.isExtended(),
2148	encoder.rex(.{	2114	});
2149	.w = setRexWRegister(reg),	2115	}
2150	.r = reg.isExtended(),
2151	});
2152	}
2153	break :blk encoder;
2154	},
2155	.avx_register => {
2156	const encoder = try Encoder.init(code, 10);
2157	var vex_prefix = getVexPrefix(tag, .rm).?;
2158	const vex = &vex_prefix.prefix;
2159	if (src_mem.base) \|base\| {
2160	vex.rex(.{
2161	.r = reg.isExtended(),
2162	.b = base.isExtended(),
2163	});
2164	} else {
2165	vex.rex(.{
2166	.r = reg.isExtended(),
2167	});
2168	}
2169	encoder.vex(vex_prefix.prefix);
2170	break :blk encoder;
2171	},
2172	}
2173	};
2174	opc.encode(encoder);	2116	opc.encode(encoder);
2175	src_mem.encode(encoder, reg.lowId());	2117	src_mem.encode(encoder, reg.lowEnc());
2176	},	2118	},
2177	}	2119	}
2178	}	2120	}
...	@@ -2183,6 +2125,7 @@ fn lowerToMrEnc(	...	@@ -2183,6 +2125,7 @@ fn lowerToMrEnc(
2183	reg: Register,	2125	reg: Register,
2184	code: *std.ArrayList(u8),	2126	code: *std.ArrayList(u8),
2185	) InnerError!void {	2127	) InnerError!void {
		2128	assert(!tag.isAvx());
2186	const opc = getOpCode(tag, .mr, reg.size() == 8 or reg_or_mem.size() == 8).?;	2129	const opc = getOpCode(tag, .mr, reg.size() == 8 or reg_or_mem.size() == 8).?;
2187	switch (reg_or_mem) {	2130	switch (reg_or_mem) {
2188	.register => \|dst_reg\| {	2131	.register => \|dst_reg\| {
...	@@ -2196,53 +2139,27 @@ fn lowerToMrEnc(	...	@@ -2196,53 +2139,27 @@ fn lowerToMrEnc(
2196	.b = dst_reg.isExtended(),	2139	.b = dst_reg.isExtended(),
2197	});	2140	});
2198	opc.encode(encoder);	2141	opc.encode(encoder);
2199	encoder.modRm_direct(reg.lowId(), dst_reg.lowId());	2142	encoder.modRm_direct(reg.lowEnc(), dst_reg.lowEnc());
2200	},	2143	},
2201	.memory => \|dst_mem\| {	2144	.memory => \|dst_mem\| {
2202	const encoder: Encoder = blk: {	2145	const encoder = try Encoder.init(code, 9);
2203	switch (reg) {	2146	if (reg.size() == 16) {
2204	.register => {	2147	encoder.prefix16BitMode();
2205	const encoder = try Encoder.init(code, 9);	2148	}
2206	if (reg.size() == 16) {	2149	if (dst_mem.base) \|base\| {
2207	encoder.prefix16BitMode();	2150	encoder.rex(.{
2208	}	2151	.w = dst_mem.ptr_size == .qword_ptr or setRexWRegister(reg),
2209	if (dst_mem.base) \|base\| {	2152	.r = reg.isExtended(),
2210	encoder.rex(.{	2153	.b = base.isExtended(),
2211	.w = dst_mem.ptr_size == .qword_ptr or setRexWRegister(reg),	2154	});
2212	.r = reg.isExtended(),	2155	} else {
2213	.b = base.isExtended(),	2156	encoder.rex(.{
2214	});	2157	.w = dst_mem.ptr_size == .qword_ptr or setRexWRegister(reg),
2215	} else {	2158	.r = reg.isExtended(),
2216	encoder.rex(.{	2159	});
2217	.w = dst_mem.ptr_size == .qword_ptr or setRexWRegister(reg),	2160	}
2218	.r = reg.isExtended(),
2219	});
2220	}
2221	break :blk encoder;
2222	},
2223	.avx_register => {
2224	const encoder = try Encoder.init(code, 10);
2225	var vex_prefix = getVexPrefix(tag, .mr).?;
2226	const vex = &vex_prefix.prefix;
2227	if (dst_mem.base) \|base\| {
2228	vex.rex(.{
2229	.w = dst_mem.ptr_size == .qword_ptr,
2230	.r = reg.isExtended(),
2231	.b = base.isExtended(),
2232	});
2233	} else {
2234	vex.rex(.{
2235	.w = dst_mem.ptr_size == .qword_ptr,
2236	.r = reg.isExtended(),
2237	});
2238	}
2239	encoder.vex(vex_prefix.prefix);
2240	break :blk encoder;
2241	},
2242	}
2243	};
2244	opc.encode(encoder);	2161	opc.encode(encoder);
2245	dst_mem.encode(encoder, reg.lowId());	2162	dst_mem.encode(encoder, reg.lowEnc());
2246	},	2163	},
2247	}	2164	}
2248	}	2165	}
...	@@ -2254,6 +2171,7 @@ fn lowerToRmiEnc(	...	@@ -2254,6 +2171,7 @@ fn lowerToRmiEnc(
2254	imm: u32,	2171	imm: u32,
2255	code: *std.ArrayList(u8),	2172	code: *std.ArrayList(u8),
2256	) InnerError!void {	2173	) InnerError!void {
		2174	assert(!tag.isAvx());
2257	const opc = getOpCode(tag, .rmi, false).?;	2175	const opc = getOpCode(tag, .rmi, false).?;
2258	const encoder = try Encoder.init(code, 13);	2176	const encoder = try Encoder.init(code, 13);
2259	if (reg.size() == 16) {	2177	if (reg.size() == 16) {
...	@@ -2267,7 +2185,7 @@ fn lowerToRmiEnc(	...	@@ -2267,7 +2185,7 @@ fn lowerToRmiEnc(
2267	.b = src_reg.isExtended(),	2185	.b = src_reg.isExtended(),
2268	});	2186	});
2269	opc.encode(encoder);	2187	opc.encode(encoder);
2270	encoder.modRm_direct(reg.lowId(), src_reg.lowId());	2188	encoder.modRm_direct(reg.lowEnc(), src_reg.lowEnc());
2271	},	2189	},
2272	.memory => \|src_mem\| {	2190	.memory => \|src_mem\| {
2273	if (src_mem.base) \|base\| {	2191	if (src_mem.base) \|base\| {
...	@@ -2285,12 +2203,94 @@ fn lowerToRmiEnc(	...	@@ -2285,12 +2203,94 @@ fn lowerToRmiEnc(
2285	});	2203	});
2286	}	2204	}
2287	opc.encode(encoder);	2205	opc.encode(encoder);
2288	src_mem.encode(encoder, reg.lowId());	2206	src_mem.encode(encoder, reg.lowEnc());
2289	},	2207	},
2290	}	2208	}
2291	encodeImm(encoder, imm, reg.size());	2209	encodeImm(encoder, imm, reg.size());
2292	}	2210	}
2293		2211
		2212	/// Also referred to as XM encoding in Intel manual.
		2213	fn lowerToVmEnc(
		2214	tag: Tag,
		2215	reg: Register,
		2216	reg_or_mem: RegisterOrMemory,
		2217	code: *std.ArrayList(u8),
		2218	) InnerError!void {
		2219	const opc = getOpCode(tag, .vm, false).?;
		2220	var vex_prefix = getVexPrefix(tag, .vm).?;
		2221	const vex = &vex_prefix.prefix;
		2222	switch (reg_or_mem) {
		2223	.register => \|src_reg\| {
		2224	const encoder = try Encoder.init(code, 5);
		2225	vex.rex(.{
		2226	.r = reg.isExtended(),
		2227	.b = src_reg.isExtended(),
		2228	});
		2229	encoder.vex(vex_prefix.prefix);
		2230	opc.encode(encoder);
		2231	encoder.modRm_direct(reg.lowEnc(), src_reg.lowEnc());
		2232	},
		2233	.memory => \|src_mem\| {
		2234	assert(src_mem.ptr_size == .qword_ptr);
		2235	const encoder = try Encoder.init(code, 10);
		2236	if (src_mem.base) \|base\| {
		2237	vex.rex(.{
		2238	.r = reg.isExtended(),
		2239	.b = base.isExtended(),
		2240	});
		2241	} else {
		2242	vex.rex(.{
		2243	.r = reg.isExtended(),
		2244	});
		2245	}
		2246	encoder.vex(vex_prefix.prefix);
		2247	opc.encode(encoder);
		2248	src_mem.encode(encoder, reg.lowEnc());
		2249	},
		2250	}
		2251	}
		2252
		2253	/// Usually referred to as MR encoding with V/V in Intel manual.
		2254	fn lowerToMvEnc(
		2255	tag: Tag,
		2256	reg_or_mem: RegisterOrMemory,
		2257	reg: Register,
		2258	code: *std.ArrayList(u8),
		2259	) InnerError!void {
		2260	const opc = getOpCode(tag, .mv, false).?;
		2261	var vex_prefix = getVexPrefix(tag, .mv).?;
		2262	const vex = &vex_prefix.prefix;
		2263	switch (reg_or_mem) {
		2264	.register => \|dst_reg\| {
		2265	const encoder = try Encoder.init(code, 4);
		2266	vex.rex(.{
		2267	.r = reg.isExtended(),
		2268	.b = dst_reg.isExtended(),
		2269	});
		2270	encoder.vex(vex_prefix.prefix);
		2271	opc.encode(encoder);
		2272	encoder.modRm_direct(reg.lowEnc(), dst_reg.lowEnc());
		2273	},
		2274	.memory => \|dst_mem\| {
		2275	assert(dst_mem.ptr_size == .qword_ptr);
		2276	const encoder = try Encoder.init(code, 10);
		2277	if (dst_mem.base) \|base\| {
		2278	vex.rex(.{
		2279	.r = reg.isExtended(),
		2280	.b = base.isExtended(),
		2281	});
		2282	} else {
		2283	vex.rex(.{
		2284	.r = reg.isExtended(),
		2285	});
		2286	}
		2287	encoder.vex(vex_prefix.prefix);
		2288	opc.encode(encoder);
		2289	dst_mem.encode(encoder, reg.lowEnc());
		2290	},
		2291	}
		2292	}
		2293
2294	fn lowerToRvmEnc(	2294	fn lowerToRvmEnc(
2295	tag: Tag,	2295	tag: Tag,
2296	reg1: Register,	2296	reg1: Register,
...	@@ -2305,7 +2305,7 @@ fn lowerToRvmEnc(	...	@@ -2305,7 +2305,7 @@ fn lowerToRvmEnc(
2305	.register => \|reg3\| {	2305	.register => \|reg3\| {
2306	if (vex_prefix.reg) \|vvvv\| {	2306	if (vex_prefix.reg) \|vvvv\| {
2307	switch (vvvv) {	2307	switch (vvvv) {
2308	.nds => vex.reg(reg2.avx_register.id()),	2308	.nds => vex.reg(reg2.enc()),
2309	else => unreachable, // TODO	2309	else => unreachable, // TODO
2310	}	2310	}
2311	}	2311	}
...	@@ -2316,7 +2316,7 @@ fn lowerToRvmEnc(	...	@@ -2316,7 +2316,7 @@ fn lowerToRvmEnc(
2316	});	2316	});
2317	encoder.vex(vex_prefix.prefix);	2317	encoder.vex(vex_prefix.prefix);
2318	opc.encode(encoder);	2318	opc.encode(encoder);
2319	encoder.modRm_direct(reg1.lowId(), reg3.lowId());	2319	encoder.modRm_direct(reg1.lowEnc(), reg3.lowEnc());
2320	},	2320	},
2321	.memory => \|dst_mem\| {	2321	.memory => \|dst_mem\| {
2322	_ = dst_mem;	2322	_ = dst_mem;
...	@@ -2341,7 +2341,7 @@ fn lowerToRvmiEnc(	...	@@ -2341,7 +2341,7 @@ fn lowerToRvmiEnc(
2341	.register => \|reg3\| {	2341	.register => \|reg3\| {
2342	if (vex_prefix.reg) \|vvvv\| {	2342	if (vex_prefix.reg) \|vvvv\| {
2343	switch (vvvv) {	2343	switch (vvvv) {
2344	.nds => vex.reg(reg2.avx_register.id()),	2344	.nds => vex.reg(reg2.enc()),
2345	else => unreachable, // TODO	2345	else => unreachable, // TODO
2346	}	2346	}
2347	}	2347	}
...	@@ -2352,7 +2352,7 @@ fn lowerToRvmiEnc(	...	@@ -2352,7 +2352,7 @@ fn lowerToRvmiEnc(
2352	});	2352	});
2353	encoder.vex(vex_prefix.prefix);	2353	encoder.vex(vex_prefix.prefix);
2354	opc.encode(encoder);	2354	opc.encode(encoder);
2355	encoder.modRm_direct(reg1.lowId(), reg3.lowId());	2355	encoder.modRm_direct(reg1.lowEnc(), reg3.lowEnc());
2356	break :blk encoder;	2356	break :blk encoder;
2357	},	2357	},
2358	.memory => \|dst_mem\| {	2358	.memory => \|dst_mem\| {
...	@@ -2490,23 +2490,23 @@ test "lower MI encoding" {	...	@@ -2490,23 +2490,23 @@ test "lower MI encoding" {
2490	test "lower RM encoding" {	2490	test "lower RM encoding" {
2491	var emit = TestEmit.init();	2491	var emit = TestEmit.init();
2492	defer emit.deinit();	2492	defer emit.deinit();
2493	try lowerToRmEnc(.mov, Register.reg(.rax), RegisterOrMemory.reg(.rbx), emit.code());	2493	try lowerToRmEnc(.mov, .rax, RegisterOrMemory.reg(.rbx), emit.code());
2494	try expectEqualHexStrings("\x48\x8b\xc3", emit.lowered(), "mov rax, rbx");	2494	try expectEqualHexStrings("\x48\x8b\xc3", emit.lowered(), "mov rax, rbx");
2495	try lowerToRmEnc(.mov, Register.reg(.rax), RegisterOrMemory.mem(.qword_ptr, .{ .disp = 0, .base = .r11 }), emit.code());	2495	try lowerToRmEnc(.mov, .rax, RegisterOrMemory.mem(.qword_ptr, .{ .disp = 0, .base = .r11 }), emit.code());
2496	try expectEqualHexStrings("\x49\x8b\x03", emit.lowered(), "mov rax, qword ptr [r11 + 0]");	2496	try expectEqualHexStrings("\x49\x8b\x03", emit.lowered(), "mov rax, qword ptr [r11 + 0]");
2497	try lowerToRmEnc(.add, Register.reg(.r11), RegisterOrMemory.mem(.qword_ptr, .{ .disp = 0x10000000 }), emit.code());	2497	try lowerToRmEnc(.add, .r11, RegisterOrMemory.mem(.qword_ptr, .{ .disp = 0x10000000 }), emit.code());
2498	try expectEqualHexStrings(	2498	try expectEqualHexStrings(
2499	"\x4C\x03\x1C\x25\x00\x00\x00\x10",	2499	"\x4C\x03\x1C\x25\x00\x00\x00\x10",
2500	emit.lowered(),	2500	emit.lowered(),
2501	"add r11, qword ptr [ds:0x10000000]",	2501	"add r11, qword ptr [ds:0x10000000]",
2502	);	2502	);
2503	try lowerToRmEnc(.add, Register.reg(.r12b), RegisterOrMemory.mem(.byte_ptr, .{ .disp = 0x10000000 }), emit.code());	2503	try lowerToRmEnc(.add, .r12b, RegisterOrMemory.mem(.byte_ptr, .{ .disp = 0x10000000 }), emit.code());
2504	try expectEqualHexStrings(	2504	try expectEqualHexStrings(
2505	"\x44\x02\x24\x25\x00\x00\x00\x10",	2505	"\x44\x02\x24\x25\x00\x00\x00\x10",
2506	emit.lowered(),	2506	emit.lowered(),
2507	"add r11b, byte ptr [ds:0x10000000]",	2507	"add r11b, byte ptr [ds:0x10000000]",
2508	);	2508	);
2509	try lowerToRmEnc(.sub, Register.reg(.r11), RegisterOrMemory.mem(.qword_ptr, .{	2509	try lowerToRmEnc(.sub, .r11, RegisterOrMemory.mem(.qword_ptr, .{
2510	.disp = 0x10000000,	2510	.disp = 0x10000000,
2511	.base = .r13,	2511	.base = .r13,
2512	}), emit.code());	2512	}), emit.code());
...	@@ -2515,7 +2515,7 @@ test "lower RM encoding" {	...	@@ -2515,7 +2515,7 @@ test "lower RM encoding" {
2515	emit.lowered(),	2515	emit.lowered(),
2516	"sub r11, qword ptr [r13 + 0x10000000]",	2516	"sub r11, qword ptr [r13 + 0x10000000]",
2517	);	2517	);
2518	try lowerToRmEnc(.sub, Register.reg(.r11), RegisterOrMemory.mem(.qword_ptr, .{	2518	try lowerToRmEnc(.sub, .r11, RegisterOrMemory.mem(.qword_ptr, .{
2519	.disp = 0x10000000,	2519	.disp = 0x10000000,
2520	.base = .r12,	2520	.base = .r12,
2521	}), emit.code());	2521	}), emit.code());
...	@@ -2524,14 +2524,14 @@ test "lower RM encoding" {	...	@@ -2524,14 +2524,14 @@ test "lower RM encoding" {
2524	emit.lowered(),	2524	emit.lowered(),
2525	"sub r11, qword ptr [r12 + 0x10000000]",	2525	"sub r11, qword ptr [r12 + 0x10000000]",
2526	);	2526	);
2527	try lowerToRmEnc(.mov, Register.reg(.rax), RegisterOrMemory.mem(.qword_ptr, .{	2527	try lowerToRmEnc(.mov, .rax, RegisterOrMemory.mem(.qword_ptr, .{
2528	.disp = @bitCast(u32, @as(i32, -4)),	2528	.disp = @bitCast(u32, @as(i32, -4)),
2529	.base = .rbp,	2529	.base = .rbp,
2530	}), emit.code());	2530	}), emit.code());
2531	try expectEqualHexStrings("\x48\x8B\x45\xFC", emit.lowered(), "mov rax, qword ptr [rbp - 4]");	2531	try expectEqualHexStrings("\x48\x8B\x45\xFC", emit.lowered(), "mov rax, qword ptr [rbp - 4]");
2532	try lowerToRmEnc(.lea, Register.reg(.rax), RegisterOrMemory.rip(.qword_ptr, 0x10), emit.code());	2532	try lowerToRmEnc(.lea, .rax, RegisterOrMemory.rip(.qword_ptr, 0x10), emit.code());
2533	try expectEqualHexStrings("\x48\x8D\x05\x10\x00\x00\x00", emit.lowered(), "lea rax, [rip + 0x10]");	2533	try expectEqualHexStrings("\x48\x8D\x05\x10\x00\x00\x00", emit.lowered(), "lea rax, [rip + 0x10]");
2534	try lowerToRmEnc(.mov, Register.reg(.rax), RegisterOrMemory.mem(.qword_ptr, .{	2534	try lowerToRmEnc(.mov, .rax, RegisterOrMemory.mem(.qword_ptr, .{
2535	.disp = @bitCast(u32, @as(i32, -8)),	2535	.disp = @bitCast(u32, @as(i32, -8)),
2536	.base = .rbp,	2536	.base = .rbp,
2537	.scale_index = .{	2537	.scale_index = .{
...	@@ -2540,7 +2540,7 @@ test "lower RM encoding" {	...	@@ -2540,7 +2540,7 @@ test "lower RM encoding" {
2540	},	2540	},
2541	}), emit.code());	2541	}), emit.code());
2542	try expectEqualHexStrings("\x48\x8B\x44\x0D\xF8", emit.lowered(), "mov rax, qword ptr [rbp + rcx*1 - 8]");	2542	try expectEqualHexStrings("\x48\x8B\x44\x0D\xF8", emit.lowered(), "mov rax, qword ptr [rbp + rcx*1 - 8]");
2543	try lowerToRmEnc(.mov, Register.reg(.eax), RegisterOrMemory.mem(.dword_ptr, .{	2543	try lowerToRmEnc(.mov, .eax, RegisterOrMemory.mem(.dword_ptr, .{
2544	.disp = @bitCast(u32, @as(i32, -4)),	2544	.disp = @bitCast(u32, @as(i32, -4)),
2545	.base = .rbp,	2545	.base = .rbp,
2546	.scale_index = .{	2546	.scale_index = .{
...	@@ -2549,7 +2549,7 @@ test "lower RM encoding" {	...	@@ -2549,7 +2549,7 @@ test "lower RM encoding" {
2549	},	2549	},
2550	}), emit.code());	2550	}), emit.code());
2551	try expectEqualHexStrings("\x8B\x44\x95\xFC", emit.lowered(), "mov eax, dword ptr [rbp + rdx*4 - 4]");	2551	try expectEqualHexStrings("\x8B\x44\x95\xFC", emit.lowered(), "mov eax, dword ptr [rbp + rdx*4 - 4]");
2552	try lowerToRmEnc(.mov, Register.reg(.rax), RegisterOrMemory.mem(.qword_ptr, .{	2552	try lowerToRmEnc(.mov, .rax, RegisterOrMemory.mem(.qword_ptr, .{
2553	.disp = @bitCast(u32, @as(i32, -8)),	2553	.disp = @bitCast(u32, @as(i32, -8)),
2554	.base = .rbp,	2554	.base = .rbp,
2555	.scale_index = .{	2555	.scale_index = .{
...	@@ -2558,7 +2558,7 @@ test "lower RM encoding" {	...	@@ -2558,7 +2558,7 @@ test "lower RM encoding" {
2558	},	2558	},
2559	}), emit.code());	2559	}), emit.code());
2560	try expectEqualHexStrings("\x48\x8B\x44\xCD\xF8", emit.lowered(), "mov rax, qword ptr [rbp + rcx*8 - 8]");	2560	try expectEqualHexStrings("\x48\x8B\x44\xCD\xF8", emit.lowered(), "mov rax, qword ptr [rbp + rcx*8 - 8]");
2561	try lowerToRmEnc(.mov, Register.reg(.r8b), RegisterOrMemory.mem(.byte_ptr, .{	2561	try lowerToRmEnc(.mov, .r8b, RegisterOrMemory.mem(.byte_ptr, .{
2562	.disp = @bitCast(u32, @as(i32, -24)),	2562	.disp = @bitCast(u32, @as(i32, -24)),
2563	.base = .rsi,	2563	.base = .rsi,
2564	.scale_index = .{	2564	.scale_index = .{
...	@@ -2567,7 +2567,7 @@ test "lower RM encoding" {	...	@@ -2567,7 +2567,7 @@ test "lower RM encoding" {
2567	},	2567	},
2568	}), emit.code());	2568	}), emit.code());
2569	try expectEqualHexStrings("\x44\x8A\x44\x0E\xE8", emit.lowered(), "mov r8b, byte ptr [rsi + rcx*1 - 24]");	2569	try expectEqualHexStrings("\x44\x8A\x44\x0E\xE8", emit.lowered(), "mov r8b, byte ptr [rsi + rcx*1 - 24]");
2570	try lowerToRmEnc(.lea, Register.reg(.rsi), RegisterOrMemory.mem(.qword_ptr, .{	2570	try lowerToRmEnc(.lea, .rsi, RegisterOrMemory.mem(.qword_ptr, .{
2571	.disp = 0,	2571	.disp = 0,
2572	.base = .rbp,	2572	.base = .rbp,
2573	.scale_index = .{	2573	.scale_index = .{
...	@@ -2576,33 +2576,25 @@ test "lower RM encoding" {	...	@@ -2576,33 +2576,25 @@ test "lower RM encoding" {
2576	},	2576	},
2577	}), emit.code());	2577	}), emit.code());
2578	try expectEqualHexStrings("\x48\x8D\x74\x0D\x00", emit.lowered(), "lea rsi, qword ptr [rbp + rcx*1 + 0]");	2578	try expectEqualHexStrings("\x48\x8D\x74\x0D\x00", emit.lowered(), "lea rsi, qword ptr [rbp + rcx*1 + 0]");
2579
2580	// AVX extension tests
2581	try lowerToRmEnc(.vmovsd, Register.avxReg(.xmm1), RegisterOrMemory.rip(.qword_ptr, 0x10), emit.code());
2582	try expectEqualHexStrings(
2583	"\xC5\xFB\x10\x0D\x10\x00\x00\x00",
2584	emit.lowered(),
2585	"vmovsd xmm1, qword ptr [rip + 0x10]",
2586	);
2587	}	2579	}
2588		2580
2589	test "lower MR encoding" {	2581	test "lower MR encoding" {
2590	var emit = TestEmit.init();	2582	var emit = TestEmit.init();
2591	defer emit.deinit();	2583	defer emit.deinit();
2592	try lowerToMrEnc(.mov, RegisterOrMemory.reg(.rax), Register.reg(.rbx), emit.code());	2584	try lowerToMrEnc(.mov, RegisterOrMemory.reg(.rax), .rbx, emit.code());
2593	try expectEqualHexStrings("\x48\x89\xd8", emit.lowered(), "mov rax, rbx");	2585	try expectEqualHexStrings("\x48\x89\xd8", emit.lowered(), "mov rax, rbx");
2594	try lowerToMrEnc(.mov, RegisterOrMemory.mem(.qword_ptr, .{	2586	try lowerToMrEnc(.mov, RegisterOrMemory.mem(.qword_ptr, .{
2595	.disp = @bitCast(u32, @as(i32, -4)),	2587	.disp = @bitCast(u32, @as(i32, -4)),
2596	.base = .rbp,	2588	.base = .rbp,
2597	}), Register.reg(.r11), emit.code());	2589	}), .r11, emit.code());
2598	try expectEqualHexStrings("\x4c\x89\x5d\xfc", emit.lowered(), "mov qword ptr [rbp - 4], r11");	2590	try expectEqualHexStrings("\x4c\x89\x5d\xfc", emit.lowered(), "mov qword ptr [rbp - 4], r11");
2599	try lowerToMrEnc(.add, RegisterOrMemory.mem(.byte_ptr, .{ .disp = 0x10000000 }), Register.reg(.r12b), emit.code());	2591	try lowerToMrEnc(.add, RegisterOrMemory.mem(.byte_ptr, .{ .disp = 0x10000000 }), .r12b, emit.code());
2600	try expectEqualHexStrings(	2592	try expectEqualHexStrings(
2601	"\x44\x00\x24\x25\x00\x00\x00\x10",	2593	"\x44\x00\x24\x25\x00\x00\x00\x10",
2602	emit.lowered(),	2594	emit.lowered(),
2603	"add byte ptr [ds:0x10000000], r12b",	2595	"add byte ptr [ds:0x10000000], r12b",
2604	);	2596	);
2605	try lowerToMrEnc(.add, RegisterOrMemory.mem(.dword_ptr, .{ .disp = 0x10000000 }), Register.reg(.r12d), emit.code());	2597	try lowerToMrEnc(.add, RegisterOrMemory.mem(.dword_ptr, .{ .disp = 0x10000000 }), .r12d, emit.code());
2606	try expectEqualHexStrings(	2598	try expectEqualHexStrings(
2607	"\x44\x01\x24\x25\x00\x00\x00\x10",	2599	"\x44\x01\x24\x25\x00\x00\x00\x10",
2608	emit.lowered(),	2600	emit.lowered(),
...	@@ -2611,61 +2603,53 @@ test "lower MR encoding" {	...	@@ -2611,61 +2603,53 @@ test "lower MR encoding" {
2611	try lowerToMrEnc(.sub, RegisterOrMemory.mem(.qword_ptr, .{	2603	try lowerToMrEnc(.sub, RegisterOrMemory.mem(.qword_ptr, .{
2612	.disp = 0x10000000,	2604	.disp = 0x10000000,
2613	.base = .r11,	2605	.base = .r11,
2614	}), Register.reg(.r12), emit.code());	2606	}), .r12, emit.code());
2615	try expectEqualHexStrings(	2607	try expectEqualHexStrings(
2616	"\x4D\x29\xA3\x00\x00\x00\x10",	2608	"\x4D\x29\xA3\x00\x00\x00\x10",
2617	emit.lowered(),	2609	emit.lowered(),
2618	"sub qword ptr [r11 + 0x10000000], r12",	2610	"sub qword ptr [r11 + 0x10000000], r12",
2619	);	2611	);
2620	try lowerToMrEnc(.mov, RegisterOrMemory.rip(.qword_ptr, 0x10), Register.reg(.r12), emit.code());	2612	try lowerToMrEnc(.mov, RegisterOrMemory.rip(.qword_ptr, 0x10), .r12, emit.code());
2621	try expectEqualHexStrings("\x4C\x89\x25\x10\x00\x00\x00", emit.lowered(), "mov qword ptr [rip + 0x10], r12");	2613	try expectEqualHexStrings("\x4C\x89\x25\x10\x00\x00\x00", emit.lowered(), "mov qword ptr [rip + 0x10], r12");
2622
2623	// AVX extension tests
2624	try lowerToMrEnc(.vmovsd, RegisterOrMemory.rip(.qword_ptr, 0x10), Register.avxReg(.xmm1), emit.code());
2625	try expectEqualHexStrings(
2626	"\xC5\xFB\x11\x0D\x10\x00\x00\x00",
2627	emit.lowered(),
2628	"vmovsd qword ptr [rip + 0x10], xmm1",
2629	);
2630	}	2614	}
2631		2615
2632	test "lower OI encoding" {	2616	test "lower OI encoding" {
2633	var emit = TestEmit.init();	2617	var emit = TestEmit.init();
2634	defer emit.deinit();	2618	defer emit.deinit();
2635	try lowerToOiEnc(.mov, Register.reg(.rax), 0x1000000000000000, emit.code());	2619	try lowerToOiEnc(.mov, .rax, 0x1000000000000000, emit.code());
2636	try expectEqualHexStrings(	2620	try expectEqualHexStrings(
2637	"\x48\xB8\x00\x00\x00\x00\x00\x00\x00\x10",	2621	"\x48\xB8\x00\x00\x00\x00\x00\x00\x00\x10",
2638	emit.lowered(),	2622	emit.lowered(),
2639	"movabs rax, 0x1000000000000000",	2623	"movabs rax, 0x1000000000000000",
2640	);	2624	);
2641	try lowerToOiEnc(.mov, Register.reg(.r11), 0x1000000000000000, emit.code());	2625	try lowerToOiEnc(.mov, .r11, 0x1000000000000000, emit.code());
2642	try expectEqualHexStrings(	2626	try expectEqualHexStrings(
2643	"\x49\xBB\x00\x00\x00\x00\x00\x00\x00\x10",	2627	"\x49\xBB\x00\x00\x00\x00\x00\x00\x00\x10",
2644	emit.lowered(),	2628	emit.lowered(),
2645	"movabs r11, 0x1000000000000000",	2629	"movabs r11, 0x1000000000000000",
2646	);	2630	);
2647	try lowerToOiEnc(.mov, Register.reg(.r11d), 0x10000000, emit.code());	2631	try lowerToOiEnc(.mov, .r11d, 0x10000000, emit.code());
2648	try expectEqualHexStrings("\x41\xBB\x00\x00\x00\x10", emit.lowered(), "mov r11d, 0x10000000");	2632	try expectEqualHexStrings("\x41\xBB\x00\x00\x00\x10", emit.lowered(), "mov r11d, 0x10000000");
2649	try lowerToOiEnc(.mov, Register.reg(.r11w), 0x1000, emit.code());	2633	try lowerToOiEnc(.mov, .r11w, 0x1000, emit.code());
2650	try expectEqualHexStrings("\x66\x41\xBB\x00\x10", emit.lowered(), "mov r11w, 0x1000");	2634	try expectEqualHexStrings("\x66\x41\xBB\x00\x10", emit.lowered(), "mov r11w, 0x1000");
2651	try lowerToOiEnc(.mov, Register.reg(.r11b), 0x10, emit.code());	2635	try lowerToOiEnc(.mov, .r11b, 0x10, emit.code());
2652	try expectEqualHexStrings("\x41\xB3\x10", emit.lowered(), "mov r11b, 0x10");	2636	try expectEqualHexStrings("\x41\xB3\x10", emit.lowered(), "mov r11b, 0x10");
2653	}	2637	}
2654		2638
2655	test "lower FD/TD encoding" {	2639	test "lower FD/TD encoding" {
2656	var emit = TestEmit.init();	2640	var emit = TestEmit.init();
2657	defer emit.deinit();	2641	defer emit.deinit();
2658	try lowerToFdEnc(.mov, Register.reg(.rax), 0x1000000000000000, emit.code());	2642	try lowerToFdEnc(.mov, .rax, 0x1000000000000000, emit.code());
2659	try expectEqualHexStrings(	2643	try expectEqualHexStrings(
2660	"\x48\xa1\x00\x00\x00\x00\x00\x00\x00\x10",	2644	"\x48\xa1\x00\x00\x00\x00\x00\x00\x00\x10",
2661	emit.lowered(),	2645	emit.lowered(),
2662	"mov rax, ds:0x1000000000000000",	2646	"mov rax, ds:0x1000000000000000",
2663	);	2647	);
2664	try lowerToFdEnc(.mov, Register.reg(.eax), 0x10000000, emit.code());	2648	try lowerToFdEnc(.mov, .eax, 0x10000000, emit.code());
2665	try expectEqualHexStrings("\xa1\x00\x00\x00\x10", emit.lowered(), "mov eax, ds:0x10000000");	2649	try expectEqualHexStrings("\xa1\x00\x00\x00\x10", emit.lowered(), "mov eax, ds:0x10000000");
2666	try lowerToFdEnc(.mov, Register.reg(.ax), 0x1000, emit.code());	2650	try lowerToFdEnc(.mov, .ax, 0x1000, emit.code());
2667	try expectEqualHexStrings("\x66\xa1\x00\x10", emit.lowered(), "mov ax, ds:0x1000");	2651	try expectEqualHexStrings("\x66\xa1\x00\x10", emit.lowered(), "mov ax, ds:0x1000");
2668	try lowerToFdEnc(.mov, Register.reg(.al), 0x10, emit.code());	2652	try lowerToFdEnc(.mov, .al, 0x10, emit.code());
2669	try expectEqualHexStrings("\xa0\x10", emit.lowered(), "mov al, ds:0x10");	2653	try expectEqualHexStrings("\xa0\x10", emit.lowered(), "mov al, ds:0x10");
2670	}	2654	}
2671		2655
...	@@ -2741,16 +2725,16 @@ test "lower M1 and MC encodings" {	...	@@ -2741,16 +2725,16 @@ test "lower M1 and MC encodings" {
2741	test "lower O encoding" {	2725	test "lower O encoding" {
2742	var emit = TestEmit.init();	2726	var emit = TestEmit.init();
2743	defer emit.deinit();	2727	defer emit.deinit();
2744	try lowerToOEnc(.pop, Register.reg(.r12), emit.code());	2728	try lowerToOEnc(.pop, .r12, emit.code());
2745	try expectEqualHexStrings("\x41\x5c", emit.lowered(), "pop r12");	2729	try expectEqualHexStrings("\x41\x5c", emit.lowered(), "pop r12");
2746	try lowerToOEnc(.push, Register.reg(.r12w), emit.code());	2730	try lowerToOEnc(.push, .r12w, emit.code());
2747	try expectEqualHexStrings("\x66\x41\x54", emit.lowered(), "push r12w");	2731	try expectEqualHexStrings("\x66\x41\x54", emit.lowered(), "push r12w");
2748	}	2732	}
2749		2733
2750	test "lower RMI encoding" {	2734	test "lower RMI encoding" {
2751	var emit = TestEmit.init();	2735	var emit = TestEmit.init();
2752	defer emit.deinit();	2736	defer emit.deinit();
2753	try lowerToRmiEnc(.imul, Register.reg(.rax), RegisterOrMemory.mem(.qword_ptr, .{	2737	try lowerToRmiEnc(.imul, .rax, RegisterOrMemory.mem(.qword_ptr, .{
2754	.disp = @bitCast(u32, @as(i32, -8)),	2738	.disp = @bitCast(u32, @as(i32, -8)),
2755	.base = .rbp,	2739	.base = .rbp,
2756	}), 0x10, emit.code());	2740	}), 0x10, emit.code());
...	@@ -2759,39 +2743,49 @@ test "lower RMI encoding" {	...	@@ -2759,39 +2743,49 @@ test "lower RMI encoding" {
2759	emit.lowered(),	2743	emit.lowered(),
2760	"imul rax, qword ptr [rbp - 8], 0x10",	2744	"imul rax, qword ptr [rbp - 8], 0x10",
2761	);	2745	);
2762	try lowerToRmiEnc(.imul, Register.reg(.eax), RegisterOrMemory.mem(.dword_ptr, .{	2746	try lowerToRmiEnc(.imul, .eax, RegisterOrMemory.mem(.dword_ptr, .{
2763	.disp = @bitCast(u32, @as(i32, -4)),	2747	.disp = @bitCast(u32, @as(i32, -4)),
2764	.base = .rbp,	2748	.base = .rbp,
2765	}), 0x10, emit.code());	2749	}), 0x10, emit.code());
2766	try expectEqualHexStrings("\x69\x45\xFC\x10\x00\x00\x00", emit.lowered(), "imul eax, dword ptr [rbp - 4], 0x10");	2750	try expectEqualHexStrings("\x69\x45\xFC\x10\x00\x00\x00", emit.lowered(), "imul eax, dword ptr [rbp - 4], 0x10");
2767	try lowerToRmiEnc(.imul, Register.reg(.ax), RegisterOrMemory.mem(.word_ptr, .{	2751	try lowerToRmiEnc(.imul, .ax, RegisterOrMemory.mem(.word_ptr, .{
2768	.disp = @bitCast(u32, @as(i32, -2)),	2752	.disp = @bitCast(u32, @as(i32, -2)),
2769	.base = .rbp,	2753	.base = .rbp,
2770	}), 0x10, emit.code());	2754	}), 0x10, emit.code());
2771	try expectEqualHexStrings("\x66\x69\x45\xFE\x10\x00", emit.lowered(), "imul ax, word ptr [rbp - 2], 0x10");	2755	try expectEqualHexStrings("\x66\x69\x45\xFE\x10\x00", emit.lowered(), "imul ax, word ptr [rbp - 2], 0x10");
2772	try lowerToRmiEnc(.imul, Register.reg(.r12), RegisterOrMemory.reg(.r12), 0x10, emit.code());	2756	try lowerToRmiEnc(.imul, .r12, RegisterOrMemory.reg(.r12), 0x10, emit.code());
2773	try expectEqualHexStrings("\x4D\x69\xE4\x10\x00\x00\x00", emit.lowered(), "imul r12, r12, 0x10");	2757	try expectEqualHexStrings("\x4D\x69\xE4\x10\x00\x00\x00", emit.lowered(), "imul r12, r12, 0x10");
2774	try lowerToRmiEnc(.imul, Register.reg(.r12w), RegisterOrMemory.reg(.r12w), 0x10, emit.code());	2758	try lowerToRmiEnc(.imul, .r12w, RegisterOrMemory.reg(.r12w), 0x10, emit.code());
2775	try expectEqualHexStrings("\x66\x45\x69\xE4\x10\x00", emit.lowered(), "imul r12w, r12w, 0x10");	2759	try expectEqualHexStrings("\x66\x45\x69\xE4\x10\x00", emit.lowered(), "imul r12w, r12w, 0x10");
2776	}	2760	}
2777		2761
2778	test "lower to RVM encoding" {	2762	test "lower MV encoding" {
2779	var emit = TestEmit.init();	2763	var emit = TestEmit.init();
2780	defer emit.deinit();	2764	defer emit.deinit();
2781	try lowerToRvmEnc(	2765	try lowerToMvEnc(.vmovsd, RegisterOrMemory.rip(.qword_ptr, 0x10), .xmm1, emit.code());
2782	.vaddsd,	2766	try expectEqualHexStrings(
2783	Register.avxReg(.xmm0),	2767	"\xC5\xFB\x11\x0D\x10\x00\x00\x00",
2784	Register.avxReg(.xmm1),	2768	emit.lowered(),
2785	RegisterOrMemory.avxReg(.xmm2),	2769	"vmovsd qword ptr [rip + 0x10], xmm1",
2786	emit.code(),
2787	);	2770	);
2788	try expectEqualHexStrings("\xC5\xF3\x58\xC2", emit.lowered(), "vaddsd xmm0, xmm1, xmm2");	2771	}
2789	try lowerToRvmEnc(	2772
2790	.vaddsd,	2773	test "lower VM encoding" {
2791	Register.avxReg(.xmm0),	2774	var emit = TestEmit.init();
2792	Register.avxReg(.xmm0),	2775	defer emit.deinit();
2793	RegisterOrMemory.avxReg(.xmm1),	2776	try lowerToVmEnc(.vmovsd, .xmm1, RegisterOrMemory.rip(.qword_ptr, 0x10), emit.code());
2794	emit.code(),	2777	try expectEqualHexStrings(
		2778	"\xC5\xFB\x10\x0D\x10\x00\x00\x00",
		2779	emit.lowered(),
		2780	"vmovsd xmm1, qword ptr [rip + 0x10]",
2795	);	2781	);
		2782	}
		2783
		2784	test "lower to RVM encoding" {
		2785	var emit = TestEmit.init();
		2786	defer emit.deinit();
		2787	try lowerToRvmEnc(.vaddsd, .xmm0, .xmm1, RegisterOrMemory.reg(.xmm2), emit.code());
		2788	try expectEqualHexStrings("\xC5\xF3\x58\xC2", emit.lowered(), "vaddsd xmm0, xmm1, xmm2");
		2789	try lowerToRvmEnc(.vaddsd, .xmm0, .xmm0, RegisterOrMemory.reg(.xmm1), emit.code());
2796	try expectEqualHexStrings("\xC5\xFB\x58\xC1", emit.lowered(), "vaddsd xmm0, xmm0, xmm1");	2790	try expectEqualHexStrings("\xC5\xFB\x58\xC1", emit.lowered(), "vaddsd xmm0, xmm0, xmm1");
2797	}	2791	}

src/arch/x86_64/Mir.zig+32-34

 @@ -14,8 +14,7 @@ const assert = std.debug.assert;
 const bits = @import("bits.zig");
 const Air = @import("../../Air.zig");
 const CodeGen = @import("CodeGen.zig");
-const GpRegister = bits.Register;
+const Register = bits.Register;
-const AvxRegister = bits.AvxRegister;
 instructions: std.MultiArrayList(Inst).Slice,
 /// The meaning of this data is determined by `Inst.Tag` value.
 @@ -23,11 +22,7 @@ extra: []const u32,
 pub const Inst = struct {
     tag: Tag,
-    /// This is 3 fields, and the meaning of each depends on `tag`.
+    ops: Ops,
-    /// reg1: Register
-    /// reg2: Register
-    /// flags: u2
-    ops: u16,
     /// The meaning of this depends on `tag` and `ops`.
     data: Data,
 @@ -397,6 +392,36 @@ pub const Inst = struct {
     /// The position of an MIR instruction within the `Mir` instructions array.
     pub const Index = u32;
+    pub const Ops = packed struct {
+        reg1: u7,
+        reg2: u7,
+        flags: u2,
+        pub fn encode(vals: struct {
+            reg1: Register = .none,
+            reg2: Register = .none,
+            flags: u2 = 0b00,
+        }) Ops {
+            return .{
+                .reg1 = @enumToInt(vals.reg1),
+                .reg2 = @enumToInt(vals.reg2),
+                .flags = vals.flags,
+            };
+        }
+        pub fn decode(ops: Ops) struct {
+            reg1: Register,
+            reg2: Register,
+            flags: u2,
+        } {
+            return .{
+                .reg1 = @intToEnum(Register, ops.reg1),
+                .reg2 = @intToEnum(Register, ops.reg2),
+                .flags = ops.flags,
+            };
+        }
+    };
     /// All instructions have a 4-byte payload, which is contained within
     /// this union. `Tag` determines which union field is active, as well as
     /// how to interpret the data within.
 @@ -466,33 +491,6 @@ pub const DbgLineColumn = struct {
     column: u32,
 };
-pub fn Ops(comptime Reg1: type, comptime Reg2: type) type {
-    return struct {
-        reg1: Reg1 = .none,
-        reg2: Reg2 = .none,
-        flags: u2 = 0b00,
-        pub fn encode(self: @This()) u16 {
-            var ops: u16 = 0;
-            ops |= @intCast(u16, @enumToInt(self.reg1)) << 9;
-            ops |= @intCast(u16, @enumToInt(self.reg2)) << 2;
-            ops |= self.flags;
-            return ops;
-        }
-        pub fn decode(ops: u16) @This() {
-            const reg1 = @intToEnum(Reg1, @truncate(u7, ops >> 9));
-            const reg2 = @intToEnum(Reg2, @truncate(u7, ops >> 2));
-            const flags = @truncate(u2, ops);
-            return .{
-                .reg1 = reg1,
-                .reg2 = reg2,
-                .flags = flags,
-            };
-        }
-    };
-}
 pub fn deinit(mir: *Mir, gpa: std.mem.Allocator) void {
     mir.instructions.deinit(gpa);
     gpa.free(mir.extra);

src/arch/x86_64/abi.zig+11-6

 @@ -3,7 +3,6 @@ const Type = @import("../../type.zig").Type;
 const Target = std.Target;
 const assert = std.debug.assert;
 const Register = @import("bits.zig").Register;
-const AvxRegister = @import("bits.zig").AvxRegister;
 pub const Class = enum { integer, sse, sseup, x87, x87up, complex_x87, memory, none };
 @@ -379,11 +378,17 @@ pub const callee_preserved_regs = [_]Register{ .rbx, .r12, .r13, .r14, .r15 };
 /// the caller relinquishes control to a subroutine via call instruction (or similar).
 /// In other words, these registers are free to use by the callee.
 pub const caller_preserved_regs = [_]Register{ .rax, .rcx, .rdx, .rsi, .rdi, .r8, .r9, .r10, .r11 };
-pub const allocatable_registers = callee_preserved_regs ++ caller_preserved_regs;
+pub const avx_regs = [_]Register{
-pub const c_abi_int_param_regs = [_]Register{ .rdi, .rsi, .rdx, .rcx, .r8, .r9 };
-pub const c_abi_int_return_regs = [_]Register{ .rax, .rdx };
-pub const avx_regs = [_]AvxRegister{
     .ymm0, .ymm1, .ymm2,  .ymm3,  .ymm4,  .ymm5,  .ymm6,  .ymm7,
     .ymm8, .ymm9, .ymm10, .ymm11, .ymm12, .ymm13, .ymm14, .ymm15,
 };
+pub const allocatable_registers = callee_preserved_regs ++ caller_preserved_regs ++ avx_regs;
+// Masks for register manager
+const FreeRegInt = std.meta.Int(.unsigned, allocatable_registers.len);
+// TODO
+pub const gp_mask: FreeRegInt = 0x3fff;
+pub const avx_mask: FreeRegInt = 0x3fff_c000;
+pub const c_abi_int_param_regs = [_]Register{ .rdi, .rsi, .rdx, .rcx, .r8, .r9 };
+pub const c_abi_int_return_regs = [_]Register{ .rax, .rdx };

src/arch/x86_64/bits.zig+38-62

 @@ -43,17 +43,36 @@ pub const Register = enum(u7) {
     al, cl, dl, bl, ah, ch, dh, bh,
     r8b, r9b, r10b, r11b, r12b, r13b, r14b, r15b,
-    // Pseudo, used only for MIR to signify that the
+    // 64-79, 256-bit registers.
-    // operand is not a register but an immediate, etc.
+    // id is int value - 64.
+    ymm0, ymm1, ymm2,  ymm3,  ymm4,  ymm5,  ymm6,  ymm7,
+    ymm8, ymm9, ymm10, ymm11, ymm12, ymm13, ymm14, ymm15,
+    // 80-95, 128-bit registers.
+    // id is int value - 80.
+    xmm0, xmm1, xmm2,  xmm3,  xmm4,  xmm5,  xmm6,  xmm7,
+    xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15,
+    // Pseudo-value for MIR instructions.
     none,
+    pub fn id(self: Register) u5 {
+        return switch (@enumToInt(self)) {
+            0...63 => @as(u5, @truncate(u4, @enumToInt(self))),
+            64...79 => @truncate(u5, @enumToInt(self)),
+            else => unreachable,
+        };
+    }
     /// Returns the bit-width of the register.
-    pub fn size(self: Register) u7 {
+    pub fn size(self: Register) u9 {
         return switch (@enumToInt(self)) {
             0...15 => 64,
             16...31 => 32,
             32...47 => 16,
-            48...64 => 8,
+            48...63 => 8,
+            64...79 => 256,
+            80...95 => 128,
             else => unreachable,
         };
     }
 @@ -72,15 +91,23 @@ pub const Register = enum(u7) {
     /// an instruction (@see isExtended), and requires special handling. The
     /// lower three bits are often embedded directly in instructions (such as
     /// the B8 variant of moves), or used in R/M bytes.
-    pub fn id(self: Register) u4 {
+    pub fn enc(self: Register) u4 {
         return @truncate(u4, @enumToInt(self));
     }
-    /// Like id, but only returns the lower 3 bits.
+    /// Like enc, but only returns the lower 3 bits.
-    pub fn lowId(self: Register) u3 {
+    pub fn lowEnc(self: Register) u3 {
         return @truncate(u3, @enumToInt(self));
     }
+    pub fn to256(self: Register) Register {
+        return @intToEnum(Register, @as(u8, self.id()) + 64);
+    }
+    pub fn to128(self: Register) Register {
+        return @intToEnum(Register, @as(u8, self.id()) + 80);
+    }
     /// Convert from any register to its 64 bit alias.
     pub fn to64(self: Register) Register {
         return @intToEnum(Register, self.id());
 @@ -126,57 +153,6 @@ pub const Register = enum(u7) {
     }
 };
-/// AVX registers.
-/// TODO missing dwarfLocOp implementation.
-/// TODO add support for AVX-512
-pub const AvxRegister = enum(u6) {
-    // 256-bit registers
-    ymm0, ymm1, ymm2,  ymm3,  ymm4,  ymm5,  ymm6,  ymm7,
-    ymm8, ymm9, ymm10, ymm11, ymm12, ymm13, ymm14, ymm15,
-    // 128-bit registers
-    xmm0, xmm1, xmm2,  xmm3,  xmm4,  xmm5,  xmm6,  xmm7,
-    xmm8, xmm9, xmm10, xmm11, xmm12, xmm13, xmm14, xmm15,
-    // Pseudo, used only for MIR to signify that the
-    // operand is not a register but an immediate, etc.
-    none,
-    /// Returns the bit-width of the register.
-    pub fn size(self: AvxRegister) u9 {
-        return switch (@enumToInt(self)) {
-            0...15 => 256,
-            16...31 => 128,
-            else => unreachable,
-        };
-    }
-    /// Returns whether the register is *extended*.
-    pub fn isExtended(self: AvxRegister) bool {
-        return @enumToInt(self) & 0x08 != 0;
-    }
-    /// This returns the 4-bit register ID.
-    pub fn id(self: AvxRegister) u4 {
-        return @truncate(u4, @enumToInt(self));
-    }
-    /// Like id, but only returns the lower 3 bits.
-    pub fn lowId(self: AvxRegister) u3 {
-        return @truncate(u3, @enumToInt(self));
-    }
-    /// Convert from any register to its 256 bit alias.
-    pub fn to256(self: AvxRegister) AvxRegister {
-        return @intToEnum(AvxRegister, self.id());
-    }
-    /// Convert from any register to its 128 bit alias.
-    pub fn to128(self: AvxRegister) AvxRegister {
-        return @intToEnum(AvxRegister, @as(u8, self.id()) + 16);
-    }
-};
 // zig fmt: on
 /// Encoding helper functions for x86_64 instructions
 @@ -792,7 +768,7 @@ test "Encoder helpers - Vex prefix" {
     {
         stream.reset();
         var vex_prefix = Encoder.Vex{};
-        vex_prefix.reg(AvxRegister.xmm15.id());
+        vex_prefix.reg(Register.xmm15.id());
         const nwritten = vex_prefix.write(writer);
         try testing.expectEqualSlices(u8, &[_]u8{ 0xc5, 0x80 }, buf[0..nwritten]);
     }
 @@ -832,7 +808,7 @@ test "Encoder helpers - Vex prefix" {
         vex.simd_prefix_66();
         encoder.vex(vex); // use 64 bit operation
         encoder.opcode_1byte(0x28);
-        encoder.modRm_direct(0, AvxRegister.xmm1.lowId());
+        encoder.modRm_direct(0, Register.xmm1.lowId());
         try testing.expectEqualSlices(u8, &[_]u8{ 0xC5, 0xF9, 0x28, 0xC1 }, code.items);
     }
 @@ -846,10 +822,10 @@ test "Encoder helpers - Vex prefix" {
         vex.simd_prefix_66();
         vex.lead_opc_0f();
         vex.rex(.{ .r = true });
-        vex.reg(AvxRegister.xmm1.id());
+        vex.reg(Register.xmm1.id());
         encoder.vex(vex);
         encoder.opcode_1byte(0x16);
-        encoder.modRm_RIPDisp32(AvxRegister.xmm13.lowId());
+        encoder.modRm_RIPDisp32(Register.xmm13.lowId());
         encoder.disp32(0);
         try testing.expectEqualSlices(u8, &[_]u8{ 0xC5, 0x71, 0x16, 0x2D, 0x00, 0x00, 0x00, 0x00 }, code.items);
     }

src/codegen.zig+12-12

src/register_manager.zig+255-261

...	@@ -23,15 +23,10 @@ pub const AllocateRegistersError = error{	...	@@ -23,15 +23,10 @@ pub const AllocateRegistersError = error{
23	CodegenFail,	23	CodegenFail,
24	};	24	};
25		25
26	pub fn SpillFn(comptime Function: type, comptime Register: type) type {
27	return fn (*Function, Register, Air.Inst.Index) anyerror!void;
28	}
29
30	pub fn RegisterManager(	26	pub fn RegisterManager(
31	comptime Function: type,	27	comptime Function: type,
32	comptime Register: type,	28	comptime Register: type,
33	comptime tracked_registers: []const Register,	29	comptime tracked_registers: []const Register,
34	comptime spill_fn: SpillFn(Function, Register),
35	) type {	30	) type {
36	// architectures which do not have a concept of registers should	31	// architectures which do not have a concept of registers should
37	// refrain from using RegisterManager	32	// refrain from using RegisterManager
...	@@ -52,7 +47,6 @@ pub fn RegisterManager(	...	@@ -52,7 +47,6 @@ pub fn RegisterManager(
52	allocated_registers: FreeRegInt = 0,	47	allocated_registers: FreeRegInt = 0,
53	/// Tracks registers which are locked from being allocated	48	/// Tracks registers which are locked from being allocated
54	locked_registers: FreeRegInt = 0,	49	locked_registers: FreeRegInt = 0,
55	function: *Function,
56		50
57	const Self = @This();	51	const Self = @This();
58		52
...	@@ -61,8 +55,8 @@ pub fn RegisterManager(	...	@@ -61,8 +55,8 @@ pub fn RegisterManager(
61	const FreeRegInt = std.meta.Int(.unsigned, tracked_registers.len);	55	const FreeRegInt = std.meta.Int(.unsigned, tracked_registers.len);
62	const ShiftInt = math.Log2Int(FreeRegInt);	56	const ShiftInt = math.Log2Int(FreeRegInt);
63		57
64	fn spillInstruction(self: *Self, reg: Register, inst: Air.Inst.Index) AllocateRegistersError!void {	58	fn getFunction(self: Self) Function {
65	return try spill_fn(self.function, reg, inst);	59	return @fieldParentPtr(Function, "register_manager", self);
66	}	60	}
67		61
68	fn getRegisterMask(reg: Register) ?FreeRegInt {	62	fn getRegisterMask(reg: Register) ?FreeRegInt {
...	@@ -257,14 +251,14 @@ pub fn RegisterManager(	...	@@ -257,14 +251,14 @@ pub fn RegisterManager(
257	self.markRegUsed(reg);	251	self.markRegUsed(reg);
258	} else {	252	} else {
259	const spilled_inst = self.registers[index];	253	const spilled_inst = self.registers[index];
260	try self.spillInstruction(reg, spilled_inst);	254	try self.getFunction().spillInstruction(reg, spilled_inst);
261	}	255	}
262	self.registers[index] = inst;	256	self.registers[index] = inst;
263	} else {	257	} else {
264	// Don't track the register	258	// Don't track the register
265	if (!self.isRegFree(reg)) {	259	if (!self.isRegFree(reg)) {
266	const spilled_inst = self.registers[index];	260	const spilled_inst = self.registers[index];
267	try self.spillInstruction(reg, spilled_inst);	261	try self.getFunction().spillInstruction(reg, spilled_inst);
268	self.freeReg(reg);	262	self.freeReg(reg);
269	}	263	}
270	}	264	}
...	@@ -299,7 +293,7 @@ pub fn RegisterManager(	...	@@ -299,7 +293,7 @@ pub fn RegisterManager(
299	// stack allocation.	293	// stack allocation.
300	const spilled_inst = self.registers[index];	294	const spilled_inst = self.registers[index];
301	self.registers[index] = tracked_inst;	295	self.registers[index] = tracked_inst;
302	try self.spillInstruction(reg, spilled_inst);	296	try self.getFunction().spillInstruction(reg, spilled_inst);
303	} else {	297	} else {
304	self.getRegAssumeFree(reg, tracked_inst);	298	self.getRegAssumeFree(reg, tracked_inst);
305	}	299	}
...	@@ -308,7 +302,7 @@ pub fn RegisterManager(	...	@@ -308,7 +302,7 @@ pub fn RegisterManager(
308	// Move the instruction that was previously there to a	302	// Move the instruction that was previously there to a
309	// stack allocation.	303	// stack allocation.
310	const spilled_inst = self.registers[index];	304	const spilled_inst = self.registers[index];
311	try self.spillInstruction(reg, spilled_inst);	305	try self.getFunction().spillInstruction(reg, spilled_inst);
312	self.freeReg(reg);	306	self.freeReg(reg);
313	}	307	}
314	}	308	}
...	@@ -338,253 +332,253 @@ pub fn RegisterManager(	...	@@ -338,253 +332,253 @@ pub fn RegisterManager(
338	};	332	};
339	}	333	}
340		334
341	//const MockRegister1 = enum(u2) {	335	const MockRegister1 = enum(u2) {
342	// r0,	336	r0,
343	// r1,	337	r1,
344	// r2,	338	r2,
345	// r3,	339	r3,
346		340
347	// pub fn id(reg: MockRegister1) u2 {	341	pub fn id(reg: MockRegister1) u2 {
348	// return @enumToInt(reg);	342	return @enumToInt(reg);
349	// }	343	}
		344
		345	const allocatable_registers = [_]MockRegister1{ .r2, .r3 };
		346	};
		347
		348	const MockRegister2 = enum(u2) {
		349	r0,
		350	r1,
		351	r2,
		352	r3,
		353
		354	pub fn id(reg: MockRegister2) u2 {
		355	return @enumToInt(reg);
		356	}
		357
		358	const allocatable_registers = [_]MockRegister2{ .r0, .r1, .r2, .r3 };
		359	};
		360
		361	fn MockFunction(comptime Register: type) type {
		362	return struct {
		363	allocator: Allocator,
		364	register_manager: RegisterManager(Self, Register, &Register.allocatable_registers) = .{},
		365	spilled: std.ArrayListUnmanaged(Register) = .{},
		366
		367	const Self = @This();
		368
		369	pub fn deinit(self: *Self) void {
		370	self.spilled.deinit(self.allocator);
		371	}
		372
		373	pub fn spillInstruction(self: *Self, reg: Register, inst: Air.Inst.Index) !void {
		374	_ = inst;
		375	try self.spilled.append(self.allocator, reg);
		376	}
		377
		378	pub fn genAdd(self: *Self, res: Register, lhs: Register, rhs: Register) !void {
		379	_ = self;
		380	_ = res;
		381	_ = lhs;
		382	_ = rhs;
		383	}
		384	};
		385	}
		386
		387	const MockFunction1 = MockFunction(MockRegister1);
		388	const MockFunction2 = MockFunction(MockRegister2);
		389
		390	test "default state" {
		391	const allocator = std.testing.allocator;
		392
		393	var function = MockFunction1{
		394	.allocator = allocator,
		395	};
		396	defer function.deinit();
		397
		398	try expect(!function.register_manager.isRegAllocated(.r2));
		399	try expect(!function.register_manager.isRegAllocated(.r3));
		400	try expect(function.register_manager.isRegFree(.r2));
		401	try expect(function.register_manager.isRegFree(.r3));
		402	}
		403
		404	test "tryAllocReg: no spilling" {
		405	const allocator = std.testing.allocator;
		406
		407	var function = MockFunction1{
		408	.allocator = allocator,
		409	};
		410	defer function.deinit();
		411
		412	const mock_instruction: Air.Inst.Index = 1;
		413
		414	try expectEqual(@as(?MockRegister1, .r2), function.register_manager.tryAllocReg(mock_instruction));
		415	try expectEqual(@as(?MockRegister1, .r3), function.register_manager.tryAllocReg(mock_instruction));
		416	try expectEqual(@as(?MockRegister1, null), function.register_manager.tryAllocReg(mock_instruction));
		417
		418	try expect(function.register_manager.isRegAllocated(.r2));
		419	try expect(function.register_manager.isRegAllocated(.r3));
		420	try expect(!function.register_manager.isRegFree(.r2));
		421	try expect(!function.register_manager.isRegFree(.r3));
		422
		423	function.register_manager.freeReg(.r2);
		424	function.register_manager.freeReg(.r3);
		425
		426	try expect(function.register_manager.isRegAllocated(.r2));
		427	try expect(function.register_manager.isRegAllocated(.r3));
		428	try expect(function.register_manager.isRegFree(.r2));
		429	try expect(function.register_manager.isRegFree(.r3));
		430	}
		431
		432	test "allocReg: spilling" {
		433	const allocator = std.testing.allocator;
350		434
351	// const allocatable_registers = [_]MockRegister1{ .r2, .r3 };	435	var function = MockFunction1{
352	//};	436	.allocator = allocator,
353		437	};
354	//const MockRegister2 = enum(u2) {	438	defer function.deinit();
355	// r0,	439
356	// r1,	440	const mock_instruction: Air.Inst.Index = 1;
357	// r2,	441
358	// r3,	442	try expectEqual(@as(?MockRegister1, .r2), try function.register_manager.allocReg(mock_instruction));
359		443	try expectEqual(@as(?MockRegister1, .r3), try function.register_manager.allocReg(mock_instruction));
360	// pub fn id(reg: MockRegister2) u2 {	444
361	// return @enumToInt(reg);	445	// Spill a register
362	// }	446	try expectEqual(@as(?MockRegister1, .r2), try function.register_manager.allocReg(mock_instruction));
363		447	try expectEqualSlices(MockRegister1, &[_]MockRegister1{.r2}, function.spilled.items);
364	// const allocatable_registers = [_]MockRegister2{ .r0, .r1, .r2, .r3 };	448
365	//};	449	// No spilling necessary
366		450	function.register_manager.freeReg(.r3);
367	//fn MockFunction(comptime Register: type) type {	451	try expectEqual(@as(?MockRegister1, .r3), try function.register_manager.allocReg(mock_instruction));
368	// return struct {	452	try expectEqualSlices(MockRegister1, &[_]MockRegister1{.r2}, function.spilled.items);
369	// allocator: Allocator,	453
370	// register_manager: RegisterManager(Self, Register, &Register.allocatable_registers) = .{},	454	// Locked registers
371	// spilled: std.ArrayListUnmanaged(Register) = .{},	455	function.register_manager.freeReg(.r3);
372		456	{
373	// const Self = @This();	457	const lock = function.register_manager.lockReg(.r2);
374		458	defer if (lock) \|reg\| function.register_manager.unlockReg(reg);
375	// pub fn deinit(self: *Self) void {	459
376	// self.spilled.deinit(self.allocator);	460	try expectEqual(@as(?MockRegister1, .r3), try function.register_manager.allocReg(mock_instruction));
377	// }	461	}
378		462	try expect(!function.register_manager.lockedRegsExist());
379	// pub fn spillInstruction(self: *Self, reg: Register, inst: Air.Inst.Index) !void {	463	}
380	// _ = inst;	464
381	// try self.spilled.append(self.allocator, reg);	465	test "tryAllocRegs" {
382	// }	466	const allocator = std.testing.allocator;
383		467
384	// pub fn genAdd(self: *Self, res: Register, lhs: Register, rhs: Register) !void {	468	var function = MockFunction2{
385	// _ = self;	469	.allocator = allocator,
386	// _ = res;	470	};
387	// _ = lhs;	471	defer function.deinit();
388	// _ = rhs;	472
389	// }	473	try expectEqual([_]MockRegister2{ .r0, .r1, .r2 }, function.register_manager.tryAllocRegs(3, .{ null, null, null }).?);
390	// };	474
391	//}	475	try expect(function.register_manager.isRegAllocated(.r0));
392		476	try expect(function.register_manager.isRegAllocated(.r1));
393	//const MockFunction1 = MockFunction(MockRegister1);	477	try expect(function.register_manager.isRegAllocated(.r2));
394	//const MockFunction2 = MockFunction(MockRegister2);	478	try expect(!function.register_manager.isRegAllocated(.r3));
395		479
396	//test "default state" {	480	// Locked registers
397	// const allocator = std.testing.allocator;	481	function.register_manager.freeReg(.r0);
398		482	function.register_manager.freeReg(.r2);
399	// var function = MockFunction1{	483	function.register_manager.freeReg(.r3);
400	// .allocator = allocator,	484	{
401	// };	485	const lock = function.register_manager.lockReg(.r1);
402	// defer function.deinit();	486	defer if (lock) \|reg\| function.register_manager.unlockReg(reg);
403		487
404	// try expect(!function.register_manager.isRegAllocated(.r2));	488	try expectEqual([_]MockRegister2{ .r0, .r2, .r3 }, function.register_manager.tryAllocRegs(3, .{ null, null, null }).?);
405	// try expect(!function.register_manager.isRegAllocated(.r3));	489	}
406	// try expect(function.register_manager.isRegFree(.r2));	490	try expect(!function.register_manager.lockedRegsExist());
407	// try expect(function.register_manager.isRegFree(.r3));	491
408	//}	492	try expect(function.register_manager.isRegAllocated(.r0));
409		493	try expect(function.register_manager.isRegAllocated(.r1));
410	//test "tryAllocReg: no spilling" {	494	try expect(function.register_manager.isRegAllocated(.r2));
411	// const allocator = std.testing.allocator;	495	try expect(function.register_manager.isRegAllocated(.r3));
412		496	}
413	// var function = MockFunction1{	497
414	// .allocator = allocator,	498	test "allocRegs: normal usage" {
415	// };	499	// TODO: convert this into a decltest once that is supported
416	// defer function.deinit();	500
417		501	const allocator = std.testing.allocator;
418	// const mock_instruction: Air.Inst.Index = 1;	502
419		503	var function = MockFunction2{
420	// try expectEqual(@as(?MockRegister1, .r2), function.register_manager.tryAllocReg(mock_instruction));	504	.allocator = allocator,
421	// try expectEqual(@as(?MockRegister1, .r3), function.register_manager.tryAllocReg(mock_instruction));	505	};
422	// try expectEqual(@as(?MockRegister1, null), function.register_manager.tryAllocReg(mock_instruction));	506	defer function.deinit();
423		507
424	// try expect(function.register_manager.isRegAllocated(.r2));	508	{
425	// try expect(function.register_manager.isRegAllocated(.r3));	509	const result_reg: MockRegister2 = .r1;
426	// try expect(!function.register_manager.isRegFree(.r2));	510
427	// try expect(!function.register_manager.isRegFree(.r3));	511	// The result register is known and fixed at this point, we
428		512	// don't want to accidentally allocate lhs or rhs to the
429	// function.register_manager.freeReg(.r2);	513	// result register, this is why we lock it.
430	// function.register_manager.freeReg(.r3);	514	//
431		515	// Using defer unlock right after lock is a good idea in
432	// try expect(function.register_manager.isRegAllocated(.r2));	516	// most cases as you probably are using the locked registers
433	// try expect(function.register_manager.isRegAllocated(.r3));	517	// in the remainder of this scope and don't need to use it
434	// try expect(function.register_manager.isRegFree(.r2));	518	// after the end of this scope. However, in some situations,
435	// try expect(function.register_manager.isRegFree(.r3));	519	// it may make sense to manually unlock registers before the
436	//}	520	// end of the scope when you are certain that they don't
437		521	// contain any valuable data anymore and can be reused. For an
438	//test "allocReg: spilling" {	522	// example of that, see `selectively reducing register
439	// const allocator = std.testing.allocator;	523	// pressure`.
440		524	const lock = function.register_manager.lockReg(result_reg);
441	// var function = MockFunction1{	525	defer if (lock) \|reg\| function.register_manager.unlockReg(reg);
442	// .allocator = allocator,	526
443	// };	527	const regs = try function.register_manager.allocRegs(2, .{ null, null });
444	// defer function.deinit();	528	try function.genAdd(result_reg, regs[0], regs[1]);
445		529	}
446	// const mock_instruction: Air.Inst.Index = 1;	530	}
447		531
448	// try expectEqual(@as(?MockRegister1, .r2), try function.register_manager.allocReg(mock_instruction));	532	test "allocRegs: selectively reducing register pressure" {
449	// try expectEqual(@as(?MockRegister1, .r3), try function.register_manager.allocReg(mock_instruction));	533	// TODO: convert this into a decltest once that is supported
450		534
451	// // Spill a register	535	const allocator = std.testing.allocator;
452	// try expectEqual(@as(?MockRegister1, .r2), try function.register_manager.allocReg(mock_instruction));	536
453	// try expectEqualSlices(MockRegister1, &[_]MockRegister1{.r2}, function.spilled.items);	537	var function = MockFunction2{
454		538	.allocator = allocator,
455	// // No spilling necessary	539	};
456	// function.register_manager.freeReg(.r3);	540	defer function.deinit();
457	// try expectEqual(@as(?MockRegister1, .r3), try function.register_manager.allocReg(mock_instruction));	541
458	// try expectEqualSlices(MockRegister1, &[_]MockRegister1{.r2}, function.spilled.items);	542	{
459		543	const result_reg: MockRegister2 = .r1;
460	// // Locked registers	544
461	// function.register_manager.freeReg(.r3);	545	const lock = function.register_manager.lockReg(result_reg);
462	// {	546
463	// const lock = function.register_manager.lockReg(.r2);	547	// Here, we don't defer unlock because we manually unlock
464	// defer if (lock) \|reg\| function.register_manager.unlockReg(reg);	548	// after genAdd
465		549	const regs = try function.register_manager.allocRegs(2, .{ null, null });
466	// try expectEqual(@as(?MockRegister1, .r3), try function.register_manager.allocReg(mock_instruction));	550
467	// }	551	try function.genAdd(result_reg, regs[0], regs[1]);
468	// try expect(!function.register_manager.lockedRegsExist());	552	function.register_manager.unlockReg(lock.?);
469	//}	553
470		554	const extra_summand_reg = try function.register_manager.allocReg(null);
471	//test "tryAllocRegs" {	555	try function.genAdd(result_reg, result_reg, extra_summand_reg);
472	// const allocator = std.testing.allocator;	556	}
473		557	}
474	// var function = MockFunction2{	558
475	// .allocator = allocator,	559	test "getReg" {
476	// };	560	const allocator = std.testing.allocator;
477	// defer function.deinit();	561
478		562	var function = MockFunction1{
479	// try expectEqual([_]MockRegister2{ .r0, .r1, .r2 }, function.register_manager.tryAllocRegs(3, .{ null, null, null }).?);	563	.allocator = allocator,
480		564	};
481	// try expect(function.register_manager.isRegAllocated(.r0));	565	defer function.deinit();
482	// try expect(function.register_manager.isRegAllocated(.r1));	566
483	// try expect(function.register_manager.isRegAllocated(.r2));	567	const mock_instruction: Air.Inst.Index = 1;
484	// try expect(!function.register_manager.isRegAllocated(.r3));	568
485		569	try function.register_manager.getReg(.r3, mock_instruction);
486	// // Locked registers	570
487	// function.register_manager.freeReg(.r0);	571	try expect(!function.register_manager.isRegAllocated(.r2));
488	// function.register_manager.freeReg(.r2);	572	try expect(function.register_manager.isRegAllocated(.r3));
489	// function.register_manager.freeReg(.r3);	573	try expect(function.register_manager.isRegFree(.r2));
490	// {	574	try expect(!function.register_manager.isRegFree(.r3));
491	// const lock = function.register_manager.lockReg(.r1);	575
492	// defer if (lock) \|reg\| function.register_manager.unlockReg(reg);	576	// Spill r3
493		577	try function.register_manager.getReg(.r3, mock_instruction);
494	// try expectEqual([_]MockRegister2{ .r0, .r2, .r3 }, function.register_manager.tryAllocRegs(3, .{ null, null, null }).?);	578
495	// }	579	try expect(!function.register_manager.isRegAllocated(.r2));
496	// try expect(!function.register_manager.lockedRegsExist());	580	try expect(function.register_manager.isRegAllocated(.r3));
497		581	try expect(function.register_manager.isRegFree(.r2));
498	// try expect(function.register_manager.isRegAllocated(.r0));	582	try expect(!function.register_manager.isRegFree(.r3));
499	// try expect(function.register_manager.isRegAllocated(.r1));	583	try expectEqualSlices(MockRegister1, &[_]MockRegister1{.r3}, function.spilled.items);
500	// try expect(function.register_manager.isRegAllocated(.r2));	584	}
501	// try expect(function.register_manager.isRegAllocated(.r3));
502	//}
503
504	//test "allocRegs: normal usage" {
505	// // TODO: convert this into a decltest once that is supported
506
507	// const allocator = std.testing.allocator;
508
509	// var function = MockFunction2{
510	// .allocator = allocator,
511	// };
512	// defer function.deinit();
513
514	// {
515	// const result_reg: MockRegister2 = .r1;
516
517	// // The result register is known and fixed at this point, we
518	// // don't want to accidentally allocate lhs or rhs to the
519	// // result register, this is why we lock it.
520	// //
521	// // Using defer unlock right after lock is a good idea in
522	// // most cases as you probably are using the locked registers
523	// // in the remainder of this scope and don't need to use it
524	// // after the end of this scope. However, in some situations,
525	// // it may make sense to manually unlock registers before the
526	// // end of the scope when you are certain that they don't
527	// // contain any valuable data anymore and can be reused. For an
528	// // example of that, see `selectively reducing register
529	// // pressure`.
530	// const lock = function.register_manager.lockReg(result_reg);
531	// defer if (lock) \|reg\| function.register_manager.unlockReg(reg);
532
533	// const regs = try function.register_manager.allocRegs(2, .{ null, null });
534	// try function.genAdd(result_reg, regs[0], regs[1]);
535	// }
536	//}
537
538	//test "allocRegs: selectively reducing register pressure" {
539	// // TODO: convert this into a decltest once that is supported
540
541	// const allocator = std.testing.allocator;
542
543	// var function = MockFunction2{
544	// .allocator = allocator,
545	// };
546	// defer function.deinit();
547
548	// {
549	// const result_reg: MockRegister2 = .r1;
550
551	// const lock = function.register_manager.lockReg(result_reg);
552
553	// // Here, we don't defer unlock because we manually unlock
554	// // after genAdd
555	// const regs = try function.register_manager.allocRegs(2, .{ null, null });
556
557	// try function.genAdd(result_reg, regs[0], regs[1]);
558	// function.register_manager.unlockReg(lock.?);
559
560	// const extra_summand_reg = try function.register_manager.allocReg(null);
561	// try function.genAdd(result_reg, result_reg, extra_summand_reg);
562	// }
563	//}
564
565	//test "getReg" {
566	// const allocator = std.testing.allocator;
567
568	// var function = MockFunction1{
569	// .allocator = allocator,
570	// };
571	// defer function.deinit();
572
573	// const mock_instruction: Air.Inst.Index = 1;
574
575	// try function.register_manager.getReg(.r3, mock_instruction);
576
577	// try expect(!function.register_manager.isRegAllocated(.r2));
578	// try expect(function.register_manager.isRegAllocated(.r3));
579	// try expect(function.register_manager.isRegFree(.r2));
580	// try expect(!function.register_manager.isRegFree(.r3));
581
582	// // Spill r3
583	// try function.register_manager.getReg(.r3, mock_instruction);
584
585	// try expect(!function.register_manager.isRegAllocated(.r2));
586	// try expect(function.register_manager.isRegAllocated(.r3));
587	// try expect(function.register_manager.isRegFree(.r2));
588	// try expect(!function.register_manager.isRegFree(.r3));
589	// try expectEqualSlices(MockRegister1, &[_]MockRegister1{.r3}, function.spilled.items);
590	//}

...	@@ -78,13 +78,13 @@ pub fn generateFunction(	...	@@ -78,13 +78,13 @@ pub fn generateFunction(
78	debug_output: DebugInfoOutput,	78	debug_output: DebugInfoOutput,
79	) GenerateSymbolError!FnResult {	79	) GenerateSymbolError!FnResult {
80	switch (bin_file.options.target.cpu.arch) {	80	switch (bin_file.options.target.cpu.arch) {
81	// .arm,	81	.arm,
82	// .armeb,	82	.armeb,
83	// => return @import("arch/arm/CodeGen.zig").generate(bin_file, src_loc, func, air, liveness, code, debug_output),	83	=> return @import("arch/arm/CodeGen.zig").generate(bin_file, src_loc, func, air, liveness, code, debug_output),
84	// .aarch64,	84	.aarch64,
85	// .aarch64_be,	85	.aarch64_be,
86	// .aarch64_32,	86	.aarch64_32,
87	// => return @import("arch/aarch64/CodeGen.zig").generate(bin_file, src_loc, func, air, liveness, code, debug_output),	87	=> return @import("arch/aarch64/CodeGen.zig").generate(bin_file, src_loc, func, air, liveness, code, debug_output),
88	//.arc => return Function(.arc).generate(bin_file, src_loc, func, air, liveness, code, debug_output),	88	//.arc => return Function(.arc).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
89	//.avr => return Function(.avr).generate(bin_file, src_loc, func, air, liveness, code, debug_output),	89	//.avr => return Function(.avr).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
90	//.bpfel => return Function(.bpfel).generate(bin_file, src_loc, func, air, liveness, code, debug_output),	90	//.bpfel => return Function(.bpfel).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
...	@@ -101,9 +101,9 @@ pub fn generateFunction(	...	@@ -101,9 +101,9 @@ pub fn generateFunction(
101	//.r600 => return Function(.r600).generate(bin_file, src_loc, func, air, liveness, code, debug_output),	101	//.r600 => return Function(.r600).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
102	//.amdgcn => return Function(.amdgcn).generate(bin_file, src_loc, func, air, liveness, code, debug_output),	102	//.amdgcn => return Function(.amdgcn).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
103	//.riscv32 => return Function(.riscv32).generate(bin_file, src_loc, func, air, liveness, code, debug_output),	103	//.riscv32 => return Function(.riscv32).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
104	// .riscv64 => return @import("arch/riscv64/CodeGen.zig").generate(bin_file, src_loc, func, air, liveness, code, debug_output),	104	.riscv64 => return @import("arch/riscv64/CodeGen.zig").generate(bin_file, src_loc, func, air, liveness, code, debug_output),
105	//.sparc => return Function(.sparc).generate(bin_file, src_loc, func, air, liveness, code, debug_output),	105	//.sparc => return Function(.sparc).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
106	// .sparc64 => return @import("arch/sparc64/CodeGen.zig").generate(bin_file, src_loc, func, air, liveness, code, debug_output),	106	.sparc64 => return @import("arch/sparc64/CodeGen.zig").generate(bin_file, src_loc, func, air, liveness, code, debug_output),
107	//.sparcel => return Function(.sparcel).generate(bin_file, src_loc, func, air, liveness, code, debug_output),	107	//.sparcel => return Function(.sparcel).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
108	//.s390x => return Function(.s390x).generate(bin_file, src_loc, func, air, liveness, code, debug_output),	108	//.s390x => return Function(.s390x).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
109	//.tce => return Function(.tce).generate(bin_file, src_loc, func, air, liveness, code, debug_output),	109	//.tce => return Function(.tce).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
...	@@ -129,9 +129,9 @@ pub fn generateFunction(	...	@@ -129,9 +129,9 @@ pub fn generateFunction(
129	//.renderscript32 => return Function(.renderscript32).generate(bin_file, src_loc, func, air, liveness, code, debug_output),	129	//.renderscript32 => return Function(.renderscript32).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
130	//.renderscript64 => return Function(.renderscript64).generate(bin_file, src_loc, func, air, liveness, code, debug_output),	130	//.renderscript64 => return Function(.renderscript64).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
131	//.ve => return Function(.ve).generate(bin_file, src_loc, func, air, liveness, code, debug_output),	131	//.ve => return Function(.ve).generate(bin_file, src_loc, func, air, liveness, code, debug_output),
132	// .wasm32,	132	.wasm32,
133	// .wasm64,	133	.wasm64,
134	// => return @import("arch/wasm/CodeGen.zig").generate(bin_file, src_loc, func, air, liveness, code, debug_output),	134	=> return @import("arch/wasm/CodeGen.zig").generate(bin_file, src_loc, func, air, liveness, code, debug_output),
135	else => @panic("Backend architectures that don't have good support yet are commented out, to improve compilation performance. If you are interested in one of these other backends feel free to uncomment them. Eventually these will be completed, but stage1 is slow and a memory hog."),	135	else => @panic("Backend architectures that don't have good support yet are commented out, to improve compilation performance. If you are interested in one of these other backends feel free to uncomment them. Eventually these will be completed, but stage1 is slow and a memory hog."),
136	}	136	}
137	}	137	}