authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-09-05 22:59:09+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-09-05 22:59:09+02:00
log9eb2e11b854ecb58dd577edb009548f8da9a3927
tree5741c71d7ba2f6525f1b2be22840172855748ec7
parente39a2afa24a8f3db4d40b40703254011acc97efa
parent153371f5313c0ffbffe5a430a4e410f3d8608c53

Merge pull request '`std.zig.system`: some aarch64 detection enhancements/fixes' (#36764) from alexrp/zig:aarch64-detect-2 into master

Reviewed-on: https://codeberg.org/ziglang/zig/pulls/36764

2 files changed, 65 insertions(+), 79 deletions(-)

lib/std/zig/system/arm.zig+24-24
......@@ -242,6 +242,10 @@ pub const aarch64 = struct {
242242 return @as(u4, @truncate(input >> offset));
243243 }
244244
245 inline fn signedBitField(input: u64, offset: u6) i4 {
246 return @as(i4, @bitCast(@as(u4, @truncate(input >> offset))));
247 }
248
245249 /// Input array should consist of readouts from 12 system registers such that:
246250 /// 0 -> MIDR_EL1
247251 /// 1 -> ID_AA64PFR0_EL1
......@@ -255,18 +259,22 @@ pub const aarch64 = struct {
255259 /// 9 -> ID_AA64MMFR0_EL1
256260 /// 10 -> ID_AA64MMFR1_EL1
257261 /// 11 -> ID_AA64MMFR2_EL1
258 pub fn detectNativeCpuAndFeatures(arch: Target.Cpu.Arch, registers: [12]u64) ?Target.Cpu {
262 pub fn detectNativeCpuAndFeatures(arch: Target.Cpu.Arch, registers: [12]u64) Target.Cpu {
259263 const info = detectNativeCoreInfo(registers[0]);
260 const model = cpu_models.isKnown(info, true) orelse return null;
264 const model = cpu_models.isKnown(info, true) orelse Target.Cpu.Model.generic(arch);
261265
262266 var cpu = Target.Cpu{
263267 .arch = arch,
264268 .model = model,
265 .features = Target.Cpu.Feature.Set.empty,
269 .features = .empty,
266270 };
267271
272 cpu.features.addFeatureSet(model.features);
273
268274 detectNativeCpuFeatures(&cpu, registers[1..12]);
269 addInstructionFusions(&cpu, info);
275 addInstructionFusions(&cpu);
276
277 cpu.features.populateDependencies(cpu.arch.allFeaturesList());
270278
271279 return cpu;
272280 }
......@@ -318,14 +326,9 @@ pub const aarch64 = struct {
318326 setFeature(cpu, .sve, bitField(registers[0], 32) >= 1);
319327 setFeature(cpu, .el3, bitField(registers[0], 12) >= 1);
320328 setFeature(cpu, .ras, bitField(registers[0], 28) >= 1);
321
322 if (bitField(registers[0], 20) < 0xF) blk: {
323 if (bitField(registers[0], 16) != bitField(registers[0], 20)) break :blk; // This should never occur
324
325 setFeature(cpu, .neon, true);
326 setFeature(cpu, .fp_armv8, true);
327 setFeature(cpu, .fullfp16, bitField(registers[0], 20) > 0);
328 }
329 setFeature(cpu, .fp_armv8, signedBitField(registers[0], 16) >= 0);
330 setFeature(cpu, .neon, signedBitField(registers[0], 20) >= 0);
331 setFeature(cpu, .fullfp16, signedBitField(registers[0], 16) >= 1 and signedBitField(registers[0], 20) >= 1);
329332
330333 // ID_AA64PFR1_EL1
331334 setFeature(cpu, .mpam, bitField(registers[1], 16) > 0 and bitField(registers[0], 40) == 0); // MPAM v0.1
......@@ -336,7 +339,7 @@ pub const aarch64 = struct {
336339 // ID_AA64DFR0_EL1
337340 setFeature(cpu, .tracev8_4, bitField(registers[2], 40) >= 1);
338341 setFeature(cpu, .spe, bitField(registers[2], 32) >= 1);
339 setFeature(cpu, .perfmon, bitField(registers[2], 8) >= 1 and bitField(registers[2], 8) < 0xF);
342 setFeature(cpu, .perfmon, signedBitField(registers[2], 8) >= 1);
340343
341344 // ID_AA64DFR1_EL1 reserved
342345 // ID_AA64AFR0_EL1 reserved / implementation defined
......@@ -387,17 +390,14 @@ pub const aarch64 = struct {
387390 setFeature(cpu, .uaops, bitField(registers[10], 4) >= 1);
388391 }
389392
390 fn addInstructionFusions(cpu: *Target.Cpu, info: CoreInfo) void {
391 switch (info.implementer) {
392 0x41 => switch (info.part) {
393 0xd4b, 0xd4c => {
394 // According to A78C/X1C Core Software Optimization Guide, CPU fuses certain instructions.
395 setFeature(cpu, .cmp_bcc_fusion, true);
396 setFeature(cpu, .fuse_aes, true);
397 },
398 else => {},
399 },
400 else => {},
393 fn addInstructionFusions(cpu: *Target.Cpu) void {
394 const m = cpu.model;
395 const c = Target.aarch64.cpu;
396
397 if (m == &c.cortex_a78c or m == &c.cortex_x1c) {
398 // According to A78C/X1C Core Software Optimization Guide, CPU fuses certain instructions.
399 setFeature(cpu, .cmp_bcc_fusion, true);
400 setFeature(cpu, .fuse_aes, true);
401401 }
402402 }
403403};
lib/std/zig/system/windows.zig+41-55
......@@ -3,11 +3,10 @@ const builtin = @import("builtin");
33const assert = std.debug.assert;
44const mem = std.mem;
55const Target = std.Target;
6
7pub const WindowsVersion = std.Target.Os.WindowsVersion;
8pub const PF = std.os.windows.PF;
9pub const REG = std.os.windows.REG;
10pub const IsProcessorFeaturePresent = std.os.windows.IsProcessorFeaturePresent;
6const WindowsVersion = std.Target.Os.WindowsVersion;
7const PF = std.os.windows.PF;
8const REG = std.os.windows.REG;
9const IsProcessorFeaturePresent = std.os.windows.IsProcessorFeaturePresent;
1110
1211/// Returns the highest known WindowsVersion deduced from reported runtime information.
1312/// Discards information about in-between versions we don't differentiate.
......@@ -193,21 +192,19 @@ fn setFeature(comptime Feature: type, cpu: *Target.Cpu, feature: Feature, enable
193192 if (enabled) cpu.features.addFeature(idx) else cpu.features.removeFeature(idx);
194193}
195194
196fn getCpuCount() usize {
197 return std.os.windows.peb().NumberOfProcessors;
198}
199
200195/// If the fine-grained detection of CPU features via Win registry fails,
201196/// we fallback to a generic CPU model but we override the feature set
202197/// using `SharedUserData` contents.
203198/// This is effectively what LLVM does for all ARM chips on Windows.
204199fn genericCpuAndNativeFeatures(arch: Target.Cpu.Arch) Target.Cpu {
205 var cpu = Target.Cpu{
200 var cpu: Target.Cpu = .{
206201 .arch = arch,
207202 .model = Target.Cpu.Model.generic(arch),
208 .features = Target.Cpu.Feature.Set.empty,
203 .features = .empty,
209204 };
210205
206 cpu.features.addFeatureSet(cpu.model.features);
207
211208 switch (arch) {
212209 .aarch64, .aarch64_be => {
213210 const Feature = Target.aarch64.Feature;
......@@ -256,6 +253,8 @@ fn genericCpuAndNativeFeatures(arch: Target.Cpu.Arch) Target.Cpu {
256253 else => {},
257254 }
258255
256 cpu.features.populateDependencies(cpu.arch.allFeaturesList());
257
259258 return cpu;
260259}
261260
......@@ -263,52 +262,39 @@ pub fn detectNativeCpuAndFeatures() ?Target.Cpu {
263262 const current_arch = builtin.cpu.arch;
264263 const cpu: ?Target.Cpu = switch (current_arch) {
265264 .aarch64, .aarch64_be => blk: {
266 var cores: [128]Target.Cpu = undefined;
267 const core_count = getCpuCount();
268
269 if (core_count > cores.len) break :blk null;
270
271 var i: usize = 0;
272 while (i < core_count) : (i += 1) {
273 // Backing datastore
274 var registers: [12]u64 = undefined;
275
276 // Registry key to system ID register mapping
277 // CP 4000 -> MIDR_EL1
278 // CP 4020 -> ID_AA64PFR0_EL1
279 // CP 4021 -> ID_AA64PFR1_EL1
280 // CP 4028 -> ID_AA64DFR0_EL1
281 // CP 4029 -> ID_AA64DFR1_EL1
282 // CP 402C -> ID_AA64AFR0_EL1
283 // CP 402D -> ID_AA64AFR1_EL1
284 // CP 4030 -> ID_AA64ISAR0_EL1
285 // CP 4031 -> ID_AA64ISAR1_EL1
286 // CP 4038 -> ID_AA64MMFR0_EL1
287 // CP 4039 -> ID_AA64MMFR1_EL1
288 // CP 403A -> ID_AA64MMFR2_EL1
289 getCpuInfoFromRegistry(i, .{
290 .{ .key = "CP 4000", .value_type = REG.ValueType.QWORD, .value_buf = @as(*[8]u8, @ptrCast(&registers[0])) },
291 .{ .key = "CP 4020", .value_type = REG.ValueType.QWORD, .value_buf = @as(*[8]u8, @ptrCast(&registers[1])) },
292 .{ .key = "CP 4021", .value_type = REG.ValueType.QWORD, .value_buf = @as(*[8]u8, @ptrCast(&registers[2])) },
293 .{ .key = "CP 4028", .value_type = REG.ValueType.QWORD, .value_buf = @as(*[8]u8, @ptrCast(&registers[3])) },
294 .{ .key = "CP 4029", .value_type = REG.ValueType.QWORD, .value_buf = @as(*[8]u8, @ptrCast(&registers[4])) },
295 .{ .key = "CP 402C", .value_type = REG.ValueType.QWORD, .value_buf = @as(*[8]u8, @ptrCast(&registers[5])) },
296 .{ .key = "CP 402D", .value_type = REG.ValueType.QWORD, .value_buf = @as(*[8]u8, @ptrCast(&registers[6])) },
297 .{ .key = "CP 4030", .value_type = REG.ValueType.QWORD, .value_buf = @as(*[8]u8, @ptrCast(&registers[7])) },
298 .{ .key = "CP 4031", .value_type = REG.ValueType.QWORD, .value_buf = @as(*[8]u8, @ptrCast(&registers[8])) },
299 .{ .key = "CP 4038", .value_type = REG.ValueType.QWORD, .value_buf = @as(*[8]u8, @ptrCast(&registers[9])) },
300 .{ .key = "CP 4039", .value_type = REG.ValueType.QWORD, .value_buf = @as(*[8]u8, @ptrCast(&registers[10])) },
301 .{ .key = "CP 403A", .value_type = REG.ValueType.QWORD, .value_buf = @as(*[8]u8, @ptrCast(&registers[11])) },
302 }) catch break :blk null;
303
304 cores[i] = @import("arm.zig").aarch64.detectNativeCpuAndFeatures(current_arch, registers) orelse
305 break :blk null;
306 }
307
308 // Pick the first core, usually LITTLE in big.LITTLE architecture.
309 break :blk cores[0];
265 var registers: [12]u64 = undefined;
266
267 // CP 4000 -> MIDR_EL1
268 // CP 4020 -> ID_AA64PFR0_EL1
269 // CP 4021 -> ID_AA64PFR1_EL1
270 // CP 4028 -> ID_AA64DFR0_EL1
271 // CP 4029 -> ID_AA64DFR1_EL1
272 // CP 402C -> ID_AA64AFR0_EL1
273 // CP 402D -> ID_AA64AFR1_EL1
274 // CP 4030 -> ID_AA64ISAR0_EL1
275 // CP 4031 -> ID_AA64ISAR1_EL1
276 // CP 4038 -> ID_AA64MMFR0_EL1
277 // CP 4039 -> ID_AA64MMFR1_EL1
278 // CP 403A -> ID_AA64MMFR2_EL1
279 getCpuInfoFromRegistry(0, .{
280 .{ .key = "CP 4000", .value_type = REG.ValueType.QWORD, .value_buf = @as(*[8]u8, @ptrCast(&registers[0])) },
281 .{ .key = "CP 4020", .value_type = REG.ValueType.QWORD, .value_buf = @as(*[8]u8, @ptrCast(&registers[1])) },
282 .{ .key = "CP 4021", .value_type = REG.ValueType.QWORD, .value_buf = @as(*[8]u8, @ptrCast(&registers[2])) },
283 .{ .key = "CP 4028", .value_type = REG.ValueType.QWORD, .value_buf = @as(*[8]u8, @ptrCast(&registers[3])) },
284 .{ .key = "CP 4029", .value_type = REG.ValueType.QWORD, .value_buf = @as(*[8]u8, @ptrCast(&registers[4])) },
285 .{ .key = "CP 402C", .value_type = REG.ValueType.QWORD, .value_buf = @as(*[8]u8, @ptrCast(&registers[5])) },
286 .{ .key = "CP 402D", .value_type = REG.ValueType.QWORD, .value_buf = @as(*[8]u8, @ptrCast(&registers[6])) },
287 .{ .key = "CP 4030", .value_type = REG.ValueType.QWORD, .value_buf = @as(*[8]u8, @ptrCast(&registers[7])) },
288 .{ .key = "CP 4031", .value_type = REG.ValueType.QWORD, .value_buf = @as(*[8]u8, @ptrCast(&registers[8])) },
289 .{ .key = "CP 4038", .value_type = REG.ValueType.QWORD, .value_buf = @as(*[8]u8, @ptrCast(&registers[9])) },
290 .{ .key = "CP 4039", .value_type = REG.ValueType.QWORD, .value_buf = @as(*[8]u8, @ptrCast(&registers[10])) },
291 .{ .key = "CP 403A", .value_type = REG.ValueType.QWORD, .value_buf = @as(*[8]u8, @ptrCast(&registers[11])) },
292 }) catch break :blk null;
293
294 break :blk @import("arm.zig").aarch64.detectNativeCpuAndFeatures(current_arch, registers);
310295 },
311296 else => null,
312297 };
298
313299 return cpu orelse genericCpuAndNativeFeatures(current_arch);
314300}