authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-10-20 10:09:01+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2026-10-20 10:09:01+02:00
loga0f9377690d107e9d190981529951340327371de
treeead06f08f355b809ba04a67de07706d955c36a43
parent6d24378a301076621bd84f484bc4e128ed21da78
signature Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

compiler_rt.fmv: avoid depending on @import("aarch64_outline_atomics.zig").__aarch64_have_lse_atomics

3 files changed, 5 insertions(+), 3 deletions(-)

lib/compiler_rt/aarch64_outline_atomics.zig+1-1
...@@ -9,7 +9,7 @@ const always_has_lse = builtin.cpu.has(.aarch64, .lse);...@@ -9,7 +9,7 @@ const always_has_lse = builtin.cpu.has(.aarch64, .lse);
9/// It is intentionally not exported in order to make the machine code that9/// It is intentionally not exported in order to make the machine code that
10/// uses it a statically predicted direct branch rather than using the PLT,10/// uses it a statically predicted direct branch rather than using the PLT,
11/// which ARM is concerned would have too much overhead.11/// which ARM is concerned would have too much overhead.
12pub var __aarch64_have_lse_atomics: u8 = @intFromBool(always_has_lse);12var __aarch64_have_lse_atomics: u8 = @intFromBool(always_has_lse);
1313
14fn __aarch64_cas1_relax() align(16) callconv(.naked) void {14fn __aarch64_cas1_relax() align(16) callconv(.naked) void {
15 @setRuntimeSafety(false);15 @setRuntimeSafety(false);
lib/compiler_rt/fmv.zig+3-1
...@@ -18,7 +18,7 @@ comptime {...@@ -18,7 +18,7 @@ comptime {
18const aarch64 = struct {18const aarch64 = struct {
19 comptime {19 comptime {
20 symbol(&__aarch64_cpu_features, "__aarch64_cpu_features");20 symbol(&__aarch64_cpu_features, "__aarch64_cpu_features");
21 symbol(&@import("aarch64_outline_atomics.zig").__aarch64_have_lse_atomics, "__aarch64_have_lse_atomics");21 symbol(&__aarch64_have_lse_atomics, "__aarch64_have_lse_atomics");
22 symbol(&__init_cpu_features_resolver, "__init_cpu_features_resolver");22 symbol(&__init_cpu_features_resolver, "__init_cpu_features_resolver");
23 }23 }
2424
...@@ -28,6 +28,8 @@ const aarch64 = struct {...@@ -28,6 +28,8 @@ const aarch64 = struct {
28 .features = 0,28 .features = 0,
29 };29 };
3030
31 var __aarch64_have_lse_atomics: bool = false;
32
31 const __init_cpu_features_resolver = switch (builtin.target.os.tag) {33 const __init_cpu_features_resolver = switch (builtin.target.os.tag) {
32 .fuchsia,34 .fuchsia,
33 .driverkit,35 .driverkit,
tools/gen_outline_atomics.zig+1-1
...@@ -32,7 +32,7 @@ pub fn main(init: std.process.Init) !void {...@@ -32,7 +32,7 @@ pub fn main(init: std.process.Init) !void {
32 \\/// It is intentionally not exported in order to make the machine code that32 \\/// It is intentionally not exported in order to make the machine code that
33 \\/// uses it a statically predicted direct branch rather than using the PLT,33 \\/// uses it a statically predicted direct branch rather than using the PLT,
34 \\/// which ARM is concerned would have too much overhead.34 \\/// which ARM is concerned would have too much overhead.
35 \\pub var __aarch64_have_lse_atomics: u8 = @intFromBool(always_has_lse);35 \\var __aarch64_have_lse_atomics: u8 = @intFromBool(always_has_lse);
36 \\36 \\
37 \\37 \\
38 );38 );