diff --git a/lib/std/crypto/aes.zig b/lib/std/crypto/aes.zig
index 6073886e5265446a0a47ae67e6c075ddb9c514a2..70246e6630b03fcb8be7ed9f2f87f995909e3bb6 100644
--- a/lib/std/crypto/aes.zig
+++ b/lib/std/crypto/aes.zig
@@ -8,7 +8,7 @@ const has_armaes = std.Target.aarch64.featureSetHas(builtin.cpu.features, .aes);
 // C backend doesn't currently support passing vectors to inline asm.
 const impl = if (builtin.cpu.arch == .x86_64 and builtin.zig_backend != .stage2_c and has_aesni and has_avx) impl: {
     break :impl @import("aes/aesni.zig");
-} else if (builtin.cpu.arch == .aarch64 and has_armaes)
+} else if (builtin.cpu.arch == .aarch64 and builtin.zig_backend != .stage2_c and has_armaes)
 impl: {
     break :impl @import("aes/armcrypto.zig");
 } else impl: {
diff --git a/lib/std/crypto/ghash_polyval.zig b/lib/std/crypto/ghash_polyval.zig
index 90339fcdc2fe000a4aced7bccac6c16726ddd5fa..2bb118c791765663c9bb94df6de7cfc63dae9958 100644
--- a/lib/std/crypto/ghash_polyval.zig
+++ b/lib/std/crypto/ghash_polyval.zig
@@ -251,7 +251,7 @@ fn Hash(comptime endian: std.builtin.Endian, comptime shift_key: bool) type {
         // C backend doesn't currently support passing vectors to inline asm.
         const clmul = if (builtin.cpu.arch == .x86_64 and builtin.zig_backend != .stage2_c and has_pclmul and has_avx) impl: {
             break :impl clmulPclmul;
-        } else if (builtin.cpu.arch == .aarch64 and has_armaes) impl: {
+        } else if (builtin.cpu.arch == .aarch64 and builtin.zig_backend != .stage2_c and has_armaes) impl: {
             break :impl clmulPmull;
         } else impl: {
             break :impl clmulSoft;
diff --git a/lib/std/crypto/sha2.zig b/lib/std/crypto/sha2.zig
index 6080f0b52804a184ebbbb478ccfe311e254e4b18..07bda8958531ff81cc58d095d2fc4de470b9b96c 100644
--- a/lib/std/crypto/sha2.zig
+++ b/lib/std/crypto/sha2.zig
@@ -205,7 +205,7 @@ fn Sha2x32(comptime params: Sha2Params32) type {
 
             if (!isComptime()) {
                 switch (builtin.cpu.arch) {
-                    .aarch64 => if (comptime std.Target.aarch64.featureSetHas(builtin.cpu.features, .sha2)) {
+                    .aarch64 => if (builtin.zig_backend != .stage2_c and comptime std.Target.aarch64.featureSetHas(builtin.cpu.features, .sha2)) {
                         var x: v4u32 = d.s[0..4].*;
                         var y: v4u32 = d.s[4..8].*;
                         const s_v = @ptrCast(*[16]v4u32, &s);
diff --git a/src/codegen/c.zig b/src/codegen/c.zig
index 88185f32d52fbbc65409b53528ecf833323264dd..f2c65e098aaaa08c9673a4a2169cf105d5564c0d 100644
--- a/src/codegen/c.zig
+++ b/src/codegen/c.zig
@@ -6070,9 +6070,18 @@ fn airAtomicRmw(f: *Function, inst: Air.Inst.Index) !CValue {
     if (is_float) try writer.writeAll("_float");
     try writer.writeByte('(');
     try f.writeCValue(writer, local, .Other);
-    try writer.writeAll(", (zig_atomic(");
-    try f.renderType(writer, ty);
-    try writer.writeByte(')');
+    try writer.writeAll(", (");
+    switch (extra.op()) {
+        else => {
+            try writer.writeAll("zig_atomic(");
+            try f.renderType(writer, ty);
+            try writer.writeByte(')');
+        },
+        .Nand, .Min, .Max => {
+            // These are missing from stdatomic.h, so no atomic types for now.
+            try f.renderType(writer, ty);
+        },
+    }
     if (ptr_ty.isVolatilePtr()) try writer.writeAll(" volatile");
     try writer.writeAll(" *)");
     try f.writeCValue(writer, ptr, .Other);
diff --git a/test/cases/compile_errors/atomicrmw_with_float_op_not_.Xchg_.Add_.Sub_.Max_or_.Min.zig b/test/cases/compile_errors/atomicrmw_with_float_op_not_.Xchg_.Add_.Sub_.Max_or_.Min.zig
new file mode 100644
index 0000000000000000000000000000000000000000..5714b323f1f483b3a46496be75af0950dcc0711d
--- /dev/null
+++ b/test/cases/compile_errors/atomicrmw_with_float_op_not_.Xchg_.Add_.Sub_.Max_or_.Min.zig
@@ -0,0 +1,10 @@
+export fn entry() void {
+    var x: f32 = 0;
+    _ = @atomicRmw(f32, &x, .And, 2, .SeqCst);
+}
+
+// error
+// backend=stage2
+// target=native
+//
+// :3:30: error: @atomicRmw with float only allowed with .Xchg, .Add, .Sub, .Max, and .Min
diff --git a/test/cases/compile_errors/atomicrmw_with_float_op_not_.Xchg_.Add_or_.Sub.zig b/test/cases/compile_errors/atomicrmw_with_float_op_not_.Xchg_.Add_or_.Sub.zig
deleted file mode 100644
index 80720fbca16aed050b006f9e70b3be1889e4f20d..0000000000000000000000000000000000000000
--- a/test/cases/compile_errors/atomicrmw_with_float_op_not_.Xchg_.Add_or_.Sub.zig
+++ /dev/null
@@ -1,10 +0,0 @@
-export fn entry() void {
-    var x: f32 = 0;
-    _ = @atomicRmw(f32, &x, .And, 2, .SeqCst);
-}
-
-// error
-// backend=stage2
-// target=native
-//
-// :3:30: error: @atomicRmw with float only allowed with .Xchg, .Add, and .Sub