| ... | ... | @@ -2,9 +2,7 @@ const std = @import("std"); |
| 2 | 2 | const mem = std.mem; |
| 3 | 3 | const expectEqual = std.testing.expectEqual; |
| 4 | 4 | |
| 5 | | inline fn rotl(comptime count: comptime_int, value: anytype) @TypeOf(value) { |
| 6 | | return (value << count) | (value >> (@bitSizeOf(@TypeOf(value)) - count)); |
| 7 | | } |
| 5 | const rotl = std.math.rotl; |
| 8 | 6 | |
| 9 | 7 | pub const XxHash64 = struct { |
| 10 | 8 | acc1: u64, |
| ... | ... | @@ -71,7 +69,7 @@ pub const XxHash64 = struct { |
| 71 | 69 | |
| 72 | 70 | inline fn round(acc: u64, lane: u64) u64 { |
| 73 | 71 | const a = acc +% (lane *% prime_2); |
| 74 | | const b = rotl(31, a); |
| 72 | const b = rotl(u64, a, 31); |
| 75 | 73 | return b *% prime_1; |
| 76 | 74 | } |
| 77 | 75 | |
| ... | ... | @@ -81,7 +79,8 @@ pub const XxHash64 = struct { |
| 81 | 79 | if (self.byte_count < 32) { |
| 82 | 80 | acc = self.seed +% prime_5; |
| 83 | 81 | } else { |
| 84 | | acc = rotl(1, self.acc1) +% rotl(7, self.acc2) +% rotl(12, self.acc3) +% rotl(18, self.acc4); |
| 82 | acc = rotl(u64, self.acc1, 1) +% rotl(u64, self.acc2, 7) +% |
| 83 | rotl(u64, self.acc3, 12) +% rotl(u64, self.acc4, 18); |
| 85 | 84 | acc = mergeAccumulator(acc, self.acc1); |
| 86 | 85 | acc = mergeAccumulator(acc, self.acc2); |
| 87 | 86 | acc = mergeAccumulator(acc, self.acc3); |
| ... | ... | @@ -94,14 +93,14 @@ pub const XxHash64 = struct { |
| 94 | 93 | while (pos + 8 <= self.buf_len) : (pos += 8) { |
| 95 | 94 | const lane = mem.readIntLittle(u64, self.buf[pos..][0..8]); |
| 96 | 95 | acc ^= round(0, lane); |
| 97 | | acc = rotl(27, acc) *% prime_1; |
| 96 | acc = rotl(u64, acc, 27) *% prime_1; |
| 98 | 97 | acc +%= prime_4; |
| 99 | 98 | } |
| 100 | 99 | |
| 101 | 100 | if (pos + 4 <= self.buf_len) { |
| 102 | 101 | const lane = @as(u64, mem.readIntLittle(u32, self.buf[pos..][0..4])); |
| 103 | 102 | acc ^= lane *% prime_1; |
| 104 | | acc = rotl(23, acc) *% prime_2; |
| 103 | acc = rotl(u64, acc, 23) *% prime_2; |
| 105 | 104 | acc +%= prime_3; |
| 106 | 105 | pos += 4; |
| 107 | 106 | } |
| ... | ... | @@ -109,7 +108,7 @@ pub const XxHash64 = struct { |
| 109 | 108 | while (pos < self.buf_len) : (pos += 1) { |
| 110 | 109 | const lane = @as(u64, self.buf[pos]); |
| 111 | 110 | acc ^= lane *% prime_5; |
| 112 | | acc = rotl(11, acc) *% prime_1; |
| 111 | acc = rotl(u64, acc, 11) *% prime_1; |
| 113 | 112 | } |
| 114 | 113 | |
| 115 | 114 | acc ^= acc >> 33; |
| ... | ... | @@ -199,7 +198,7 @@ pub const XxHash32 = struct { |
| 199 | 198 | |
| 200 | 199 | inline fn round(acc: u32, lane: u32) u32 { |
| 201 | 200 | const a = acc +% (lane *% prime_2); |
| 202 | | const b = rotl(13, a); |
| 201 | const b = rotl(u32, a, 13); |
| 203 | 202 | return b *% prime_1; |
| 204 | 203 | } |
| 205 | 204 | |
| ... | ... | @@ -209,7 +208,8 @@ pub const XxHash32 = struct { |
| 209 | 208 | if (self.byte_count < 16) { |
| 210 | 209 | acc = self.seed +% prime_5; |
| 211 | 210 | } else { |
| 212 | | acc = rotl(1, self.acc1) +% rotl(7, self.acc2) +% rotl(12, self.acc3) +% rotl(18, self.acc4); |
| 211 | acc = rotl(u32, self.acc1, 1) +% rotl(u32, self.acc2, 7) +% |
| 212 | rotl(u32, self.acc3, 12) +% rotl(u32, self.acc4, 18); |
| 213 | 213 | } |
| 214 | 214 | |
| 215 | 215 | acc = acc +% @intCast(u32, self.byte_count) +% @intCast(u32, self.buf_len); |
| ... | ... | @@ -218,13 +218,13 @@ pub const XxHash32 = struct { |
| 218 | 218 | while (pos + 4 <= self.buf_len) : (pos += 4) { |
| 219 | 219 | const lane = mem.readIntLittle(u32, self.buf[pos..][0..4]); |
| 220 | 220 | acc +%= lane *% prime_3; |
| 221 | | acc = rotl(17, acc) *% prime_4; |
| 221 | acc = rotl(u32, acc, 17) *% prime_4; |
| 222 | 222 | } |
| 223 | 223 | |
| 224 | 224 | while (pos < self.buf_len) : (pos += 1) { |
| 225 | 225 | const lane = @as(u32, self.buf[pos]); |
| 226 | 226 | acc +%= lane *% prime_5; |
| 227 | | acc = rotl(11, acc) *% prime_1; |
| 227 | acc = rotl(u32, acc, 11) *% prime_1; |
| 228 | 228 | } |
| 229 | 229 | |
| 230 | 230 | acc ^= acc >> 15; |
Dominic <4678790+dweiller@users.noreply.github.com> 2023-02-21 11:30:59+11:00
lib