authorgravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2020-01-19 02:40:35-05:00
committergravatar for andrew@ziglang.orgAndrew Kelley <andrew@ziglang.org> 2020-01-19 20:54:04-05:00
loga867b43366c7fb132ec44a03f9b40ead888900fb
tree13cb163c8e42f78b690481ea60bcbea97465396e
parentc15623428e83bd8baa1450678bf59beab2c2df99
signaturelock-open Commit is signed but in an unrecognized format.

progress towards merging

see BRANCH_TODO file

17 files changed, 2088 insertions(+), 2043 deletions(-)

BRANCH_TODO created+55
......@@ -0,0 +1,55 @@
1Finish these thigns before merging teh branch
2
3 * need to populate builtin.zig cpu_features, undefined is incorrect. I guess for zig0 it will be always baseline
4 * need to populate std.Target.current.cpu_features even for native target
5
6 * finish refactoring target/arch/*
7 * `zig builtin` integration
8 * move target details to better location
9 * +foo,-bar vs foo,bar
10 * baseline features
11
12
13const riscv32_default_features: []*const std.target.Feature = &[_]*const std.target.Feature{
14 &std.target.riscv.feature_a,
15 &std.target.riscv.feature_c,
16 &std.target.riscv.feature_d,
17 &std.target.riscv.feature_f,
18 &std.target.riscv.feature_m,
19 &std.target.riscv.feature_relax,
20};
21
22const riscv64_default_features: []*const std.target.Feature = &[_]*const std.target.Feature{
23 &std.target.riscv.feature_bit64,
24 &std.target.riscv.feature_a,
25 &std.target.riscv.feature_c,
26 &std.target.riscv.feature_d,
27 &std.target.riscv.feature_f,
28 &std.target.riscv.feature_m,
29 &std.target.riscv.feature_relax,
30};
31
32const i386_default_features: []*const std.target.Feature = &[_]*const std.target.Feature{
33 &std.target.x86.feature_cmov,
34 &std.target.x86.feature_cx8,
35 &std.target.x86.feature_fxsr,
36 &std.target.x86.feature_mmx,
37 &std.target.x86.feature_nopl,
38 &std.target.x86.feature_sse,
39 &std.target.x86.feature_sse2,
40 &std.target.x86.feature_slowUnalignedMem16,
41 &std.target.x86.feature_x87,
42};
43
44// Same as above but without sse.
45const i386_default_features_freestanding: []*const std.target.Feature = &[_]*const std.target.Feature{
46 &std.target.x86.feature_cmov,
47 &std.target.x86.feature_cx8,
48 &std.target.x86.feature_fxsr,
49 &std.target.x86.feature_mmx,
50 &std.target.x86.feature_nopl,
51 &std.target.x86.feature_slowUnalignedMem16,
52 &std.target.x86.feature_x87,
53};
54
55
lib/std/buffer.zig+2-2
......@@ -57,11 +57,11 @@ pub const Buffer = struct {
5757
5858 /// The caller owns the returned memory. The Buffer becomes null and
5959 /// is safe to `deinit`.
60 pub fn toOwnedSlice(self: *Buffer) []u8 {
60 pub fn toOwnedSlice(self: *Buffer) [:0]u8 {
6161 const allocator = self.list.allocator;
6262 const result = allocator.shrink(self.list.items, self.len());
6363 self.* = initNull(allocator);
64 return result;
64 return result[0 .. result.len - 1 :0];
6565 }
6666
6767 pub fn allocPrint(allocator: *Allocator, comptime format: []const u8, args: var) !Buffer {
lib/std/build.zig+21-28
......@@ -1199,8 +1199,6 @@ pub const LibExeObjStep = struct {
11991199
12001200 subsystem: ?builtin.SubSystem = null,
12011201
1202 target_details: ?std.target.TargetDetails = null,
1203
12041202 const LinkObject = union(enum) {
12051203 StaticPath: []const u8,
12061204 OtherStep: *LibExeObjStep,
......@@ -1386,10 +1384,6 @@ pub const LibExeObjStep = struct {
13861384 self.computeOutFileNames();
13871385 }
13881386
1389 pub fn setTargetDetails(self: *LibExeObjStep, target_details: std.target.TargetDetails) void {
1390 self.target_details = target_details;
1391 }
1392
13931387 pub fn setTargetGLibC(self: *LibExeObjStep, major: u32, minor: u32, patch: u32) void {
13941388 self.target_glibc = Version{
13951389 .major = major,
......@@ -1974,32 +1968,31 @@ pub const LibExeObjStep = struct {
19741968
19751969 switch (self.target) {
19761970 .Native => {},
1977 .Cross => {
1971 .Cross => |cross| {
19781972 try zig_args.append("-target");
19791973 try zig_args.append(self.target.zigTriple(builder.allocator) catch unreachable);
1980 },
1981 }
19821974
1983 if (self.target_details) |td| {
1984 switch (td) {
1985 .cpu => |cpu| {
1986 try zig_args.append("--cpu");
1987 try zig_args.append(cpu.name);
1988 },
1989 .features => |features| {
1990 try zig_args.append("--features");
1991
1992 var feature_str_buffer = try std.Buffer.initSize(builder.allocator, 0);
1993 defer feature_str_buffer.deinit();
1994
1995 for (features) |feature| {
1996 try feature_str_buffer.append(feature.name);
1997 try feature_str_buffer.append(",");
1998 }
1975 switch (cross.cpu_features) {
1976 .baseline => {},
1977 .cpu => |cpu| {
1978 try zig_args.append("-target-cpu");
1979 try zig_args.append(cpu.name);
1980 },
1981 .features => |features| {
1982 try zig_args.append("-target-cpu-features");
1983
1984 var feature_str_buffer = try std.Buffer.initSize(builder.allocator, 0);
1985 for (self.target.getArch().allFeaturesList()) |feature, i| {
1986 if (Target.Cpu.Feature.isEnabled(features, @intCast(u7, i))) {
1987 try feature_str_buffer.append(feature.name);
1988 try feature_str_buffer.append(",");
1989 }
1990 }
19991991
2000 try zig_args.append(feature_str_buffer.toOwnedSlice());
2001 },
2002 }
1992 try zig_args.append(feature_str_buffer.toSlice());
1993 },
1994 }
1995 },
20031996 }
20041997
20051998 if (self.target_glibc) |ver| {
lib/std/builtin.zig+6
......@@ -15,6 +15,12 @@ pub const ObjectFormat = std.Target.ObjectFormat;
1515/// Deprecated: use `std.Target.SubSystem`.
1616pub const SubSystem = std.Target.SubSystem;
1717
18/// Deprecated: use `std.Target.Cross.CpuFeatures`.
19pub const CpuFeatures = std.Target.Cross.CpuFeatures;
20
21/// Deprecated: use `std.Target.Cpu`.
22pub const Cpu = std.Target.Cpu;
23
1824/// `explicit_subsystem` is missing when the subsystem is automatically detected,
1925/// so Zig standard library has the subsystem detection logic here. This should generally be
2026/// used rather than `explicit_subsystem`.
lib/std/fmt.zig+5
......@@ -1138,6 +1138,11 @@ fn countSize(size: *usize, bytes: []const u8) (error{}!void) {
11381138 size.* += bytes.len;
11391139}
11401140
1141pub fn allocPrint0(allocator: *mem.Allocator, comptime fmt: []const u8, args: var) AllocPrintError![:0]u8 {
1142 const result = try allocPrint(allocator, fmt ++ "\x00", args);
1143 return result[0 .. result.len - 1 :0];
1144}
1145
11411146test "bufPrintInt" {
11421147 var buffer: [100]u8 = undefined;
11431148 const buf = buffer[0..];
lib/std/meta.zig+18
......@@ -556,3 +556,21 @@ pub fn refAllDecls(comptime T: type) void {
556556 if (!builtin.is_test) return;
557557 _ = declarations(T);
558558}
559
560/// Returns a slice of pointers to public declarations of a namespace.
561pub fn declList(comptime Namespace: type, comptime Decl: type) []const *const Decl {
562 const S = struct {
563 fn declNameLessThan(lhs: *const Decl, rhs: *const Decl) bool {
564 return mem.lessThan(u8, lhs.name, rhs.name);
565 }
566 };
567 comptime {
568 const decls = declarations(Namespace);
569 var array: [decls.len]*const Decl = undefined;
570 for (decls) |decl, i| {
571 array[i] = &@field(Namespace, decl.name);
572 }
573 std.sort.sort(*const Decl, &array, S.declNameLessThan);
574 return &array;
575 }
576}
lib/std/os/linux/tls.zig+1-1
......@@ -211,7 +211,7 @@ pub fn initTLS() ?*elf.Phdr {
211211
212212 if (tls_phdr) |phdr| {
213213 // If the cpu is arm-based, check if it supports the TLS register
214 if (builtin.arch == builtin.Arch.arm and at_hwcap & std.os.linux.HWCAP_TLS == 0) {
214 if (builtin.arch == .arm and at_hwcap & std.os.linux.HWCAP_TLS == 0) {
215215 // If the CPU does not support TLS via a coprocessor register,
216216 // a kernel helper function can be used instead on certain linux kernels.
217217 // See linux/arch/arm/include/asm/tls.h and musl/src/thread/arm/__set_thread_area.c.
lib/std/std.zig-1
......@@ -60,7 +60,6 @@ pub const rand = @import("rand.zig");
6060pub const rb = @import("rb.zig");
6161pub const sort = @import("sort.zig");
6262pub const ascii = @import("ascii.zig");
63pub const target = @import("target.zig");
6463pub const testing = @import("testing.zig");
6564pub const time = @import("time.zig");
6665pub const unicode = @import("unicode.zig");
lib/std/target.zig+218-106
......@@ -101,6 +101,22 @@ pub const Target = union(enum) {
101101 renderscript32,
102102 renderscript64,
103103
104 pub const aarch64 = @import("target/aarch64.zig");
105 pub const amdgpu = @import("target/amdgpu.zig");
106 pub const arm = @import("target/arm.zig");
107 pub const avr = @import("target/avr.zig");
108 pub const bpf = @import("target/bpf.zig");
109 pub const hexagon = @import("target/hexagon.zig");
110 pub const mips = @import("target/mips.zig");
111 pub const msp430 = @import("target/msp430.zig");
112 pub const nvptx = @import("target/nvptx.zig");
113 pub const powerpc = @import("target/powerpc.zig");
114 pub const riscv = @import("target/riscv.zig");
115 pub const sparc = @import("target/sparc.zig");
116 pub const systemz = @import("target/systemz.zig");
117 pub const wasm = @import("target/wasm.zig");
118 pub const x86 = @import("target/x86.zig");
119
104120 pub const Arm32 = enum {
105121 v8_5a,
106122 v8_4a,
......@@ -184,6 +200,71 @@ pub const Target = union(enum) {
184200 };
185201 }
186202
203 pub fn parseCpu(arch: Arch, cpu_name: []const u8) !*const Cpu {
204 for (arch.allCpus()) |cpu| {
205 if (mem.eql(u8, cpu_name, cpu.name)) {
206 return cpu;
207 }
208 }
209 return error.UnknownCpu;
210 }
211
212 /// This parsing function supports 2 syntaxes.
213 /// * Comma-separated list of features, with + or - in front of each feature. This
214 /// form represents a deviation from baseline.
215 /// * Comma-separated list of features, with no + or - in front of each feature. This
216 /// form represents an exclusive list of enabled features; no other features besides
217 /// the ones listed, and their dependencies, will be enabled.
218 /// Extra commas are ignored.
219 pub fn parseCpuFeatureSet(arch: Arch, features_text: []const u8) !Cpu.Feature.Set {
220 // Here we compute both and choose the correct result at the end, based
221 // on whether or not we saw + and - signs.
222 var set: @Vector(2, Cpu.Feature.Set) = [2]Cpu.Feature.Set{ 0, arch.baselineFeatures() };
223 var mode: enum {
224 unknown,
225 baseline,
226 whitelist,
227 } = .unknown;
228
229 var it = mem.tokenize(features_text, ",");
230 while (it.next()) |item_text| {
231 const feature_name = blk: {
232 if (mem.startsWith(u8, item_text, "+")) {
233 switch (mode) {
234 .unknown, .baseline => mode = .baseline,
235 .whitelist => return error.InvalidCpuFeatures,
236 }
237 break :blk item_text[1..];
238 } else if (mem.startsWith(u8, item_text, "-")) {
239 switch (mode) {
240 .unknown, .baseline => mode = .baseline,
241 .whitelist => return error.InvalidCpuFeatures,
242 }
243 break :blk item_text[1..];
244 } else {
245 switch (mode) {
246 .unknown, .whitelist => mode = .whitelist,
247 .baseline => return error.InvalidCpuFeatures,
248 }
249 break :blk item_text;
250 }
251 };
252 for (arch.allFeaturesList()) |feature, index| {
253 if (mem.eql(u8, feature_name, feature.name)) {
254 set |= @splat(2, 1 << index);
255 break;
256 }
257 } else {
258 return error.UnknownCpuFeature;
259 }
260 }
261
262 return switch (mode) {
263 .unknown, .whitelist => set[0],
264 .baseline => set[1],
265 };
266 }
267
187268 pub fn toElfMachine(arch: Arch) std.elf.EM {
188269 return switch (arch) {
189270 .avr => ._AVR,
......@@ -296,6 +377,98 @@ pub const Target = union(enum) {
296377 => .Big,
297378 };
298379 }
380
381 /// Returns a name that matches the lib/std/target/* directory name.
382 pub fn genericName(arch: Arch) []const u8 {
383 return switch (arch) {
384 .arm, .armeb, .thumb, .thumbeb => "arm",
385 .aarch64, .aarch64_be, .aarch64_32 => "aarch64",
386 .avr => "avr",
387 .bpfel, .bpfeb => "bpf",
388 .hexagon => "hexagon",
389 .mips, .mipsel, .mips64, .mips64el => "mips",
390 .msp430 => "msp430",
391 .powerpc, .powerpc64, .powerpc64le => "powerpc",
392 .amdgcn => "amdgpu",
393 .riscv32, .riscv64 => "riscv",
394 .sparc, .sparcv9, .sparcel => "sparc",
395 .s390x => "systemz",
396 .i386, .x86_64 => "x86",
397 .nvptx, .nvptx64 => "nvptx",
398 .wasm32, .wasm64 => "wasm",
399 else => @tagName(arch),
400 };
401 }
402
403 /// All CPU features Zig is aware of, sorted lexicographically by name.
404 pub fn allFeaturesList(arch: Arch) []const *const Cpu.Feature {
405 return switch (arch) {
406 .arm, .armeb, .thumb, .thumbeb => arm.all_features,
407 .aarch64, .aarch64_be, .aarch64_32 => aarch64.all_features,
408 .avr => avr.all_features,
409 .bpfel, .bpfeb => bpf.all_features,
410 .hexagon => hexagon.all_features,
411 .mips, .mipsel, .mips64, .mips64el => mips.all_features,
412 .msp430 => msp430.all_features,
413 .powerpc, .powerpc64, .powerpc64le => powerpc.all_features,
414 .amdgcn => amdgpu.all_features,
415 .riscv32, .riscv64 => riscv.all_features,
416 .sparc, .sparcv9, .sparcel => sparc.all_features,
417 .s390x => systemz.all_features,
418 .i386, .x86_64 => x86.all_features,
419 .nvptx, .nvptx64 => nvptx.all_features,
420 .wasm32, .wasm64 => wasm.all_features,
421
422 else => &[0]*const Cpu.Feature{},
423 };
424 }
425
426 /// The "default" set of CPU features for cross-compiling. A conservative set
427 /// of features that is expected to be supported on most available hardware.
428 pub fn baselineFeatures(arch: Arch) Cpu.Feature.Set {
429 return switch (arch) {
430 .arm, .armeb, .thumb, .thumbeb => arm.baseline_features,
431 .aarch64, .aarch64_be, .aarch64_32 => aarch64.cpu.generic.features,
432 .avr => avr.baseline_features,
433 .bpfel, .bpfeb => bpf.baseline_features,
434 .hexagon => hexagon.baseline_features,
435 .mips, .mipsel, .mips64, .mips64el => mips.baseline_features,
436 .msp430 => msp430.baseline_features,
437 .powerpc, .powerpc64, .powerpc64le => powerpc.baseline_features,
438 .amdgcn => amdgpu.baseline_features,
439 .riscv32, .riscv64 => riscv.baseline_features,
440 .sparc, .sparcv9, .sparcel => sparc.baseline_features,
441 .s390x => systemz.baseline_features,
442 .i386, .x86_64 => x86.baseline_features,
443 .nvptx, .nvptx64 => nvptx.baseline_features,
444 .wasm32, .wasm64 => wasm.baseline_features,
445
446 else => &[0]*const Cpu.Feature{},
447 };
448 }
449
450 /// All CPUs Zig is aware of, sorted lexicographically by name.
451 pub fn allCpus(arch: Arch) []const *const Cpu {
452 return switch (arch) {
453 .arm, .armeb, .thumb, .thumbeb => arm.all_cpus,
454 .aarch64, .aarch64_be, .aarch64_32 => aarch64.all_cpus,
455 .avr => avr.all_cpus,
456 .bpfel, .bpfeb => bpf.all_cpus,
457 .hexagon => hexagon.all_cpus,
458 .mips, .mipsel, .mips64, .mips64el => mips.all_cpus,
459 .msp430 => msp430.all_cpus,
460 .powerpc, .powerpc64, .powerpc64le => powerpc.all_cpus,
461 .amdgcn => amdgpu.all_cpus,
462 .riscv32, .riscv64 => riscv.all_cpus,
463 .sparc, .sparcv9, .sparcel => sparc.all_cpus,
464 .s390x => systemz.all_cpus,
465 .i386, .x86_64 => x86.all_cpus,
466 .nvptx, .nvptx64 => nvptx.all_cpus,
467 .wasm32, .wasm64 => wasm.all_cpus,
468
469 else => &[0]*const Cpu{},
470 };
471 }
299472 };
300473
301474 pub const Abi = enum {
......@@ -323,6 +496,28 @@ pub const Target = union(enum) {
323496 macabi,
324497 };
325498
499 pub const Cpu = struct {
500 name: []const u8,
501 llvm_name: ?[:0]const u8,
502 features: Feature.Set,
503
504 pub const Feature = struct {
505 /// The bit index into `Set`.
506 index: u8,
507 name: []const u8,
508 llvm_name: ?[:0]const u8,
509 description: []const u8,
510 dependencies: Set,
511
512 /// A bit set of all the features.
513 pub const Set = u128;
514
515 pub fn isEnabled(set: Set, arch_feature_index: u7) bool {
516 return (set & (@as(Set, 1) << arch_feature_index)) != 0;
517 }
518 };
519 };
520
326521 pub const ObjectFormat = enum {
327522 unknown,
328523 coff,
......@@ -346,6 +541,19 @@ pub const Target = union(enum) {
346541 arch: Arch,
347542 os: Os,
348543 abi: Abi,
544 cpu_features: CpuFeatures = .baseline,
545
546 pub const CpuFeatures = union(enum) {
547 /// The "default" set of CPU features for cross-compiling. A conservative set
548 /// of features that is expected to be supported on most available hardware.
549 baseline,
550
551 /// Target one specific CPU.
552 cpu: *const Cpu,
553
554 /// Explicitly provide the entire CPU feature set.
555 features: Cpu.Feature.Set,
556 };
349557 };
350558
351559 pub const current = Target{
......@@ -353,11 +561,20 @@ pub const Target = union(enum) {
353561 .arch = builtin.arch,
354562 .os = builtin.os,
355563 .abi = builtin.abi,
564 .cpu_features = builtin.cpu_features,
356565 },
357566 };
358567
359568 pub const stack_align = 16;
360569
570 pub fn cpuFeatures(self: Target) []const *const Cpu.Feature {
571 return switch (self.cpu_features) {
572 .baseline => self.arch.baselineFeatures(),
573 .cpu => |cpu| cpu.features,
574 .features => |features| features,
575 };
576 }
577
361578 pub fn zigTriple(self: Target, allocator: *mem.Allocator) ![]u8 {
362579 return std.fmt.allocPrint(allocator, "{}{}-{}-{}", .{
363580 @tagName(self.getArch()),
......@@ -496,7 +713,7 @@ pub const Target = union(enum) {
496713 pub fn parseArchSub(text: []const u8) ParseArchSubError!Arch {
497714 const info = @typeInfo(Arch);
498715 inline for (info.Union.fields) |field| {
499 if (text.len >= field.name.len and mem.eql(u8, text[0..field.name.len], field.name)) {
716 if (mem.eql(u8, text, field.name)) {
500717 if (field.field_type == void) {
501718 return @as(Arch, @field(Arch, field.name));
502719 } else {
......@@ -514,31 +731,6 @@ pub const Target = union(enum) {
514731 return error.UnknownArchitecture;
515732 }
516733
517 pub fn parseArchTag(text: []const u8) ParseArchSubError!@TagType(Arch) {
518 const info = @typeInfo(Arch);
519 inline for (info.Union.fields) |field| {
520 if (text.len >= field.name.len and mem.eql(u8, text[0..field.name.len], field.name)) {
521 if (text.len == field.name.len) return @as(@TagType(Arch), @field(Arch, field.name));
522
523 if (field.field_type == void) {
524 return error.UnknownArchitecture;
525 }
526
527 const sub_info = @typeInfo(field.field_type);
528 inline for (sub_info.Enum.fields) |sub_field| {
529 const combined = field.name ++ sub_field.name;
530 if (mem.eql(u8, text, combined)) {
531 return @as(@TagType(Arch), @field(Arch, field.name));
532 }
533 }
534
535 return error.UnknownSubArchitecture;
536 }
537 }
538
539 return error.UnknownArchitecture;
540 }
541
542734 pub fn parseOs(text: []const u8) !Os {
543735 const info = @typeInfo(Os);
544736 inline for (info.Enum.fields) |field| {
......@@ -841,83 +1033,3 @@ pub const Target = union(enum) {
8411033 return .unavailable;
8421034 }
8431035};
844
845pub const aarch64 = @import("target/aarch64.zig");
846pub const amdgpu = @import("target/amdgpu.zig");
847pub const arm = @import("target/arm.zig");
848pub const avr = @import("target/avr.zig");
849pub const bpf = @import("target/bpf.zig");
850pub const hexagon = @import("target/hexagon.zig");
851pub const mips = @import("target/mips.zig");
852pub const msp430 = @import("target/msp430.zig");
853pub const nvptx = @import("target/nvptx.zig");
854pub const powerpc = @import("target/powerpc.zig");
855pub const riscv = @import("target/riscv.zig");
856pub const sparc = @import("target/sparc.zig");
857pub const systemz = @import("target/systemz.zig");
858pub const wasm = @import("target/wasm.zig");
859pub const x86 = @import("target/x86.zig");
860
861pub const Feature = struct {
862 name: []const u8,
863 llvm_name: ?[]const u8,
864 description: []const u8,
865
866 dependencies: []*const Feature,
867};
868
869pub const Cpu = struct {
870 name: []const u8,
871 llvm_name: ?[]const u8,
872
873 dependencies: []*const Feature,
874};
875
876pub const TargetDetails = union(enum) {
877 cpu: *const Cpu,
878 features: []*const Feature,
879};
880
881pub fn getFeaturesForArch(arch: @TagType(Target.Arch)) []*const Feature {
882 return switch (arch) {
883 .arm, .armeb, .thumb, .thumbeb => arm.features,
884 .aarch64, .aarch64_be, .aarch64_32 => aarch64.features,
885 .avr => avr.features,
886 .bpfel, .bpfeb => bpf.features,
887 .hexagon => hexagon.features,
888 .mips, .mipsel, .mips64, .mips64el => mips.features,
889 .msp430 => msp430.features,
890 .powerpc, .powerpc64, .powerpc64le => powerpc.features,
891 .amdgcn => amdgpu.features,
892 .riscv32, .riscv64 => riscv.features,
893 .sparc, .sparcv9, .sparcel => sparc.features,
894 .s390x => systemz.features,
895 .i386, .x86_64 => x86.features,
896 .nvptx, .nvptx64 => nvptx.features,
897 .wasm32, .wasm64 => wasm.features,
898
899 else => &[_]*const Feature{},
900 };
901}
902
903pub fn getCpusForArch(arch: @TagType(Target.Arch)) []*const Cpu {
904 return switch (arch) {
905 .arm, .armeb, .thumb, .thumbeb => arm.cpus,
906 .aarch64, .aarch64_be, .aarch64_32 => aarch64.cpus,
907 .avr => avr.cpus,
908 .bpfel, .bpfeb => bpf.cpus,
909 .hexagon => hexagon.cpus,
910 .mips, .mipsel, .mips64, .mips64el => mips.cpus,
911 .msp430 => msp430.cpus,
912 .powerpc, .powerpc64, .powerpc64le => powerpc.cpus,
913 .amdgcn => amdgpu.cpus,
914 .riscv32, .riscv64 => riscv.cpus,
915 .sparc, .sparcv9, .sparcel => sparc.cpus,
916 .s390x => systemz.cpus,
917 .i386, .x86_64 => x86.cpus,
918 .nvptx, .nvptx64 => nvptx.cpus,
919 .wasm32, .wasm64 => wasm.cpus,
920
921 else => &[_]*const Cpu{},
922 };
923}
lib/std/target/aarch64.zig+1527-1602
......@@ -1,1603 +1,1528 @@
1const Feature = @import("std").target.Feature;
2const Cpu = @import("std").target.Cpu;
3
4pub const feature_aes = Feature{
5 .name = "aes",
6 .llvm_name = "aes",
7 .description = "Enable AES support",
8 .dependencies = &[_]*const Feature {
9 &feature_fpArmv8,
10 },
11};
12
13pub const feature_am = Feature{
14 .name = "am",
15 .llvm_name = "am",
16 .description = "Enable v8.4-A Activity Monitors extension",
17 .dependencies = &[_]*const Feature {
18 },
19};
20
21pub const feature_aggressiveFma = Feature{
22 .name = "aggressiveFma",
23 .llvm_name = "aggressive-fma",
24 .description = "Enable Aggressive FMA for floating-point.",
25 .dependencies = &[_]*const Feature {
26 },
27};
28
29pub const feature_altnzcv = Feature{
30 .name = "altnzcv",
31 .llvm_name = "altnzcv",
32 .description = "Enable alternative NZCV format for floating point comparisons",
33 .dependencies = &[_]*const Feature {
34 },
35};
36
37pub const feature_alternateSextloadCvtF32Pattern = Feature{
38 .name = "alternateSextloadCvtF32Pattern",
39 .llvm_name = "alternate-sextload-cvt-f32-pattern",
40 .description = "Use alternative pattern for sextload convert to f32",
41 .dependencies = &[_]*const Feature {
42 },
43};
44
45pub const feature_arithBccFusion = Feature{
46 .name = "arithBccFusion",
47 .llvm_name = "arith-bcc-fusion",
48 .description = "CPU fuses arithmetic+bcc operations",
49 .dependencies = &[_]*const Feature {
50 },
51};
52
53pub const feature_arithCbzFusion = Feature{
54 .name = "arithCbzFusion",
55 .llvm_name = "arith-cbz-fusion",
56 .description = "CPU fuses arithmetic + cbz/cbnz operations",
57 .dependencies = &[_]*const Feature {
58 },
59};
60
61pub const feature_balanceFpOps = Feature{
62 .name = "balanceFpOps",
63 .llvm_name = "balance-fp-ops",
64 .description = "balance mix of odd and even D-registers for fp multiply(-accumulate) ops",
65 .dependencies = &[_]*const Feature {
66 },
67};
68
69pub const feature_bti = Feature{
70 .name = "bti",
71 .llvm_name = "bti",
72 .description = "Enable Branch Target Identification",
73 .dependencies = &[_]*const Feature {
74 },
75};
76
77pub const feature_ccidx = Feature{
78 .name = "ccidx",
79 .llvm_name = "ccidx",
80 .description = "Enable v8.3-A Extend of the CCSIDR number of sets",
81 .dependencies = &[_]*const Feature {
82 },
83};
84
85pub const feature_ccpp = Feature{
86 .name = "ccpp",
87 .llvm_name = "ccpp",
88 .description = "Enable v8.2 data Cache Clean to Point of Persistence",
89 .dependencies = &[_]*const Feature {
90 },
91};
92
93pub const feature_crc = Feature{
94 .name = "crc",
95 .llvm_name = "crc",
96 .description = "Enable ARMv8 CRC-32 checksum instructions",
97 .dependencies = &[_]*const Feature {
98 },
99};
100
101pub const feature_ccdp = Feature{
102 .name = "ccdp",
103 .llvm_name = "ccdp",
104 .description = "Enable v8.5 Cache Clean to Point of Deep Persistence",
105 .dependencies = &[_]*const Feature {
106 },
107};
108
109pub const feature_callSavedX8 = Feature{
110 .name = "callSavedX8",
111 .llvm_name = "call-saved-x8",
112 .description = "Make X8 callee saved.",
113 .dependencies = &[_]*const Feature {
114 },
115};
116
117pub const feature_callSavedX9 = Feature{
118 .name = "callSavedX9",
119 .llvm_name = "call-saved-x9",
120 .description = "Make X9 callee saved.",
121 .dependencies = &[_]*const Feature {
122 },
123};
124
125pub const feature_callSavedX10 = Feature{
126 .name = "callSavedX10",
127 .llvm_name = "call-saved-x10",
128 .description = "Make X10 callee saved.",
129 .dependencies = &[_]*const Feature {
130 },
131};
132
133pub const feature_callSavedX11 = Feature{
134 .name = "callSavedX11",
135 .llvm_name = "call-saved-x11",
136 .description = "Make X11 callee saved.",
137 .dependencies = &[_]*const Feature {
138 },
139};
140
141pub const feature_callSavedX12 = Feature{
142 .name = "callSavedX12",
143 .llvm_name = "call-saved-x12",
144 .description = "Make X12 callee saved.",
145 .dependencies = &[_]*const Feature {
146 },
147};
148
149pub const feature_callSavedX13 = Feature{
150 .name = "callSavedX13",
151 .llvm_name = "call-saved-x13",
152 .description = "Make X13 callee saved.",
153 .dependencies = &[_]*const Feature {
154 },
155};
156
157pub const feature_callSavedX14 = Feature{
158 .name = "callSavedX14",
159 .llvm_name = "call-saved-x14",
160 .description = "Make X14 callee saved.",
161 .dependencies = &[_]*const Feature {
162 },
163};
164
165pub const feature_callSavedX15 = Feature{
166 .name = "callSavedX15",
167 .llvm_name = "call-saved-x15",
168 .description = "Make X15 callee saved.",
169 .dependencies = &[_]*const Feature {
170 },
171};
172
173pub const feature_callSavedX18 = Feature{
174 .name = "callSavedX18",
175 .llvm_name = "call-saved-x18",
176 .description = "Make X18 callee saved.",
177 .dependencies = &[_]*const Feature {
178 },
179};
180
181pub const feature_complxnum = Feature{
182 .name = "complxnum",
183 .llvm_name = "complxnum",
184 .description = "Enable v8.3-A Floating-point complex number support",
185 .dependencies = &[_]*const Feature {
186 &feature_fpArmv8,
187 },
188};
189
190pub const feature_crypto = Feature{
191 .name = "crypto",
192 .llvm_name = "crypto",
193 .description = "Enable cryptographic instructions",
194 .dependencies = &[_]*const Feature {
195 &feature_fpArmv8,
196 },
197};
198
199pub const feature_customCheapAsMove = Feature{
200 .name = "customCheapAsMove",
201 .llvm_name = "custom-cheap-as-move",
202 .description = "Use custom handling of cheap instructions",
203 .dependencies = &[_]*const Feature {
204 },
205};
206
207pub const feature_dit = Feature{
208 .name = "dit",
209 .llvm_name = "dit",
210 .description = "Enable v8.4-A Data Independent Timing instructions",
211 .dependencies = &[_]*const Feature {
212 },
213};
214
215pub const feature_disableLatencySchedHeuristic = Feature{
216 .name = "disableLatencySchedHeuristic",
217 .llvm_name = "disable-latency-sched-heuristic",
218 .description = "Disable latency scheduling heuristic",
219 .dependencies = &[_]*const Feature {
220 },
221};
222
223pub const feature_dotprod = Feature{
224 .name = "dotprod",
225 .llvm_name = "dotprod",
226 .description = "Enable dot product support",
227 .dependencies = &[_]*const Feature {
228 },
229};
230
231pub const feature_exynosCheapAsMove = Feature{
232 .name = "exynosCheapAsMove",
233 .llvm_name = "exynos-cheap-as-move",
234 .description = "Use Exynos specific handling of cheap instructions",
235 .dependencies = &[_]*const Feature {
236 &feature_customCheapAsMove,
237 },
238};
239
240pub const feature_fmi = Feature{
241 .name = "fmi",
242 .llvm_name = "fmi",
243 .description = "Enable v8.4-A Flag Manipulation Instructions",
244 .dependencies = &[_]*const Feature {
245 },
246};
247
248pub const feature_fp16fml = Feature{
249 .name = "fp16fml",
250 .llvm_name = "fp16fml",
251 .description = "Enable FP16 FML instructions",
252 .dependencies = &[_]*const Feature {
253 &feature_fpArmv8,
254 },
255};
256
257pub const feature_fpArmv8 = Feature{
258 .name = "fpArmv8",
259 .llvm_name = "fp-armv8",
260 .description = "Enable ARMv8 FP",
261 .dependencies = &[_]*const Feature {
262 },
263};
264
265pub const feature_fptoint = Feature{
266 .name = "fptoint",
267 .llvm_name = "fptoint",
268 .description = "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int",
269 .dependencies = &[_]*const Feature {
270 },
271};
272
273pub const feature_force32bitJumpTables = Feature{
274 .name = "force32bitJumpTables",
275 .llvm_name = "force-32bit-jump-tables",
276 .description = "Force jump table entries to be 32-bits wide except at MinSize",
277 .dependencies = &[_]*const Feature {
278 },
279};
280
281pub const feature_fullfp16 = Feature{
282 .name = "fullfp16",
283 .llvm_name = "fullfp16",
284 .description = "Full FP16",
285 .dependencies = &[_]*const Feature {
286 &feature_fpArmv8,
287 },
288};
289
290pub const feature_fuseAes = Feature{
291 .name = "fuseAes",
292 .llvm_name = "fuse-aes",
293 .description = "CPU fuses AES crypto operations",
294 .dependencies = &[_]*const Feature {
295 },
296};
297
298pub const feature_fuseAddress = Feature{
299 .name = "fuseAddress",
300 .llvm_name = "fuse-address",
301 .description = "CPU fuses address generation and memory operations",
302 .dependencies = &[_]*const Feature {
303 },
304};
305
306pub const feature_fuseArithLogic = Feature{
307 .name = "fuseArithLogic",
308 .llvm_name = "fuse-arith-logic",
309 .description = "CPU fuses arithmetic and logic operations",
310 .dependencies = &[_]*const Feature {
311 },
312};
313
314pub const feature_fuseCsel = Feature{
315 .name = "fuseCsel",
316 .llvm_name = "fuse-csel",
317 .description = "CPU fuses conditional select operations",
318 .dependencies = &[_]*const Feature {
319 },
320};
321
322pub const feature_fuseCryptoEor = Feature{
323 .name = "fuseCryptoEor",
324 .llvm_name = "fuse-crypto-eor",
325 .description = "CPU fuses AES/PMULL and EOR operations",
326 .dependencies = &[_]*const Feature {
327 },
328};
329
330pub const feature_fuseLiterals = Feature{
331 .name = "fuseLiterals",
332 .llvm_name = "fuse-literals",
333 .description = "CPU fuses literal generation operations",
334 .dependencies = &[_]*const Feature {
335 },
336};
337
338pub const feature_jsconv = Feature{
339 .name = "jsconv",
340 .llvm_name = "jsconv",
341 .description = "Enable v8.3-A JavaScript FP conversion enchancement",
342 .dependencies = &[_]*const Feature {
343 &feature_fpArmv8,
344 },
345};
346
347pub const feature_lor = Feature{
348 .name = "lor",
349 .llvm_name = "lor",
350 .description = "Enables ARM v8.1 Limited Ordering Regions extension",
351 .dependencies = &[_]*const Feature {
352 },
353};
354
355pub const feature_lse = Feature{
356 .name = "lse",
357 .llvm_name = "lse",
358 .description = "Enable ARMv8.1 Large System Extension (LSE) atomic instructions",
359 .dependencies = &[_]*const Feature {
360 },
361};
362
363pub const feature_lslFast = Feature{
364 .name = "lslFast",
365 .llvm_name = "lsl-fast",
366 .description = "CPU has a fastpath logical shift of up to 3 places",
367 .dependencies = &[_]*const Feature {
368 },
369};
370
371pub const feature_mpam = Feature{
372 .name = "mpam",
373 .llvm_name = "mpam",
374 .description = "Enable v8.4-A Memory system Partitioning and Monitoring extension",
375 .dependencies = &[_]*const Feature {
376 },
377};
378
379pub const feature_mte = Feature{
380 .name = "mte",
381 .llvm_name = "mte",
382 .description = "Enable Memory Tagging Extension",
383 .dependencies = &[_]*const Feature {
384 },
385};
386
387pub const feature_neon = Feature{
388 .name = "neon",
389 .llvm_name = "neon",
390 .description = "Enable Advanced SIMD instructions",
391 .dependencies = &[_]*const Feature {
392 &feature_fpArmv8,
393 },
394};
395
396pub const feature_nv = Feature{
397 .name = "nv",
398 .llvm_name = "nv",
399 .description = "Enable v8.4-A Nested Virtualization Enchancement",
400 .dependencies = &[_]*const Feature {
401 },
402};
403
404pub const feature_noNegImmediates = Feature{
405 .name = "noNegImmediates",
406 .llvm_name = "no-neg-immediates",
407 .description = "Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.",
408 .dependencies = &[_]*const Feature {
409 },
410};
411
412pub const feature_pa = Feature{
413 .name = "pa",
414 .llvm_name = "pa",
415 .description = "Enable v8.3-A Pointer Authentication enchancement",
416 .dependencies = &[_]*const Feature {
417 },
418};
419
420pub const feature_pan = Feature{
421 .name = "pan",
422 .llvm_name = "pan",
423 .description = "Enables ARM v8.1 Privileged Access-Never extension",
424 .dependencies = &[_]*const Feature {
425 },
426};
427
428pub const feature_panRwv = Feature{
429 .name = "panRwv",
430 .llvm_name = "pan-rwv",
431 .description = "Enable v8.2 PAN s1e1R and s1e1W Variants",
432 .dependencies = &[_]*const Feature {
433 &feature_pan,
434 },
435};
436
437pub const feature_perfmon = Feature{
438 .name = "perfmon",
439 .llvm_name = "perfmon",
440 .description = "Enable ARMv8 PMUv3 Performance Monitors extension",
441 .dependencies = &[_]*const Feature {
442 },
443};
444
445pub const feature_usePostraScheduler = Feature{
446 .name = "usePostraScheduler",
447 .llvm_name = "use-postra-scheduler",
448 .description = "Schedule again after register allocation",
449 .dependencies = &[_]*const Feature {
450 },
451};
452
453pub const feature_predres = Feature{
454 .name = "predres",
455 .llvm_name = "predres",
456 .description = "Enable v8.5a execution and data prediction invalidation instructions",
457 .dependencies = &[_]*const Feature {
458 },
459};
460
461pub const feature_predictableSelectExpensive = Feature{
462 .name = "predictableSelectExpensive",
463 .llvm_name = "predictable-select-expensive",
464 .description = "Prefer likely predicted branches over selects",
465 .dependencies = &[_]*const Feature {
466 },
467};
468
469pub const feature_uaops = Feature{
470 .name = "uaops",
471 .llvm_name = "uaops",
472 .description = "Enable v8.2 UAO PState",
473 .dependencies = &[_]*const Feature {
474 },
475};
476
477pub const feature_ras = Feature{
478 .name = "ras",
479 .llvm_name = "ras",
480 .description = "Enable ARMv8 Reliability, Availability and Serviceability Extensions",
481 .dependencies = &[_]*const Feature {
482 },
483};
484
485pub const feature_rasv8_4 = Feature{
486 .name = "rasv8_4",
487 .llvm_name = "rasv8_4",
488 .description = "Enable v8.4-A Reliability, Availability and Serviceability extension",
489 .dependencies = &[_]*const Feature {
490 &feature_ras,
491 },
492};
493
494pub const feature_rcpc = Feature{
495 .name = "rcpc",
496 .llvm_name = "rcpc",
497 .description = "Enable support for RCPC extension",
498 .dependencies = &[_]*const Feature {
499 },
500};
501
502pub const feature_rcpcImmo = Feature{
503 .name = "rcpcImmo",
504 .llvm_name = "rcpc-immo",
505 .description = "Enable v8.4-A RCPC instructions with Immediate Offsets",
506 .dependencies = &[_]*const Feature {
507 &feature_rcpc,
508 },
509};
510
511pub const feature_rdm = Feature{
512 .name = "rdm",
513 .llvm_name = "rdm",
514 .description = "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions",
515 .dependencies = &[_]*const Feature {
516 },
517};
518
519pub const feature_rand = Feature{
520 .name = "rand",
521 .llvm_name = "rand",
522 .description = "Enable Random Number generation instructions",
523 .dependencies = &[_]*const Feature {
524 },
525};
526
527pub const feature_reserveX1 = Feature{
528 .name = "reserveX1",
529 .llvm_name = "reserve-x1",
530 .description = "Reserve X1, making it unavailable as a GPR",
531 .dependencies = &[_]*const Feature {
532 },
533};
534
535pub const feature_reserveX2 = Feature{
536 .name = "reserveX2",
537 .llvm_name = "reserve-x2",
538 .description = "Reserve X2, making it unavailable as a GPR",
539 .dependencies = &[_]*const Feature {
540 },
541};
542
543pub const feature_reserveX3 = Feature{
544 .name = "reserveX3",
545 .llvm_name = "reserve-x3",
546 .description = "Reserve X3, making it unavailable as a GPR",
547 .dependencies = &[_]*const Feature {
548 },
549};
550
551pub const feature_reserveX4 = Feature{
552 .name = "reserveX4",
553 .llvm_name = "reserve-x4",
554 .description = "Reserve X4, making it unavailable as a GPR",
555 .dependencies = &[_]*const Feature {
556 },
557};
558
559pub const feature_reserveX5 = Feature{
560 .name = "reserveX5",
561 .llvm_name = "reserve-x5",
562 .description = "Reserve X5, making it unavailable as a GPR",
563 .dependencies = &[_]*const Feature {
564 },
565};
566
567pub const feature_reserveX6 = Feature{
568 .name = "reserveX6",
569 .llvm_name = "reserve-x6",
570 .description = "Reserve X6, making it unavailable as a GPR",
571 .dependencies = &[_]*const Feature {
572 },
573};
574
575pub const feature_reserveX7 = Feature{
576 .name = "reserveX7",
577 .llvm_name = "reserve-x7",
578 .description = "Reserve X7, making it unavailable as a GPR",
579 .dependencies = &[_]*const Feature {
580 },
581};
582
583pub const feature_reserveX9 = Feature{
584 .name = "reserveX9",
585 .llvm_name = "reserve-x9",
586 .description = "Reserve X9, making it unavailable as a GPR",
587 .dependencies = &[_]*const Feature {
588 },
589};
590
591pub const feature_reserveX10 = Feature{
592 .name = "reserveX10",
593 .llvm_name = "reserve-x10",
594 .description = "Reserve X10, making it unavailable as a GPR",
595 .dependencies = &[_]*const Feature {
596 },
597};
598
599pub const feature_reserveX11 = Feature{
600 .name = "reserveX11",
601 .llvm_name = "reserve-x11",
602 .description = "Reserve X11, making it unavailable as a GPR",
603 .dependencies = &[_]*const Feature {
604 },
605};
606
607pub const feature_reserveX12 = Feature{
608 .name = "reserveX12",
609 .llvm_name = "reserve-x12",
610 .description = "Reserve X12, making it unavailable as a GPR",
611 .dependencies = &[_]*const Feature {
612 },
613};
614
615pub const feature_reserveX13 = Feature{
616 .name = "reserveX13",
617 .llvm_name = "reserve-x13",
618 .description = "Reserve X13, making it unavailable as a GPR",
619 .dependencies = &[_]*const Feature {
620 },
621};
622
623pub const feature_reserveX14 = Feature{
624 .name = "reserveX14",
625 .llvm_name = "reserve-x14",
626 .description = "Reserve X14, making it unavailable as a GPR",
627 .dependencies = &[_]*const Feature {
628 },
629};
630
631pub const feature_reserveX15 = Feature{
632 .name = "reserveX15",
633 .llvm_name = "reserve-x15",
634 .description = "Reserve X15, making it unavailable as a GPR",
635 .dependencies = &[_]*const Feature {
636 },
637};
638
639pub const feature_reserveX18 = Feature{
640 .name = "reserveX18",
641 .llvm_name = "reserve-x18",
642 .description = "Reserve X18, making it unavailable as a GPR",
643 .dependencies = &[_]*const Feature {
644 },
645};
646
647pub const feature_reserveX20 = Feature{
648 .name = "reserveX20",
649 .llvm_name = "reserve-x20",
650 .description = "Reserve X20, making it unavailable as a GPR",
651 .dependencies = &[_]*const Feature {
652 },
653};
654
655pub const feature_reserveX21 = Feature{
656 .name = "reserveX21",
657 .llvm_name = "reserve-x21",
658 .description = "Reserve X21, making it unavailable as a GPR",
659 .dependencies = &[_]*const Feature {
660 },
661};
662
663pub const feature_reserveX22 = Feature{
664 .name = "reserveX22",
665 .llvm_name = "reserve-x22",
666 .description = "Reserve X22, making it unavailable as a GPR",
667 .dependencies = &[_]*const Feature {
668 },
669};
670
671pub const feature_reserveX23 = Feature{
672 .name = "reserveX23",
673 .llvm_name = "reserve-x23",
674 .description = "Reserve X23, making it unavailable as a GPR",
675 .dependencies = &[_]*const Feature {
676 },
677};
678
679pub const feature_reserveX24 = Feature{
680 .name = "reserveX24",
681 .llvm_name = "reserve-x24",
682 .description = "Reserve X24, making it unavailable as a GPR",
683 .dependencies = &[_]*const Feature {
684 },
685};
686
687pub const feature_reserveX25 = Feature{
688 .name = "reserveX25",
689 .llvm_name = "reserve-x25",
690 .description = "Reserve X25, making it unavailable as a GPR",
691 .dependencies = &[_]*const Feature {
692 },
693};
694
695pub const feature_reserveX26 = Feature{
696 .name = "reserveX26",
697 .llvm_name = "reserve-x26",
698 .description = "Reserve X26, making it unavailable as a GPR",
699 .dependencies = &[_]*const Feature {
700 },
701};
702
703pub const feature_reserveX27 = Feature{
704 .name = "reserveX27",
705 .llvm_name = "reserve-x27",
706 .description = "Reserve X27, making it unavailable as a GPR",
707 .dependencies = &[_]*const Feature {
708 },
709};
710
711pub const feature_reserveX28 = Feature{
712 .name = "reserveX28",
713 .llvm_name = "reserve-x28",
714 .description = "Reserve X28, making it unavailable as a GPR",
715 .dependencies = &[_]*const Feature {
716 },
717};
718
719pub const feature_sb = Feature{
720 .name = "sb",
721 .llvm_name = "sb",
722 .description = "Enable v8.5 Speculation Barrier",
723 .dependencies = &[_]*const Feature {
724 },
725};
726
727pub const feature_sel2 = Feature{
728 .name = "sel2",
729 .llvm_name = "sel2",
730 .description = "Enable v8.4-A Secure Exception Level 2 extension",
731 .dependencies = &[_]*const Feature {
732 },
733};
734
735pub const feature_sha2 = Feature{
736 .name = "sha2",
737 .llvm_name = "sha2",
738 .description = "Enable SHA1 and SHA256 support",
739 .dependencies = &[_]*const Feature {
740 &feature_fpArmv8,
741 },
742};
743
744pub const feature_sha3 = Feature{
745 .name = "sha3",
746 .llvm_name = "sha3",
747 .description = "Enable SHA512 and SHA3 support",
748 .dependencies = &[_]*const Feature {
749 &feature_fpArmv8,
750 },
751};
752
753pub const feature_sm4 = Feature{
754 .name = "sm4",
755 .llvm_name = "sm4",
756 .description = "Enable SM3 and SM4 support",
757 .dependencies = &[_]*const Feature {
758 &feature_fpArmv8,
759 },
760};
761
762pub const feature_spe = Feature{
763 .name = "spe",
764 .llvm_name = "spe",
765 .description = "Enable Statistical Profiling extension",
766 .dependencies = &[_]*const Feature {
767 },
768};
769
770pub const feature_ssbs = Feature{
771 .name = "ssbs",
772 .llvm_name = "ssbs",
773 .description = "Enable Speculative Store Bypass Safe bit",
774 .dependencies = &[_]*const Feature {
775 },
776};
777
778pub const feature_sve = Feature{
779 .name = "sve",
780 .llvm_name = "sve",
781 .description = "Enable Scalable Vector Extension (SVE) instructions",
782 .dependencies = &[_]*const Feature {
783 },
784};
785
786pub const feature_sve2 = Feature{
787 .name = "sve2",
788 .llvm_name = "sve2",
789 .description = "Enable Scalable Vector Extension 2 (SVE2) instructions",
790 .dependencies = &[_]*const Feature {
791 &feature_sve,
792 },
793};
794
795pub const feature_sve2Aes = Feature{
796 .name = "sve2Aes",
797 .llvm_name = "sve2-aes",
798 .description = "Enable AES SVE2 instructions",
799 .dependencies = &[_]*const Feature {
800 &feature_sve,
801 &feature_fpArmv8,
802 },
803};
804
805pub const feature_sve2Bitperm = Feature{
806 .name = "sve2Bitperm",
807 .llvm_name = "sve2-bitperm",
808 .description = "Enable bit permutation SVE2 instructions",
809 .dependencies = &[_]*const Feature {
810 &feature_sve,
811 },
812};
813
814pub const feature_sve2Sha3 = Feature{
815 .name = "sve2Sha3",
816 .llvm_name = "sve2-sha3",
817 .description = "Enable SHA3 SVE2 instructions",
818 .dependencies = &[_]*const Feature {
819 &feature_sve,
820 &feature_fpArmv8,
821 },
822};
823
824pub const feature_sve2Sm4 = Feature{
825 .name = "sve2Sm4",
826 .llvm_name = "sve2-sm4",
827 .description = "Enable SM4 SVE2 instructions",
828 .dependencies = &[_]*const Feature {
829 &feature_sve,
830 &feature_fpArmv8,
831 },
832};
833
834pub const feature_slowMisaligned128store = Feature{
835 .name = "slowMisaligned128store",
836 .llvm_name = "slow-misaligned-128store",
837 .description = "Misaligned 128 bit stores are slow",
838 .dependencies = &[_]*const Feature {
839 },
840};
841
842pub const feature_slowPaired128 = Feature{
843 .name = "slowPaired128",
844 .llvm_name = "slow-paired-128",
845 .description = "Paired 128 bit loads and stores are slow",
846 .dependencies = &[_]*const Feature {
847 },
848};
849
850pub const feature_slowStrqroStore = Feature{
851 .name = "slowStrqroStore",
852 .llvm_name = "slow-strqro-store",
853 .description = "STR of Q register with register offset is slow",
854 .dependencies = &[_]*const Feature {
855 },
856};
857
858pub const feature_specrestrict = Feature{
859 .name = "specrestrict",
860 .llvm_name = "specrestrict",
861 .description = "Enable architectural speculation restriction",
862 .dependencies = &[_]*const Feature {
863 },
864};
865
866pub const feature_strictAlign = Feature{
867 .name = "strictAlign",
868 .llvm_name = "strict-align",
869 .description = "Disallow all unaligned memory access",
870 .dependencies = &[_]*const Feature {
871 },
872};
873
874pub const feature_tlbRmi = Feature{
875 .name = "tlbRmi",
876 .llvm_name = "tlb-rmi",
877 .description = "Enable v8.4-A TLB Range and Maintenance Instructions",
878 .dependencies = &[_]*const Feature {
879 },
880};
881
882pub const feature_tracev84 = Feature{
883 .name = "tracev84",
884 .llvm_name = "tracev8.4",
885 .description = "Enable v8.4-A Trace extension",
886 .dependencies = &[_]*const Feature {
887 },
888};
889
890pub const feature_useAa = Feature{
891 .name = "useAa",
892 .llvm_name = "use-aa",
893 .description = "Use alias analysis during codegen",
894 .dependencies = &[_]*const Feature {
895 },
896};
897
898pub const feature_tpidrEl1 = Feature{
899 .name = "tpidrEl1",
900 .llvm_name = "tpidr-el1",
901 .description = "Permit use of TPIDR_EL1 for the TLS base",
902 .dependencies = &[_]*const Feature {
903 },
904};
905
906pub const feature_tpidrEl2 = Feature{
907 .name = "tpidrEl2",
908 .llvm_name = "tpidr-el2",
909 .description = "Permit use of TPIDR_EL2 for the TLS base",
910 .dependencies = &[_]*const Feature {
911 },
912};
913
914pub const feature_tpidrEl3 = Feature{
915 .name = "tpidrEl3",
916 .llvm_name = "tpidr-el3",
917 .description = "Permit use of TPIDR_EL3 for the TLS base",
918 .dependencies = &[_]*const Feature {
919 },
920};
921
922pub const feature_useReciprocalSquareRoot = Feature{
923 .name = "useReciprocalSquareRoot",
924 .llvm_name = "use-reciprocal-square-root",
925 .description = "Use the reciprocal square root approximation",
926 .dependencies = &[_]*const Feature {
927 },
928};
929
930pub const feature_vh = Feature{
931 .name = "vh",
932 .llvm_name = "vh",
933 .description = "Enables ARM v8.1 Virtual Host extension",
934 .dependencies = &[_]*const Feature {
935 },
936};
937
938pub const feature_zcm = Feature{
939 .name = "zcm",
940 .llvm_name = "zcm",
941 .description = "Has zero-cycle register moves",
942 .dependencies = &[_]*const Feature {
943 },
944};
945
946pub const feature_zcz = Feature{
947 .name = "zcz",
948 .llvm_name = "zcz",
949 .description = "Has zero-cycle zeroing instructions",
950 .dependencies = &[_]*const Feature {
951 &feature_zczFp,
952 &feature_zczGp,
953 },
954};
955
956pub const feature_zczFp = Feature{
957 .name = "zczFp",
958 .llvm_name = "zcz-fp",
959 .description = "Has zero-cycle zeroing instructions for FP registers",
960 .dependencies = &[_]*const Feature {
961 },
962};
963
964pub const feature_zczFpWorkaround = Feature{
965 .name = "zczFpWorkaround",
966 .llvm_name = "zcz-fp-workaround",
967 .description = "The zero-cycle floating-point zeroing instruction has a bug",
968 .dependencies = &[_]*const Feature {
969 },
970};
971
972pub const feature_zczGp = Feature{
973 .name = "zczGp",
974 .llvm_name = "zcz-gp",
975 .description = "Has zero-cycle zeroing instructions for generic registers",
976 .dependencies = &[_]*const Feature {
977 },
978};
979
980pub const features = &[_]*const Feature {
981 &feature_aes,
982 &feature_am,
983 &feature_aggressiveFma,
984 &feature_altnzcv,
985 &feature_alternateSextloadCvtF32Pattern,
986 &feature_arithBccFusion,
987 &feature_arithCbzFusion,
988 &feature_balanceFpOps,
989 &feature_bti,
990 &feature_ccidx,
991 &feature_ccpp,
992 &feature_crc,
993 &feature_ccdp,
994 &feature_callSavedX8,
995 &feature_callSavedX9,
996 &feature_callSavedX10,
997 &feature_callSavedX11,
998 &feature_callSavedX12,
999 &feature_callSavedX13,
1000 &feature_callSavedX14,
1001 &feature_callSavedX15,
1002 &feature_callSavedX18,
1003 &feature_complxnum,
1004 &feature_crypto,
1005 &feature_customCheapAsMove,
1006 &feature_dit,
1007 &feature_disableLatencySchedHeuristic,
1008 &feature_dotprod,
1009 &feature_exynosCheapAsMove,
1010 &feature_fmi,
1011 &feature_fp16fml,
1012 &feature_fpArmv8,
1013 &feature_fptoint,
1014 &feature_force32bitJumpTables,
1015 &feature_fullfp16,
1016 &feature_fuseAes,
1017 &feature_fuseAddress,
1018 &feature_fuseArithLogic,
1019 &feature_fuseCsel,
1020 &feature_fuseCryptoEor,
1021 &feature_fuseLiterals,
1022 &feature_jsconv,
1023 &feature_lor,
1024 &feature_lse,
1025 &feature_lslFast,
1026 &feature_mpam,
1027 &feature_mte,
1028 &feature_neon,
1029 &feature_nv,
1030 &feature_noNegImmediates,
1031 &feature_pa,
1032 &feature_pan,
1033 &feature_panRwv,
1034 &feature_perfmon,
1035 &feature_usePostraScheduler,
1036 &feature_predres,
1037 &feature_predictableSelectExpensive,
1038 &feature_uaops,
1039 &feature_ras,
1040 &feature_rasv8_4,
1041 &feature_rcpc,
1042 &feature_rcpcImmo,
1043 &feature_rdm,
1044 &feature_rand,
1045 &feature_reserveX1,
1046 &feature_reserveX2,
1047 &feature_reserveX3,
1048 &feature_reserveX4,
1049 &feature_reserveX5,
1050 &feature_reserveX6,
1051 &feature_reserveX7,
1052 &feature_reserveX9,
1053 &feature_reserveX10,
1054 &feature_reserveX11,
1055 &feature_reserveX12,
1056 &feature_reserveX13,
1057 &feature_reserveX14,
1058 &feature_reserveX15,
1059 &feature_reserveX18,
1060 &feature_reserveX20,
1061 &feature_reserveX21,
1062 &feature_reserveX22,
1063 &feature_reserveX23,
1064 &feature_reserveX24,
1065 &feature_reserveX25,
1066 &feature_reserveX26,
1067 &feature_reserveX27,
1068 &feature_reserveX28,
1069 &feature_sb,
1070 &feature_sel2,
1071 &feature_sha2,
1072 &feature_sha3,
1073 &feature_sm4,
1074 &feature_spe,
1075 &feature_ssbs,
1076 &feature_sve,
1077 &feature_sve2,
1078 &feature_sve2Aes,
1079 &feature_sve2Bitperm,
1080 &feature_sve2Sha3,
1081 &feature_sve2Sm4,
1082 &feature_slowMisaligned128store,
1083 &feature_slowPaired128,
1084 &feature_slowStrqroStore,
1085 &feature_specrestrict,
1086 &feature_strictAlign,
1087 &feature_tlbRmi,
1088 &feature_tracev84,
1089 &feature_useAa,
1090 &feature_tpidrEl1,
1091 &feature_tpidrEl2,
1092 &feature_tpidrEl3,
1093 &feature_useReciprocalSquareRoot,
1094 &feature_vh,
1095 &feature_zcm,
1096 &feature_zcz,
1097 &feature_zczFp,
1098 &feature_zczFpWorkaround,
1099 &feature_zczGp,
1100};
1101
1102pub const cpu_appleLatest = Cpu{
1103 .name = "appleLatest",
1104 .llvm_name = "apple-latest",
1105 .dependencies = &[_]*const Feature {
1106 &feature_arithCbzFusion,
1107 &feature_zczFpWorkaround,
1108 &feature_alternateSextloadCvtF32Pattern,
1109 &feature_fuseCryptoEor,
1110 &feature_zcm,
1111 &feature_zczGp,
1112 &feature_perfmon,
1113 &feature_disableLatencySchedHeuristic,
1114 &feature_fpArmv8,
1115 &feature_zczFp,
1116 &feature_arithBccFusion,
1117 &feature_fuseAes,
1118 },
1119};
1120
1121pub const cpu_cortexA35 = Cpu{
1122 .name = "cortexA35",
1123 .llvm_name = "cortex-a35",
1124 .dependencies = &[_]*const Feature {
1125 &feature_perfmon,
1126 &feature_fpArmv8,
1127 &feature_crc,
1128 },
1129};
1130
1131pub const cpu_cortexA53 = Cpu{
1132 .name = "cortexA53",
1133 .llvm_name = "cortex-a53",
1134 .dependencies = &[_]*const Feature {
1135 &feature_customCheapAsMove,
1136 &feature_crc,
1137 &feature_perfmon,
1138 &feature_useAa,
1139 &feature_fpArmv8,
1140 &feature_fuseAes,
1141 &feature_balanceFpOps,
1142 &feature_usePostraScheduler,
1143 },
1144};
1145
1146pub const cpu_cortexA55 = Cpu{
1147 .name = "cortexA55",
1148 .llvm_name = "cortex-a55",
1149 .dependencies = &[_]*const Feature {
1150 &feature_ccpp,
1151 &feature_rcpc,
1152 &feature_uaops,
1153 &feature_rdm,
1154 &feature_ras,
1155 &feature_lse,
1156 &feature_crc,
1157 &feature_perfmon,
1158 &feature_fpArmv8,
1159 &feature_vh,
1160 &feature_fuseAes,
1161 &feature_lor,
1162 &feature_dotprod,
1163 &feature_pan,
1164 },
1165};
1166
1167pub const cpu_cortexA57 = Cpu{
1168 .name = "cortexA57",
1169 .llvm_name = "cortex-a57",
1170 .dependencies = &[_]*const Feature {
1171 &feature_fuseLiterals,
1172 &feature_predictableSelectExpensive,
1173 &feature_customCheapAsMove,
1174 &feature_crc,
1175 &feature_perfmon,
1176 &feature_fpArmv8,
1177 &feature_fuseAes,
1178 &feature_balanceFpOps,
1179 &feature_usePostraScheduler,
1180 },
1181};
1182
1183pub const cpu_cortexA72 = Cpu{
1184 .name = "cortexA72",
1185 .llvm_name = "cortex-a72",
1186 .dependencies = &[_]*const Feature {
1187 &feature_fuseAes,
1188 &feature_fpArmv8,
1189 &feature_perfmon,
1190 &feature_crc,
1191 },
1192};
1193
1194pub const cpu_cortexA73 = Cpu{
1195 .name = "cortexA73",
1196 .llvm_name = "cortex-a73",
1197 .dependencies = &[_]*const Feature {
1198 &feature_fuseAes,
1199 &feature_fpArmv8,
1200 &feature_perfmon,
1201 &feature_crc,
1202 },
1203};
1204
1205pub const cpu_cortexA75 = Cpu{
1206 .name = "cortexA75",
1207 .llvm_name = "cortex-a75",
1208 .dependencies = &[_]*const Feature {
1209 &feature_ccpp,
1210 &feature_rcpc,
1211 &feature_uaops,
1212 &feature_rdm,
1213 &feature_ras,
1214 &feature_lse,
1215 &feature_crc,
1216 &feature_perfmon,
1217 &feature_fpArmv8,
1218 &feature_vh,
1219 &feature_fuseAes,
1220 &feature_lor,
1221 &feature_dotprod,
1222 &feature_pan,
1223 },
1224};
1225
1226pub const cpu_cortexA76 = Cpu{
1227 .name = "cortexA76",
1228 .llvm_name = "cortex-a76",
1229 .dependencies = &[_]*const Feature {
1230 &feature_ccpp,
1231 &feature_rcpc,
1232 &feature_uaops,
1233 &feature_rdm,
1234 &feature_ras,
1235 &feature_lse,
1236 &feature_crc,
1237 &feature_fpArmv8,
1238 &feature_vh,
1239 &feature_lor,
1240 &feature_ssbs,
1241 &feature_dotprod,
1242 &feature_pan,
1243 },
1244};
1245
1246pub const cpu_cortexA76ae = Cpu{
1247 .name = "cortexA76ae",
1248 .llvm_name = "cortex-a76ae",
1249 .dependencies = &[_]*const Feature {
1250 &feature_ccpp,
1251 &feature_rcpc,
1252 &feature_uaops,
1253 &feature_rdm,
1254 &feature_ras,
1255 &feature_lse,
1256 &feature_crc,
1257 &feature_fpArmv8,
1258 &feature_vh,
1259 &feature_lor,
1260 &feature_ssbs,
1261 &feature_dotprod,
1262 &feature_pan,
1263 },
1264};
1265
1266pub const cpu_cyclone = Cpu{
1267 .name = "cyclone",
1268 .llvm_name = "cyclone",
1269 .dependencies = &[_]*const Feature {
1270 &feature_arithCbzFusion,
1271 &feature_zczFpWorkaround,
1272 &feature_alternateSextloadCvtF32Pattern,
1273 &feature_fuseCryptoEor,
1274 &feature_zcm,
1275 &feature_zczGp,
1276 &feature_perfmon,
1277 &feature_disableLatencySchedHeuristic,
1278 &feature_fpArmv8,
1279 &feature_zczFp,
1280 &feature_arithBccFusion,
1281 &feature_fuseAes,
1282 },
1283};
1284
1285pub const cpu_exynosM1 = Cpu{
1286 .name = "exynosM1",
1287 .llvm_name = "exynos-m1",
1288 .dependencies = &[_]*const Feature {
1289 &feature_customCheapAsMove,
1290 &feature_crc,
1291 &feature_force32bitJumpTables,
1292 &feature_perfmon,
1293 &feature_slowMisaligned128store,
1294 &feature_useReciprocalSquareRoot,
1295 &feature_fpArmv8,
1296 &feature_zczFp,
1297 &feature_fuseAes,
1298 &feature_slowPaired128,
1299 &feature_usePostraScheduler,
1300 },
1301};
1302
1303pub const cpu_exynosM2 = Cpu{
1304 .name = "exynosM2",
1305 .llvm_name = "exynos-m2",
1306 .dependencies = &[_]*const Feature {
1307 &feature_customCheapAsMove,
1308 &feature_crc,
1309 &feature_force32bitJumpTables,
1310 &feature_perfmon,
1311 &feature_slowMisaligned128store,
1312 &feature_fpArmv8,
1313 &feature_zczFp,
1314 &feature_fuseAes,
1315 &feature_slowPaired128,
1316 &feature_usePostraScheduler,
1317 },
1318};
1319
1320pub const cpu_exynosM3 = Cpu{
1321 .name = "exynosM3",
1322 .llvm_name = "exynos-m3",
1323 .dependencies = &[_]*const Feature {
1324 &feature_fuseLiterals,
1325 &feature_predictableSelectExpensive,
1326 &feature_customCheapAsMove,
1327 &feature_crc,
1328 &feature_force32bitJumpTables,
1329 &feature_fuseAddress,
1330 &feature_fuseCsel,
1331 &feature_perfmon,
1332 &feature_fpArmv8,
1333 &feature_zczFp,
1334 &feature_fuseAes,
1335 &feature_lslFast,
1336 &feature_usePostraScheduler,
1337 },
1338};
1339
1340pub const cpu_exynosM4 = Cpu{
1341 .name = "exynosM4",
1342 .llvm_name = "exynos-m4",
1343 .dependencies = &[_]*const Feature {
1344 &feature_arithCbzFusion,
1345 &feature_customCheapAsMove,
1346 &feature_lse,
1347 &feature_zczFp,
1348 &feature_lslFast,
1349 &feature_lor,
1350 &feature_fuseLiterals,
1351 &feature_ccpp,
1352 &feature_ras,
1353 &feature_fpArmv8,
1354 &feature_fuseAes,
1355 &feature_pan,
1356 &feature_fuseArithLogic,
1357 &feature_crc,
1358 &feature_force32bitJumpTables,
1359 &feature_fuseAddress,
1360 &feature_fuseCsel,
1361 &feature_arithBccFusion,
1362 &feature_uaops,
1363 &feature_rdm,
1364 &feature_zczGp,
1365 &feature_perfmon,
1366 &feature_vh,
1367 &feature_usePostraScheduler,
1368 &feature_dotprod,
1369 },
1370};
1371
1372pub const cpu_exynosM5 = Cpu{
1373 .name = "exynosM5",
1374 .llvm_name = "exynos-m5",
1375 .dependencies = &[_]*const Feature {
1376 &feature_arithCbzFusion,
1377 &feature_customCheapAsMove,
1378 &feature_lse,
1379 &feature_zczFp,
1380 &feature_lslFast,
1381 &feature_lor,
1382 &feature_fuseLiterals,
1383 &feature_ccpp,
1384 &feature_ras,
1385 &feature_fpArmv8,
1386 &feature_fuseAes,
1387 &feature_pan,
1388 &feature_fuseArithLogic,
1389 &feature_crc,
1390 &feature_force32bitJumpTables,
1391 &feature_fuseAddress,
1392 &feature_fuseCsel,
1393 &feature_arithBccFusion,
1394 &feature_uaops,
1395 &feature_rdm,
1396 &feature_zczGp,
1397 &feature_perfmon,
1398 &feature_vh,
1399 &feature_usePostraScheduler,
1400 &feature_dotprod,
1401 },
1402};
1403
1404pub const cpu_falkor = Cpu{
1405 .name = "falkor",
1406 .llvm_name = "falkor",
1407 .dependencies = &[_]*const Feature {
1408 &feature_predictableSelectExpensive,
1409 &feature_customCheapAsMove,
1410 &feature_rdm,
1411 &feature_slowStrqroStore,
1412 &feature_zczGp,
1413 &feature_crc,
1414 &feature_perfmon,
1415 &feature_fpArmv8,
1416 &feature_zczFp,
1417 &feature_lslFast,
1418 &feature_usePostraScheduler,
1419 },
1420};
1421
1422pub const cpu_generic = Cpu{
1423 .name = "generic",
1424 .llvm_name = "generic",
1425 .dependencies = &[_]*const Feature {
1426 &feature_fpArmv8,
1427 &feature_fuseAes,
1428 &feature_neon,
1429 &feature_perfmon,
1430 &feature_usePostraScheduler,
1431 },
1432};
1433
1434pub const cpu_kryo = Cpu{
1435 .name = "kryo",
1436 .llvm_name = "kryo",
1437 .dependencies = &[_]*const Feature {
1438 &feature_predictableSelectExpensive,
1439 &feature_customCheapAsMove,
1440 &feature_zczGp,
1441 &feature_crc,
1442 &feature_perfmon,
1443 &feature_fpArmv8,
1444 &feature_zczFp,
1445 &feature_lslFast,
1446 &feature_usePostraScheduler,
1447 },
1448};
1449
1450pub const cpu_saphira = Cpu{
1451 .name = "saphira",
1452 .llvm_name = "saphira",
1453 .dependencies = &[_]*const Feature {
1454 &feature_predictableSelectExpensive,
1455 &feature_customCheapAsMove,
1456 &feature_fmi,
1457 &feature_lse,
1458 &feature_zczFp,
1459 &feature_lslFast,
1460 &feature_lor,
1461 &feature_dit,
1462 &feature_pa,
1463 &feature_ccpp,
1464 &feature_sel2,
1465 &feature_ras,
1466 &feature_fpArmv8,
1467 &feature_ccidx,
1468 &feature_pan,
1469 &feature_rcpc,
1470 &feature_crc,
1471 &feature_tracev84,
1472 &feature_mpam,
1473 &feature_am,
1474 &feature_nv,
1475 &feature_tlbRmi,
1476 &feature_uaops,
1477 &feature_rdm,
1478 &feature_zczGp,
1479 &feature_perfmon,
1480 &feature_vh,
1481 &feature_usePostraScheduler,
1482 &feature_dotprod,
1483 &feature_spe,
1484 },
1485};
1486
1487pub const cpu_thunderx = Cpu{
1488 .name = "thunderx",
1489 .llvm_name = "thunderx",
1490 .dependencies = &[_]*const Feature {
1491 &feature_predictableSelectExpensive,
1492 &feature_crc,
1493 &feature_perfmon,
1494 &feature_fpArmv8,
1495 &feature_usePostraScheduler,
1496 },
1497};
1498
1499pub const cpu_thunderx2t99 = Cpu{
1500 .name = "thunderx2t99",
1501 .llvm_name = "thunderx2t99",
1502 .dependencies = &[_]*const Feature {
1503 &feature_predictableSelectExpensive,
1504 &feature_aggressiveFma,
1505 &feature_rdm,
1506 &feature_lse,
1507 &feature_crc,
1508 &feature_fpArmv8,
1509 &feature_vh,
1510 &feature_arithBccFusion,
1511 &feature_lor,
1512 &feature_usePostraScheduler,
1513 &feature_pan,
1514 },
1515};
1516
1517pub const cpu_thunderxt81 = Cpu{
1518 .name = "thunderxt81",
1519 .llvm_name = "thunderxt81",
1520 .dependencies = &[_]*const Feature {
1521 &feature_predictableSelectExpensive,
1522 &feature_crc,
1523 &feature_perfmon,
1524 &feature_fpArmv8,
1525 &feature_usePostraScheduler,
1526 },
1527};
1528
1529pub const cpu_thunderxt83 = Cpu{
1530 .name = "thunderxt83",
1531 .llvm_name = "thunderxt83",
1532 .dependencies = &[_]*const Feature {
1533 &feature_predictableSelectExpensive,
1534 &feature_crc,
1535 &feature_perfmon,
1536 &feature_fpArmv8,
1537 &feature_usePostraScheduler,
1538 },
1539};
1540
1541pub const cpu_thunderxt88 = Cpu{
1542 .name = "thunderxt88",
1543 .llvm_name = "thunderxt88",
1544 .dependencies = &[_]*const Feature {
1545 &feature_predictableSelectExpensive,
1546 &feature_crc,
1547 &feature_perfmon,
1548 &feature_fpArmv8,
1549 &feature_usePostraScheduler,
1550 },
1551};
1552
1553pub const cpu_tsv110 = Cpu{
1554 .name = "tsv110",
1555 .llvm_name = "tsv110",
1556 .dependencies = &[_]*const Feature {
1557 &feature_ccpp,
1558 &feature_customCheapAsMove,
1559 &feature_uaops,
1560 &feature_rdm,
1561 &feature_ras,
1562 &feature_lse,
1563 &feature_crc,
1564 &feature_perfmon,
1565 &feature_fpArmv8,
1566 &feature_vh,
1567 &feature_fuseAes,
1568 &feature_lor,
1569 &feature_usePostraScheduler,
1570 &feature_dotprod,
1571 &feature_pan,
1572 &feature_spe,
1573 },
1574};
1575
1576pub const cpus = &[_]*const Cpu {
1577 &cpu_appleLatest,
1578 &cpu_cortexA35,
1579 &cpu_cortexA53,
1580 &cpu_cortexA55,
1581 &cpu_cortexA57,
1582 &cpu_cortexA72,
1583 &cpu_cortexA73,
1584 &cpu_cortexA75,
1585 &cpu_cortexA76,
1586 &cpu_cortexA76ae,
1587 &cpu_cyclone,
1588 &cpu_exynosM1,
1589 &cpu_exynosM2,
1590 &cpu_exynosM3,
1591 &cpu_exynosM4,
1592 &cpu_exynosM5,
1593 &cpu_falkor,
1594 &cpu_generic,
1595 &cpu_kryo,
1596 &cpu_saphira,
1597 &cpu_thunderx,
1598 &cpu_thunderx2t99,
1599 &cpu_thunderxt81,
1600 &cpu_thunderxt83,
1601 &cpu_thunderxt88,
1602 &cpu_tsv110,
1const std = @import("../std.zig");
2const Cpu = std.Target.Cpu;
3
4pub const Feature = enum {
5 aes,
6 am,
7 aggressive_fma,
8 altnzcv,
9 alternate_sextload_cvt_f32_pattern,
10 arith_bcc_fusion,
11 arith_cbz_fusion,
12 balance_fp_ops,
13 bti,
14 ccidx,
15 ccpp,
16 crc,
17 ccdp,
18 call_saved_x8,
19 call_saved_x9,
20 call_saved_x10,
21 call_saved_x11,
22 call_saved_x12,
23 call_saved_x13,
24 call_saved_x14,
25 call_saved_x15,
26 call_saved_x18,
27 complxnum,
28 crypto,
29 custom_cheap_as_move,
30 dit,
31 disable_latency_sched_heuristic,
32 dotprod,
33 exynos_cheap_as_move,
34 fmi,
35 fp16fml,
36 fp_armv8,
37 fptoint,
38 force_32bit_jump_tables,
39 fullfp16,
40 fuse_aes,
41 fuse_address,
42 fuse_arith_logic,
43 fuse_csel,
44 fuse_crypto_eor,
45 fuse_literals,
46 jsconv,
47 lor,
48 lse,
49 lsl_fast,
50 mpam,
51 mte,
52 neon,
53 nv,
54 no_neg_immediates,
55 pa,
56 pan,
57 pan_rwv,
58 perfmon,
59 use_postra_scheduler,
60 predres,
61 predictable_select_expensive,
62 uaops,
63 ras,
64 rasv8_4,
65 rcpc,
66 rcpc_immo,
67 rdm,
68 rand,
69 reserve_x1,
70 reserve_x2,
71 reserve_x3,
72 reserve_x4,
73 reserve_x5,
74 reserve_x6,
75 reserve_x7,
76 reserve_x9,
77 reserve_x10,
78 reserve_x11,
79 reserve_x12,
80 reserve_x13,
81 reserve_x14,
82 reserve_x15,
83 reserve_x18,
84 reserve_x20,
85 reserve_x21,
86 reserve_x22,
87 reserve_x23,
88 reserve_x24,
89 reserve_x25,
90 reserve_x26,
91 reserve_x27,
92 reserve_x28,
93 sb,
94 sel2,
95 sha2,
96 sha3,
97 sm4,
98 spe,
99 ssbs,
100 sve,
101 sve2,
102 sve2_aes,
103 sve2_bitperm,
104 sve2_sha3,
105 sve2_sm4,
106 slow_misaligned_128store,
107 slow_paired_128,
108 slow_strqro_store,
109 specrestrict,
110 strict_align,
111 tlb_rmi,
112 tracev84,
113 use_aa,
114 tpidr_el1,
115 tpidr_el2,
116 tpidr_el3,
117 use_reciprocal_square_root,
118 vh,
119 zcm,
120 zcz,
121 zcz_fp,
122 zcz_fp_workaround,
123 zcz_gp,
124};
125
126pub fn featureSet(features: []const Feature) Cpu.Feature.Set {
127 var x: Cpu.Feature.Set = 0;
128 for (features) |feature| {
129 x |= 1 << @enumToInt(feature);
130 }
131 return x;
132}
133
134pub fn featureSetHas(set: Feature.Set, feature: Feature) bool {
135 return (set & (1 << @enumToInt(feature))) != 0;
136}
137
138pub const all_features = blk: {
139 const len = @typeInfo(Feature).Enum.fields.len;
140 std.debug.assert(len <= @typeInfo(Feature.Set).Int.bits);
141 var result: [len]Cpu.Feature = undefined;
142 result[@enumToInt(Feature.aes)] = .{
143 .index = @enumToInt(Feature.aes),
144 .name = @tagName(Feature.aes),
145 .llvm_name = "aes",
146 .description = "Enable AES support",
147 .dependencies = featureSet(&[_]Feature{
148 .fp_armv8,
149 }),
150 };
151 result[@enumToInt(Feature.am)] = .{
152 .index = @enumToInt(Feature.am),
153 .name = @tagName(Feature.am),
154 .llvm_name = "am",
155 .description = "Enable v8.4-A Activity Monitors extension",
156 .dependencies = 0,
157 };
158 result[@enumToInt(Feature.aggressive_fma)] = .{
159 .index = @enumToInt(Feature.aggressive_fma),
160 .name = @tagName(Feature.aggressive_fma),
161 .llvm_name = "aggressive-fma",
162 .description = "Enable Aggressive FMA for floating-point.",
163 .dependencies = 0,
164 };
165 result[@enumToInt(Feature.altnzcv)] = .{
166 .index = @enumToInt(Feature.altnzcv),
167 .name = @tagName(Feature.altnzcv),
168 .llvm_name = "altnzcv",
169 .description = "Enable alternative NZCV format for floating point comparisons",
170 .dependencies = 0,
171 };
172 result[@enumToInt(Feature.alternate_sextload_cvt_f32_pattern)] = .{
173 .index = @enumToInt(Feature.alternate_sextload_cvt_f32_pattern),
174 .name = @tagName(Feature.alternate_sextload_cvt_f32_pattern),
175 .llvm_name = "alternate-sextload-cvt-f32-pattern",
176 .description = "Use alternative pattern for sextload convert to f32",
177 .dependencies = 0,
178 };
179 result[@enumToInt(Feature.arith_bcc_fusion)] = .{
180 .index = @enumToInt(Feature.arith_bcc_fusion),
181 .name = @tagName(Feature.arith_bcc_fusion),
182 .llvm_name = "arith-bcc-fusion",
183 .description = "CPU fuses arithmetic+bcc operations",
184 .dependencies = 0,
185 };
186 result[@enumToInt(Feature.arith_cbz_fusion)] = .{
187 .index = @enumToInt(Feature.arith_cbz_fusion),
188 .name = @tagName(Feature.arith_cbz_fusion),
189 .llvm_name = "arith-cbz-fusion",
190 .description = "CPU fuses arithmetic + cbz/cbnz operations",
191 .dependencies = 0,
192 };
193 result[@enumToInt(Feature.balance_fp_ops)] = .{
194 .index = @enumToInt(Feature.balance_fp_ops),
195 .name = @tagName(Feature.balance_fp_ops),
196 .llvm_name = "balance-fp-ops",
197 .description = "balance mix of odd and even D-registers for fp multiply(-accumulate) ops",
198 .dependencies = 0,
199 };
200 result[@enumToInt(Feature.bti)] = .{
201 .index = @enumToInt(Feature.bti),
202 .name = @tagName(Feature.bti),
203 .llvm_name = "bti",
204 .description = "Enable Branch Target Identification",
205 .dependencies = 0,
206 };
207 result[@enumToInt(Feature.ccidx)] = .{
208 .index = @enumToInt(Feature.ccidx),
209 .name = @tagName(Feature.ccidx),
210 .llvm_name = "ccidx",
211 .description = "Enable v8.3-A Extend of the CCSIDR number of sets",
212 .dependencies = 0,
213 };
214 result[@enumToInt(Feature.ccpp)] = .{
215 .index = @enumToInt(Feature.ccpp),
216 .name = @tagName(Feature.ccpp),
217 .llvm_name = "ccpp",
218 .description = "Enable v8.2 data Cache Clean to Point of Persistence",
219 .dependencies = 0,
220 };
221 result[@enumToInt(Feature.crc)] = .{
222 .index = @enumToInt(Feature.crc),
223 .name = @tagName(Feature.crc),
224 .llvm_name = "crc",
225 .description = "Enable ARMv8 CRC-32 checksum instructions",
226 .dependencies = 0,
227 };
228 result[@enumToInt(Feature.ccdp)] = .{
229 .index = @enumToInt(Feature.ccdp),
230 .name = @tagName(Feature.ccdp),
231 .llvm_name = "ccdp",
232 .description = "Enable v8.5 Cache Clean to Point of Deep Persistence",
233 .dependencies = 0,
234 };
235 result[@enumToInt(Feature.call_saved_x8)] = .{
236 .index = @enumToInt(Feature.call_saved_x8),
237 .name = @tagName(Feature.call_saved_x8),
238 .llvm_name = "call-saved-x8",
239 .description = "Make X8 callee saved.",
240 .dependencies = 0,
241 };
242 result[@enumToInt(Feature.call_saved_x9)] = .{
243 .index = @enumToInt(Feature.call_saved_x9),
244 .name = @tagName(Feature.call_saved_x9),
245 .llvm_name = "call-saved-x9",
246 .description = "Make X9 callee saved.",
247 .dependencies = 0,
248 };
249 result[@enumToInt(Feature.call_saved_x10)] = .{
250 .index = @enumToInt(Feature.call_saved_x10),
251 .name = @tagName(Feature.call_saved_x10),
252 .llvm_name = "call-saved-x10",
253 .description = "Make X10 callee saved.",
254 .dependencies = 0,
255 };
256 result[@enumToInt(Feature.call_saved_x11)] = .{
257 .index = @enumToInt(Feature.call_saved_x11),
258 .name = @tagName(Feature.call_saved_x11),
259 .llvm_name = "call-saved-x11",
260 .description = "Make X11 callee saved.",
261 .dependencies = 0,
262 };
263 result[@enumToInt(Feature.call_saved_x12)] = .{
264 .index = @enumToInt(Feature.call_saved_x12),
265 .name = @tagName(Feature.call_saved_x12),
266 .llvm_name = "call-saved-x12",
267 .description = "Make X12 callee saved.",
268 .dependencies = 0,
269 };
270 result[@enumToInt(Feature.call_saved_x13)] = .{
271 .index = @enumToInt(Feature.call_saved_x13),
272 .name = @tagName(Feature.call_saved_x13),
273 .llvm_name = "call-saved-x13",
274 .description = "Make X13 callee saved.",
275 .dependencies = 0,
276 };
277 result[@enumToInt(Feature.call_saved_x14)] = .{
278 .index = @enumToInt(Feature.call_saved_x14),
279 .name = @tagName(Feature.call_saved_x14),
280 .llvm_name = "call-saved-x14",
281 .description = "Make X14 callee saved.",
282 .dependencies = 0,
283 };
284 result[@enumToInt(Feature.call_saved_x15)] = .{
285 .index = @enumToInt(Feature.call_saved_x15),
286 .name = @tagName(Feature.call_saved_x15),
287 .llvm_name = "call-saved-x15",
288 .description = "Make X15 callee saved.",
289 .dependencies = 0,
290 };
291 result[@enumToInt(Feature.call_saved_x18)] = .{
292 .index = @enumToInt(Feature.call_saved_x18),
293 .name = @tagName(Feature.call_saved_x18),
294 .llvm_name = "call-saved-x18",
295 .description = "Make X18 callee saved.",
296 .dependencies = 0,
297 };
298 result[@enumToInt(Feature.complxnum)] = .{
299 .index = @enumToInt(Feature.complxnum),
300 .name = @tagName(Feature.complxnum),
301 .llvm_name = "complxnum",
302 .description = "Enable v8.3-A Floating-point complex number support",
303 .dependencies = featureSet(&[_]Feature{
304 .fp_armv8,
305 }),
306 };
307 result[@enumToInt(Feature.crypto)] = .{
308 .index = @enumToInt(Feature.crypto),
309 .name = @tagName(Feature.crypto),
310 .llvm_name = "crypto",
311 .description = "Enable cryptographic instructions",
312 .dependencies = featureSet(&[_]Feature{
313 .fp_armv8,
314 }),
315 };
316 result[@enumToInt(Feature.custom_cheap_as_move)] = .{
317 .index = @enumToInt(Feature.custom_cheap_as_move),
318 .name = @tagName(Feature.custom_cheap_as_move),
319 .llvm_name = "custom-cheap-as-move",
320 .description = "Use custom handling of cheap instructions",
321 .dependencies = 0,
322 };
323 result[@enumToInt(Feature.dit)] = .{
324 .index = @enumToInt(Feature.dit),
325 .name = @tagName(Feature.dit),
326 .llvm_name = "dit",
327 .description = "Enable v8.4-A Data Independent Timing instructions",
328 .dependencies = 0,
329 };
330 result[@enumToInt(Feature.disable_latency_sched_heuristic)] = .{
331 .index = @enumToInt(Feature.disable_latency_sched_heuristic),
332 .name = @tagName(Feature.disable_latency_sched_heuristic),
333 .llvm_name = "disable-latency-sched-heuristic",
334 .description = "Disable latency scheduling heuristic",
335 .dependencies = 0,
336 };
337 result[@enumToInt(Feature.dotprod)] = .{
338 .index = @enumToInt(Feature.dotprod),
339 .name = @tagName(Feature.dotprod),
340 .llvm_name = "dotprod",
341 .description = "Enable dot product support",
342 .dependencies = 0,
343 };
344 result[@enumToInt(Feature.exynos_cheap_as_move)] = .{
345 .index = @enumToInt(Feature.exynos_cheap_as_move),
346 .name = @tagName(Feature.exynos_cheap_as_move),
347 .llvm_name = "exynos-cheap-as-move",
348 .description = "Use Exynos specific handling of cheap instructions",
349 .dependencies = featureSet(&[_]Feature{
350 .custom_cheap_as_move,
351 }),
352 };
353 result[@enumToInt(Feature.fmi)] = .{
354 .index = @enumToInt(Feature.fmi),
355 .name = @tagName(Feature.fmi),
356 .llvm_name = "fmi",
357 .description = "Enable v8.4-A Flag Manipulation Instructions",
358 .dependencies = 0,
359 };
360 result[@enumToInt(Feature.fp16fml)] = .{
361 .index = @enumToInt(Feature.fp16fml),
362 .name = @tagName(Feature.fp16fml),
363 .llvm_name = "fp16fml",
364 .description = "Enable FP16 FML instructions",
365 .dependencies = featureSet(&[_]Feature{
366 .fp_armv8,
367 }),
368 };
369 result[@enumToInt(Feature.fp_armv8)] = .{
370 .index = @enumToInt(Feature.fp_armv8),
371 .name = @tagName(Feature.fp_armv8),
372 .llvm_name = "fp-armv8",
373 .description = "Enable ARMv8 FP",
374 .dependencies = 0,
375 };
376 result[@enumToInt(Feature.fptoint)] = .{
377 .index = @enumToInt(Feature.fptoint),
378 .name = @tagName(Feature.fptoint),
379 .llvm_name = "fptoint",
380 .description = "Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int",
381 .dependencies = 0,
382 };
383 result[@enumToInt(Feature.force_32bit_jump_tables)] = .{
384 .index = @enumToInt(Feature.force_32bit_jump_tables),
385 .name = @tagName(Feature.force_32bit_jump_tables),
386 .llvm_name = "force-32bit-jump-tables",
387 .description = "Force jump table entries to be 32-bits wide except at MinSize",
388 .dependencies = 0,
389 };
390 result[@enumToInt(Feature.fullfp16)] = .{
391 .index = @enumToInt(Feature.fullfp16),
392 .name = @tagName(Feature.fullfp16),
393 .llvm_name = "fullfp16",
394 .description = "Full FP16",
395 .dependencies = featureSet(&[_]Feature{
396 .fp_armv8,
397 }),
398 };
399 result[@enumToInt(Feature.fuse_aes)] = .{
400 .index = @enumToInt(Feature.fuse_aes),
401 .name = @tagName(Feature.fuse_aes),
402 .llvm_name = "fuse-aes",
403 .description = "CPU fuses AES crypto operations",
404 .dependencies = 0,
405 };
406 result[@enumToInt(Feature.fuse_address)] = .{
407 .index = @enumToInt(Feature.fuse_address),
408 .name = @tagName(Feature.fuse_address),
409 .llvm_name = "fuse-address",
410 .description = "CPU fuses address generation and memory operations",
411 .dependencies = 0,
412 };
413 result[@enumToInt(Feature.fuse_arith_logic)] = .{
414 .index = @enumToInt(Feature.fuse_arith_logic),
415 .name = @tagName(Feature.fuse_arith_logic),
416 .llvm_name = "fuse-arith-logic",
417 .description = "CPU fuses arithmetic and logic operations",
418 .dependencies = 0,
419 };
420 result[@enumToInt(Feature.fuse_csel)] = .{
421 .index = @enumToInt(Feature.fuse_csel),
422 .name = @tagName(Feature.fuse_csel),
423 .llvm_name = "fuse-csel",
424 .description = "CPU fuses conditional select operations",
425 .dependencies = 0,
426 };
427 result[@enumToInt(Feature.fuse_crypto_eor)] = .{
428 .index = @enumToInt(Feature.fuse_crypto_eor),
429 .name = @tagName(Feature.fuse_crypto_eor),
430 .llvm_name = "fuse-crypto-eor",
431 .description = "CPU fuses AES/PMULL and EOR operations",
432 .dependencies = 0,
433 };
434 result[@enumToInt(Feature.fuse_literals)] = .{
435 .index = @enumToInt(Feature.fuse_literals),
436 .name = @tagName(Feature.fuse_literals),
437 .llvm_name = "fuse-literals",
438 .description = "CPU fuses literal generation operations",
439 .dependencies = 0,
440 };
441 result[@enumToInt(Feature.jsconv)] = .{
442 .index = @enumToInt(Feature.jsconv),
443 .name = @tagName(Feature.jsconv),
444 .llvm_name = "jsconv",
445 .description = "Enable v8.3-A JavaScript FP conversion enchancement",
446 .dependencies = featureSet(&[_]Feature{
447 .fp_armv8,
448 }),
449 };
450 result[@enumToInt(Feature.lor)] = .{
451 .index = @enumToInt(Feature.lor),
452 .name = @tagName(Feature.lor),
453 .llvm_name = "lor",
454 .description = "Enables ARM v8.1 Limited Ordering Regions extension",
455 .dependencies = 0,
456 };
457 result[@enumToInt(Feature.lse)] = .{
458 .index = @enumToInt(Feature.lse),
459 .name = @tagName(Feature.lse),
460 .llvm_name = "lse",
461 .description = "Enable ARMv8.1 Large System Extension (LSE) atomic instructions",
462 .dependencies = 0,
463 };
464 result[@enumToInt(Feature.lsl_fast)] = .{
465 .index = @enumToInt(Feature.lsl_fast),
466 .name = @tagName(Feature.lsl_fast),
467 .llvm_name = "lsl-fast",
468 .description = "CPU has a fastpath logical shift of up to 3 places",
469 .dependencies = 0,
470 };
471 result[@enumToInt(Feature.mpam)] = .{
472 .index = @enumToInt(Feature.mpam),
473 .name = @tagName(Feature.mpam),
474 .llvm_name = "mpam",
475 .description = "Enable v8.4-A Memory system Partitioning and Monitoring extension",
476 .dependencies = 0,
477 };
478 result[@enumToInt(Feature.mte)] = .{
479 .index = @enumToInt(Feature.mte),
480 .name = @tagName(Feature.mte),
481 .llvm_name = "mte",
482 .description = "Enable Memory Tagging Extension",
483 .dependencies = 0,
484 };
485 result[@enumToInt(Feature.neon)] = .{
486 .index = @enumToInt(Feature.neon),
487 .name = @tagName(Feature.neon),
488 .llvm_name = "neon",
489 .description = "Enable Advanced SIMD instructions",
490 .dependencies = featureSet(&[_]Feature{
491 .fp_armv8,
492 }),
493 };
494 result[@enumToInt(Feature.nv)] = .{
495 .index = @enumToInt(Feature.nv),
496 .name = @tagName(Feature.nv),
497 .llvm_name = "nv",
498 .description = "Enable v8.4-A Nested Virtualization Enchancement",
499 .dependencies = 0,
500 };
501 result[@enumToInt(Feature.no_neg_immediates)] = .{
502 .index = @enumToInt(Feature.no_neg_immediates),
503 .name = @tagName(Feature.no_neg_immediates),
504 .llvm_name = "no-neg-immediates",
505 .description = "Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.",
506 .dependencies = 0,
507 };
508 result[@enumToInt(Feature.pa)] = .{
509 .index = @enumToInt(Feature.pa),
510 .name = @tagName(Feature.pa),
511 .llvm_name = "pa",
512 .description = "Enable v8.3-A Pointer Authentication enchancement",
513 .dependencies = 0,
514 };
515 result[@enumToInt(Feature.pan)] = .{
516 .index = @enumToInt(Feature.pan),
517 .name = @tagName(Feature.pan),
518 .llvm_name = "pan",
519 .description = "Enables ARM v8.1 Privileged Access-Never extension",
520 .dependencies = 0,
521 };
522 result[@enumToInt(Feature.pan_rwv)] = .{
523 .index = @enumToInt(Feature.pan_rwv),
524 .name = @tagName(Feature.pan_rwv),
525 .llvm_name = "pan-rwv",
526 .description = "Enable v8.2 PAN s1e1R and s1e1W Variants",
527 .dependencies = featureSet(&[_]Feature{
528 .pan,
529 }),
530 };
531 result[@enumToInt(Feature.perfmon)] = .{
532 .index = @enumToInt(Feature.perfmon),
533 .name = @tagName(Feature.perfmon),
534 .llvm_name = "perfmon",
535 .description = "Enable ARMv8 PMUv3 Performance Monitors extension",
536 .dependencies = 0,
537 };
538 result[@enumToInt(Feature.use_postra_scheduler)] = .{
539 .index = @enumToInt(Feature.use_postra_scheduler),
540 .name = @tagName(Feature.use_postra_scheduler),
541 .llvm_name = "use-postra-scheduler",
542 .description = "Schedule again after register allocation",
543 .dependencies = 0,
544 };
545 result[@enumToInt(Feature.predres)] = .{
546 .index = @enumToInt(Feature.predres),
547 .name = @tagName(Feature.predres),
548 .llvm_name = "predres",
549 .description = "Enable v8.5a execution and data prediction invalidation instructions",
550 .dependencies = 0,
551 };
552 result[@enumToInt(Feature.predictable_select_expensive)] = .{
553 .index = @enumToInt(Feature.predictable_select_expensive),
554 .name = @tagName(Feature.predictable_select_expensive),
555 .llvm_name = "predictable-select-expensive",
556 .description = "Prefer likely predicted branches over selects",
557 .dependencies = 0,
558 };
559 result[@enumToInt(Feature.uaops)] = .{
560 .index = @enumToInt(Feature.uaops),
561 .name = @tagName(Feature.uaops),
562 .llvm_name = "uaops",
563 .description = "Enable v8.2 UAO PState",
564 .dependencies = 0,
565 };
566 result[@enumToInt(Feature.ras)] = .{
567 .index = @enumToInt(Feature.ras),
568 .name = @tagName(Feature.ras),
569 .llvm_name = "ras",
570 .description = "Enable ARMv8 Reliability, Availability and Serviceability Extensions",
571 .dependencies = 0,
572 };
573 result[@enumToInt(Feature.rasv8_4)] = .{
574 .index = @enumToInt(Feature.rasv8_4),
575 .name = @tagName(Feature.rasv8_4),
576 .llvm_name = "rasv8_4",
577 .description = "Enable v8.4-A Reliability, Availability and Serviceability extension",
578 .dependencies = featureSet(&[_]Feature{
579 .ras,
580 }),
581 };
582 result[@enumToInt(Feature.rcpc)] = .{
583 .index = @enumToInt(Feature.rcpc),
584 .name = @tagName(Feature.rcpc),
585 .llvm_name = "rcpc",
586 .description = "Enable support for RCPC extension",
587 .dependencies = 0,
588 };
589 result[@enumToInt(Feature.rcpc_immo)] = .{
590 .index = @enumToInt(Feature.rcpc_immo),
591 .name = @tagName(Feature.rcpc_immo),
592 .llvm_name = "rcpc-immo",
593 .description = "Enable v8.4-A RCPC instructions with Immediate Offsets",
594 .dependencies = featureSet(&[_]Feature{
595 .rcpc,
596 }),
597 };
598 result[@enumToInt(Feature.rdm)] = .{
599 .index = @enumToInt(Feature.rdm),
600 .name = @tagName(Feature.rdm),
601 .llvm_name = "rdm",
602 .description = "Enable ARMv8.1 Rounding Double Multiply Add/Subtract instructions",
603 .dependencies = 0,
604 };
605 result[@enumToInt(Feature.rand)] = .{
606 .index = @enumToInt(Feature.rand),
607 .name = @tagName(Feature.rand),
608 .llvm_name = "rand",
609 .description = "Enable Random Number generation instructions",
610 .dependencies = 0,
611 };
612 result[@enumToInt(Feature.reserve_x1)] = .{
613 .index = @enumToInt(Feature.reserve_x1),
614 .name = @tagName(Feature.reserve_x1),
615 .llvm_name = "reserve-x1",
616 .description = "Reserve X1, making it unavailable as a GPR",
617 .dependencies = 0,
618 };
619 result[@enumToInt(Feature.reserve_x2)] = .{
620 .index = @enumToInt(Feature.reserve_x2),
621 .name = @tagName(Feature.reserve_x2),
622 .llvm_name = "reserve-x2",
623 .description = "Reserve X2, making it unavailable as a GPR",
624 .dependencies = 0,
625 };
626 result[@enumToInt(Feature.reserve_x3)] = .{
627 .index = @enumToInt(Feature.reserve_x3),
628 .name = @tagName(Feature.reserve_x3),
629 .llvm_name = "reserve-x3",
630 .description = "Reserve X3, making it unavailable as a GPR",
631 .dependencies = 0,
632 };
633 result[@enumToInt(Feature.reserve_x4)] = .{
634 .index = @enumToInt(Feature.reserve_x4),
635 .name = @tagName(Feature.reserve_x4),
636 .llvm_name = "reserve-x4",
637 .description = "Reserve X4, making it unavailable as a GPR",
638 .dependencies = 0,
639 };
640 result[@enumToInt(Feature.reserve_x5)] = .{
641 .index = @enumToInt(Feature.reserve_x5),
642 .name = @tagName(Feature.reserve_x5),
643 .llvm_name = "reserve-x5",
644 .description = "Reserve X5, making it unavailable as a GPR",
645 .dependencies = 0,
646 };
647 result[@enumToInt(Feature.reserve_x6)] = .{
648 .index = @enumToInt(Feature.reserve_x6),
649 .name = @tagName(Feature.reserve_x6),
650 .llvm_name = "reserve-x6",
651 .description = "Reserve X6, making it unavailable as a GPR",
652 .dependencies = 0,
653 };
654 result[@enumToInt(Feature.reserve_x7)] = .{
655 .index = @enumToInt(Feature.reserve_x7),
656 .name = @tagName(Feature.reserve_x7),
657 .llvm_name = "reserve-x7",
658 .description = "Reserve X7, making it unavailable as a GPR",
659 .dependencies = 0,
660 };
661 result[@enumToInt(Feature.reserve_x9)] = .{
662 .index = @enumToInt(Feature.reserve_x9),
663 .name = @tagName(Feature.reserve_x9),
664 .llvm_name = "reserve-x9",
665 .description = "Reserve X9, making it unavailable as a GPR",
666 .dependencies = 0,
667 };
668 result[@enumToInt(Feature.reserve_x10)] = .{
669 .index = @enumToInt(Feature.reserve_x10),
670 .name = @tagName(Feature.reserve_x10),
671 .llvm_name = "reserve-x10",
672 .description = "Reserve X10, making it unavailable as a GPR",
673 .dependencies = 0,
674 };
675 result[@enumToInt(Feature.reserve_x11)] = .{
676 .index = @enumToInt(Feature.reserve_x11),
677 .name = @tagName(Feature.reserve_x11),
678 .llvm_name = "reserve-x11",
679 .description = "Reserve X11, making it unavailable as a GPR",
680 .dependencies = 0,
681 };
682 result[@enumToInt(Feature.reserve_x12)] = .{
683 .index = @enumToInt(Feature.reserve_x12),
684 .name = @tagName(Feature.reserve_x12),
685 .llvm_name = "reserve-x12",
686 .description = "Reserve X12, making it unavailable as a GPR",
687 .dependencies = 0,
688 };
689 result[@enumToInt(Feature.reserve_x13)] = .{
690 .index = @enumToInt(Feature.reserve_x13),
691 .name = @tagName(Feature.reserve_x13),
692 .llvm_name = "reserve-x13",
693 .description = "Reserve X13, making it unavailable as a GPR",
694 .dependencies = 0,
695 };
696 result[@enumToInt(Feature.reserve_x14)] = .{
697 .index = @enumToInt(Feature.reserve_x14),
698 .name = @tagName(Feature.reserve_x14),
699 .llvm_name = "reserve-x14",
700 .description = "Reserve X14, making it unavailable as a GPR",
701 .dependencies = 0,
702 };
703 result[@enumToInt(Feature.reserve_x15)] = .{
704 .index = @enumToInt(Feature.reserve_x15),
705 .name = @tagName(Feature.reserve_x15),
706 .llvm_name = "reserve-x15",
707 .description = "Reserve X15, making it unavailable as a GPR",
708 .dependencies = 0,
709 };
710 result[@enumToInt(Feature.reserve_x18)] = .{
711 .index = @enumToInt(Feature.reserve_x18),
712 .name = @tagName(Feature.reserve_x18),
713 .llvm_name = "reserve-x18",
714 .description = "Reserve X18, making it unavailable as a GPR",
715 .dependencies = 0,
716 };
717 result[@enumToInt(Feature.reserve_x20)] = .{
718 .index = @enumToInt(Feature.reserve_x20),
719 .name = @tagName(Feature.reserve_x20),
720 .llvm_name = "reserve-x20",
721 .description = "Reserve X20, making it unavailable as a GPR",
722 .dependencies = 0,
723 };
724 result[@enumToInt(Feature.reserve_x21)] = .{
725 .index = @enumToInt(Feature.reserve_x21),
726 .name = @tagName(Feature.reserve_x21),
727 .llvm_name = "reserve-x21",
728 .description = "Reserve X21, making it unavailable as a GPR",
729 .dependencies = 0,
730 };
731 result[@enumToInt(Feature.reserve_x22)] = .{
732 .index = @enumToInt(Feature.reserve_x22),
733 .name = @tagName(Feature.reserve_x22),
734 .llvm_name = "reserve-x22",
735 .description = "Reserve X22, making it unavailable as a GPR",
736 .dependencies = 0,
737 };
738 result[@enumToInt(Feature.reserve_x23)] = .{
739 .index = @enumToInt(Feature.reserve_x23),
740 .name = @tagName(Feature.reserve_x23),
741 .llvm_name = "reserve-x23",
742 .description = "Reserve X23, making it unavailable as a GPR",
743 .dependencies = 0,
744 };
745 result[@enumToInt(Feature.reserve_x24)] = .{
746 .index = @enumToInt(Feature.reserve_x24),
747 .name = @tagName(Feature.reserve_x24),
748 .llvm_name = "reserve-x24",
749 .description = "Reserve X24, making it unavailable as a GPR",
750 .dependencies = 0,
751 };
752 result[@enumToInt(Feature.reserve_x25)] = .{
753 .index = @enumToInt(Feature.reserve_x25),
754 .name = @tagName(Feature.reserve_x25),
755 .llvm_name = "reserve-x25",
756 .description = "Reserve X25, making it unavailable as a GPR",
757 .dependencies = 0,
758 };
759 result[@enumToInt(Feature.reserve_x26)] = .{
760 .index = @enumToInt(Feature.reserve_x26),
761 .name = @tagName(Feature.reserve_x26),
762 .llvm_name = "reserve-x26",
763 .description = "Reserve X26, making it unavailable as a GPR",
764 .dependencies = 0,
765 };
766 result[@enumToInt(Feature.reserve_x27)] = .{
767 .index = @enumToInt(Feature.reserve_x27),
768 .name = @tagName(Feature.reserve_x27),
769 .llvm_name = "reserve-x27",
770 .description = "Reserve X27, making it unavailable as a GPR",
771 .dependencies = 0,
772 };
773 result[@enumToInt(Feature.reserve_x28)] = .{
774 .index = @enumToInt(Feature.reserve_x28),
775 .name = @tagName(Feature.reserve_x28),
776 .llvm_name = "reserve-x28",
777 .description = "Reserve X28, making it unavailable as a GPR",
778 .dependencies = 0,
779 };
780 result[@enumToInt(Feature.sb)] = .{
781 .index = @enumToInt(Feature.sb),
782 .name = @tagName(Feature.sb),
783 .llvm_name = "sb",
784 .description = "Enable v8.5 Speculation Barrier",
785 .dependencies = 0,
786 };
787 result[@enumToInt(Feature.sel2)] = .{
788 .index = @enumToInt(Feature.sel2),
789 .name = @tagName(Feature.sel2),
790 .llvm_name = "sel2",
791 .description = "Enable v8.4-A Secure Exception Level 2 extension",
792 .dependencies = 0,
793 };
794 result[@enumToInt(Feature.sha2)] = .{
795 .index = @enumToInt(Feature.sha2),
796 .name = @tagName(Feature.sha2),
797 .llvm_name = "sha2",
798 .description = "Enable SHA1 and SHA256 support",
799 .dependencies = featureSet(&[_]Feature{
800 .fp_armv8,
801 }),
802 };
803 result[@enumToInt(Feature.sha3)] = .{
804 .index = @enumToInt(Feature.sha3),
805 .name = @tagName(Feature.sha3),
806 .llvm_name = "sha3",
807 .description = "Enable SHA512 and SHA3 support",
808 .dependencies = featureSet(&[_]Feature{
809 .fp_armv8,
810 }),
811 };
812 result[@enumToInt(Feature.sm4)] = .{
813 .index = @enumToInt(Feature.sm4),
814 .name = @tagName(Feature.sm4),
815 .llvm_name = "sm4",
816 .description = "Enable SM3 and SM4 support",
817 .dependencies = featureSet(&[_]Feature{
818 .fp_armv8,
819 }),
820 };
821 result[@enumToInt(Feature.spe)] = .{
822 .index = @enumToInt(Feature.spe),
823 .name = @tagName(Feature.spe),
824 .llvm_name = "spe",
825 .description = "Enable Statistical Profiling extension",
826 .dependencies = 0,
827 };
828 result[@enumToInt(Feature.ssbs)] = .{
829 .index = @enumToInt(Feature.ssbs),
830 .name = @tagName(Feature.ssbs),
831 .llvm_name = "ssbs",
832 .description = "Enable Speculative Store Bypass Safe bit",
833 .dependencies = 0,
834 };
835 result[@enumToInt(Feature.sve)] = .{
836 .index = @enumToInt(Feature.sve),
837 .name = @tagName(Feature.sve),
838 .llvm_name = "sve",
839 .description = "Enable Scalable Vector Extension (SVE) instructions",
840 .dependencies = 0,
841 };
842 result[@enumToInt(Feature.sve2)] = .{
843 .index = @enumToInt(Feature.sve2),
844 .name = @tagName(Feature.sve2),
845 .llvm_name = "sve2",
846 .description = "Enable Scalable Vector Extension 2 (SVE2) instructions",
847 .dependencies = featureSet(&[_]Feature{
848 .sve,
849 }),
850 };
851 result[@enumToInt(Feature.sve2_aes)] = .{
852 .index = @enumToInt(Feature.sve2_aes),
853 .name = @tagName(Feature.sve2_aes),
854 .llvm_name = "sve2-aes",
855 .description = "Enable AES SVE2 instructions",
856 .dependencies = featureSet(&[_]Feature{
857 .sve,
858 .fp_armv8,
859 }),
860 };
861 result[@enumToInt(Feature.sve2_bitperm)] = .{
862 .index = @enumToInt(Feature.sve2_bitperm),
863 .name = @tagName(Feature.sve2_bitperm),
864 .llvm_name = "sve2-bitperm",
865 .description = "Enable bit permutation SVE2 instructions",
866 .dependencies = featureSet(&[_]Feature{
867 .sve,
868 }),
869 };
870 result[@enumToInt(Feature.sve2_sha3)] = .{
871 .index = @enumToInt(Feature.sve2_sha3),
872 .name = @tagName(Feature.sve2_sha3),
873 .llvm_name = "sve2-sha3",
874 .description = "Enable SHA3 SVE2 instructions",
875 .dependencies = featureSet(&[_]Feature{
876 .sve,
877 .fp_armv8,
878 }),
879 };
880 result[@enumToInt(Feature.sve2_sm4)] = .{
881 .index = @enumToInt(Feature.sve2_sm4),
882 .name = @tagName(Feature.sve2_sm4),
883 .llvm_name = "sve2-sm4",
884 .description = "Enable SM4 SVE2 instructions",
885 .dependencies = featureSet(&[_]Feature{
886 .sve,
887 .fp_armv8,
888 }),
889 };
890 result[@enumToInt(Feature.slow_misaligned_128store)] = .{
891 .index = @enumToInt(Feature.slow_misaligned_128store),
892 .name = @tagName(Feature.slow_misaligned_128store),
893 .llvm_name = "slow-misaligned-128store",
894 .description = "Misaligned 128 bit stores are slow",
895 .dependencies = 0,
896 };
897 result[@enumToInt(Feature.slow_paired_128)] = .{
898 .index = @enumToInt(Feature.slow_paired_128),
899 .name = @tagName(Feature.slow_paired_128),
900 .llvm_name = "slow-paired-128",
901 .description = "Paired 128 bit loads and stores are slow",
902 .dependencies = 0,
903 };
904 result[@enumToInt(Feature.slow_strqro_store)] = .{
905 .index = @enumToInt(Feature.slow_strqro_store),
906 .name = @tagName(Feature.slow_strqro_store),
907 .llvm_name = "slow-strqro-store",
908 .description = "STR of Q register with register offset is slow",
909 .dependencies = 0,
910 };
911 result[@enumToInt(Feature.specrestrict)] = .{
912 .index = @enumToInt(Feature.specrestrict),
913 .name = @tagName(Feature.specrestrict),
914 .llvm_name = "specrestrict",
915 .description = "Enable architectural speculation restriction",
916 .dependencies = 0,
917 };
918 result[@enumToInt(Feature.strict_align)] = .{
919 .index = @enumToInt(Feature.strict_align),
920 .name = @tagName(Feature.strict_align),
921 .llvm_name = "strict-align",
922 .description = "Disallow all unaligned memory access",
923 .dependencies = 0,
924 };
925 result[@enumToInt(Feature.tlb_rmi)] = .{
926 .index = @enumToInt(Feature.tlb_rmi),
927 .name = @tagName(Feature.tlb_rmi),
928 .llvm_name = "tlb-rmi",
929 .description = "Enable v8.4-A TLB Range and Maintenance Instructions",
930 .dependencies = 0,
931 };
932 result[@enumToInt(Feature.tracev84)] = .{
933 .index = @enumToInt(Feature.tracev84),
934 .name = @tagName(Feature.tracev84),
935 .llvm_name = "tracev8.4",
936 .description = "Enable v8.4-A Trace extension",
937 .dependencies = 0,
938 };
939 result[@enumToInt(Feature.use_aa)] = .{
940 .index = @enumToInt(Feature.use_aa),
941 .name = @tagName(Feature.use_aa),
942 .llvm_name = "use-aa",
943 .description = "Use alias analysis during codegen",
944 .dependencies = 0,
945 };
946 result[@enumToInt(Feature.tpidr_el1)] = .{
947 .index = @enumToInt(Feature.tpidr_el1),
948 .name = @tagName(Feature.tpidr_el1),
949 .llvm_name = "tpidr-el1",
950 .description = "Permit use of TPIDR_EL1 for the TLS base",
951 .dependencies = 0,
952 };
953 result[@enumToInt(Feature.tpidr_el2)] = .{
954 .index = @enumToInt(Feature.tpidr_el2),
955 .name = @tagName(Feature.tpidr_el2),
956 .llvm_name = "tpidr-el2",
957 .description = "Permit use of TPIDR_EL2 for the TLS base",
958 .dependencies = 0,
959 };
960 result[@enumToInt(Feature.tpidr_el3)] = .{
961 .index = @enumToInt(Feature.tpidr_el3),
962 .name = @tagName(Feature.tpidr_el3),
963 .llvm_name = "tpidr-el3",
964 .description = "Permit use of TPIDR_EL3 for the TLS base",
965 .dependencies = 0,
966 };
967 result[@enumToInt(Feature.use_reciprocal_square_root)] = .{
968 .index = @enumToInt(Feature.use_reciprocal_square_root),
969 .name = @tagName(Feature.use_reciprocal_square_root),
970 .llvm_name = "use-reciprocal-square-root",
971 .description = "Use the reciprocal square root approximation",
972 .dependencies = 0,
973 };
974 result[@enumToInt(Feature.vh)] = .{
975 .index = @enumToInt(Feature.vh),
976 .name = @tagName(Feature.vh),
977 .llvm_name = "vh",
978 .description = "Enables ARM v8.1 Virtual Host extension",
979 .dependencies = 0,
980 };
981 result[@enumToInt(Feature.zcm)] = .{
982 .index = @enumToInt(Feature.zcm),
983 .name = @tagName(Feature.zcm),
984 .llvm_name = "zcm",
985 .description = "Has zero-cycle register moves",
986 .dependencies = 0,
987 };
988 result[@enumToInt(Feature.zcz)] = .{
989 .index = @enumToInt(Feature.zcz),
990 .name = @tagName(Feature.zcz),
991 .llvm_name = "zcz",
992 .description = "Has zero-cycle zeroing instructions",
993 .dependencies = featureSet(&[_]Feature{
994 .zcz_fp,
995 .zcz_gp,
996 }),
997 };
998 result[@enumToInt(Feature.zcz_fp)] = .{
999 .index = @enumToInt(Feature.zcz_fp),
1000 .name = @tagName(Feature.zcz_fp),
1001 .llvm_name = "zcz-fp",
1002 .description = "Has zero-cycle zeroing instructions for FP registers",
1003 .dependencies = 0,
1004 };
1005 result[@enumToInt(Feature.zcz_fp_workaround)] = .{
1006 .index = @enumToInt(Feature.zcz_fp_workaround),
1007 .name = @tagName(Feature.zcz_fp_workaround),
1008 .llvm_name = "zcz-fp-workaround",
1009 .description = "The zero-cycle floating-point zeroing instruction has a bug",
1010 .dependencies = 0,
1011 };
1012 result[@enumToInt(Feature.zcz_gp)] = .{
1013 .index = @enumToInt(Feature.zcz_gp),
1014 .name = @tagName(Feature.zcz_gp),
1015 .llvm_name = "zcz-gp",
1016 .description = "Has zero-cycle zeroing instructions for generic registers",
1017 .dependencies = 0,
1018 };
1019 break :blk result;
1020};
1021
1022pub const cpu = struct {
1023 pub const apple_latest = Cpu{
1024 .name = "apple_latest",
1025 .llvm_name = "apple-latest",
1026 .features = featureSet(&[_]Feature{
1027 .arith_cbz_fusion,
1028 .zcz_fp_workaround,
1029 .alternate_sextload_cvt_f32_pattern,
1030 .fuse_crypto_eor,
1031 .zcm,
1032 .zcz_gp,
1033 .perfmon,
1034 .disable_latency_sched_heuristic,
1035 .fp_armv8,
1036 .zcz_fp,
1037 .arith_bcc_fusion,
1038 .fuse_aes,
1039 }),
1040 };
1041
1042 pub const cortex_a35 = Cpu{
1043 .name = "cortex_a35",
1044 .llvm_name = "cortex-a35",
1045 .features = featureSet(&[_]Feature{
1046 .perfmon,
1047 .fp_armv8,
1048 .crc,
1049 }),
1050 };
1051
1052 pub const cortex_a53 = Cpu{
1053 .name = "cortex_a53",
1054 .llvm_name = "cortex-a53",
1055 .features = featureSet(&[_]Feature{
1056 .custom_cheap_as_move,
1057 .crc,
1058 .perfmon,
1059 .use_aa,
1060 .fp_armv8,
1061 .fuse_aes,
1062 .balance_fp_ops,
1063 .use_postra_scheduler,
1064 }),
1065 };
1066
1067 pub const cortex_a55 = Cpu{
1068 .name = "cortex_a55",
1069 .llvm_name = "cortex-a55",
1070 .features = featureSet(&[_]Feature{
1071 .ccpp,
1072 .rcpc,
1073 .uaops,
1074 .rdm,
1075 .ras,
1076 .lse,
1077 .crc,
1078 .perfmon,
1079 .fp_armv8,
1080 .vh,
1081 .fuse_aes,
1082 .lor,
1083 .dotprod,
1084 .pan,
1085 }),
1086 };
1087
1088 pub const cortex_a57 = Cpu{
1089 .name = "cortex_a57",
1090 .llvm_name = "cortex-a57",
1091 .features = featureSet(&[_]Feature{
1092 .fuse_literals,
1093 .predictable_select_expensive,
1094 .custom_cheap_as_move,
1095 .crc,
1096 .perfmon,
1097 .fp_armv8,
1098 .fuse_aes,
1099 .balance_fp_ops,
1100 .use_postra_scheduler,
1101 }),
1102 };
1103
1104 pub const cortex_a72 = Cpu{
1105 .name = "cortex_a72",
1106 .llvm_name = "cortex-a72",
1107 .features = featureSet(&[_]Feature{
1108 .fuse_aes,
1109 .fp_armv8,
1110 .perfmon,
1111 .crc,
1112 }),
1113 };
1114
1115 pub const cortex_a73 = Cpu{
1116 .name = "cortex_a73",
1117 .llvm_name = "cortex-a73",
1118 .features = featureSet(&[_]Feature{
1119 .fuse_aes,
1120 .fp_armv8,
1121 .perfmon,
1122 .crc,
1123 }),
1124 };
1125
1126 pub const cortex_a75 = Cpu{
1127 .name = "cortex_a75",
1128 .llvm_name = "cortex-a75",
1129 .features = featureSet(&[_]Feature{
1130 .ccpp,
1131 .rcpc,
1132 .uaops,
1133 .rdm,
1134 .ras,
1135 .lse,
1136 .crc,
1137 .perfmon,
1138 .fp_armv8,
1139 .vh,
1140 .fuse_aes,
1141 .lor,
1142 .dotprod,
1143 .pan,
1144 }),
1145 };
1146
1147 pub const cortex_a76 = Cpu{
1148 .name = "cortex_a76",
1149 .llvm_name = "cortex-a76",
1150 .features = featureSet(&[_]Feature{
1151 .ccpp,
1152 .rcpc,
1153 .uaops,
1154 .rdm,
1155 .ras,
1156 .lse,
1157 .crc,
1158 .fp_armv8,
1159 .vh,
1160 .lor,
1161 .ssbs,
1162 .dotprod,
1163 .pan,
1164 }),
1165 };
1166
1167 pub const cortex_a76ae = Cpu{
1168 .name = "cortex_a76ae",
1169 .llvm_name = "cortex-a76ae",
1170 .features = featureSet(&[_]Feature{
1171 .ccpp,
1172 .rcpc,
1173 .uaops,
1174 .rdm,
1175 .ras,
1176 .lse,
1177 .crc,
1178 .fp_armv8,
1179 .vh,
1180 .lor,
1181 .ssbs,
1182 .dotprod,
1183 .pan,
1184 }),
1185 };
1186
1187 pub const cyclone = Cpu{
1188 .name = "cyclone",
1189 .llvm_name = "cyclone",
1190 .features = featureSet(&[_]Feature{
1191 .arith_cbz_fusion,
1192 .zcz_fp_workaround,
1193 .alternate_sextload_cvt_f32_pattern,
1194 .fuse_crypto_eor,
1195 .zcm,
1196 .zcz_gp,
1197 .perfmon,
1198 .disable_latency_sched_heuristic,
1199 .fp_armv8,
1200 .zcz_fp,
1201 .arith_bcc_fusion,
1202 .fuse_aes,
1203 }),
1204 };
1205
1206 pub const exynos_m1 = Cpu{
1207 .name = "exynos_m1",
1208 .llvm_name = "exynos-m1",
1209 .features = featureSet(&[_]Feature{
1210 .custom_cheap_as_move,
1211 .crc,
1212 .force_32bit_jump_tables,
1213 .perfmon,
1214 .slow_misaligned_128store,
1215 .use_reciprocal_square_root,
1216 .fp_armv8,
1217 .zcz_fp,
1218 .fuse_aes,
1219 .slow_paired_128,
1220 .use_postra_scheduler,
1221 }),
1222 };
1223
1224 pub const exynos_m2 = Cpu{
1225 .name = "exynos_m2",
1226 .llvm_name = "exynos-m2",
1227 .features = featureSet(&[_]Feature{
1228 .custom_cheap_as_move,
1229 .crc,
1230 .force_32bit_jump_tables,
1231 .perfmon,
1232 .slow_misaligned_128store,
1233 .fp_armv8,
1234 .zcz_fp,
1235 .fuse_aes,
1236 .slow_paired_128,
1237 .use_postra_scheduler,
1238 }),
1239 };
1240
1241 pub const exynos_m3 = Cpu{
1242 .name = "exynos_m3",
1243 .llvm_name = "exynos-m3",
1244 .features = featureSet(&[_]Feature{
1245 .fuse_literals,
1246 .predictable_select_expensive,
1247 .custom_cheap_as_move,
1248 .crc,
1249 .force_32bit_jump_tables,
1250 .fuse_address,
1251 .fuse_csel,
1252 .perfmon,
1253 .fp_armv8,
1254 .zcz_fp,
1255 .fuse_aes,
1256 .lsl_fast,
1257 .use_postra_scheduler,
1258 }),
1259 };
1260
1261 pub const exynos_m4 = Cpu{
1262 .name = "exynos_m4",
1263 .llvm_name = "exynos-m4",
1264 .features = featureSet(&[_]Feature{
1265 .arith_cbz_fusion,
1266 .custom_cheap_as_move,
1267 .lse,
1268 .zcz_fp,
1269 .lsl_fast,
1270 .lor,
1271 .fuse_literals,
1272 .ccpp,
1273 .ras,
1274 .fp_armv8,
1275 .fuse_aes,
1276 .pan,
1277 .fuse_arith_logic,
1278 .crc,
1279 .force_32bit_jump_tables,
1280 .fuse_address,
1281 .fuse_csel,
1282 .arith_bcc_fusion,
1283 .uaops,
1284 .rdm,
1285 .zcz_gp,
1286 .perfmon,
1287 .vh,
1288 .use_postra_scheduler,
1289 .dotprod,
1290 }),
1291 };
1292
1293 pub const exynos_m5 = Cpu{
1294 .name = "exynos_m5",
1295 .llvm_name = "exynos-m5",
1296 .features = featureSet(&[_]Feature{
1297 .arith_cbz_fusion,
1298 .custom_cheap_as_move,
1299 .lse,
1300 .zcz_fp,
1301 .lsl_fast,
1302 .lor,
1303 .fuse_literals,
1304 .ccpp,
1305 .ras,
1306 .fp_armv8,
1307 .fuse_aes,
1308 .pan,
1309 .fuse_arith_logic,
1310 .crc,
1311 .force_32bit_jump_tables,
1312 .fuse_address,
1313 .fuse_csel,
1314 .arith_bcc_fusion,
1315 .uaops,
1316 .rdm,
1317 .zcz_gp,
1318 .perfmon,
1319 .vh,
1320 .use_postra_scheduler,
1321 .dotprod,
1322 }),
1323 };
1324
1325 pub const falkor = Cpu{
1326 .name = "falkor",
1327 .llvm_name = "falkor",
1328 .features = featureSet(&[_]Feature{
1329 .predictable_select_expensive,
1330 .custom_cheap_as_move,
1331 .rdm,
1332 .slow_strqro_store,
1333 .zcz_gp,
1334 .crc,
1335 .perfmon,
1336 .fp_armv8,
1337 .zcz_fp,
1338 .lsl_fast,
1339 .use_postra_scheduler,
1340 }),
1341 };
1342
1343 pub const generic = Cpu{
1344 .name = "generic",
1345 .llvm_name = "generic",
1346 .features = featureSet(&[_]Feature{
1347 .fp_armv8,
1348 .fuse_aes,
1349 .neon,
1350 .perfmon,
1351 .use_postra_scheduler,
1352 }),
1353 };
1354
1355 pub const kryo = Cpu{
1356 .name = "kryo",
1357 .llvm_name = "kryo",
1358 .features = featureSet(&[_]Feature{
1359 .predictable_select_expensive,
1360 .custom_cheap_as_move,
1361 .zcz_gp,
1362 .crc,
1363 .perfmon,
1364 .fp_armv8,
1365 .zcz_fp,
1366 .lsl_fast,
1367 .use_postra_scheduler,
1368 }),
1369 };
1370
1371 pub const saphira = Cpu{
1372 .name = "saphira",
1373 .llvm_name = "saphira",
1374 .features = featureSet(&[_]Feature{
1375 .predictable_select_expensive,
1376 .custom_cheap_as_move,
1377 .fmi,
1378 .lse,
1379 .zcz_fp,
1380 .lsl_fast,
1381 .lor,
1382 .dit,
1383 .pa,
1384 .ccpp,
1385 .sel2,
1386 .ras,
1387 .fp_armv8,
1388 .ccidx,
1389 .pan,
1390 .rcpc,
1391 .crc,
1392 .tracev84,
1393 .mpam,
1394 .am,
1395 .nv,
1396 .tlb_rmi,
1397 .uaops,
1398 .rdm,
1399 .zcz_gp,
1400 .perfmon,
1401 .vh,
1402 .use_postra_scheduler,
1403 .dotprod,
1404 .spe,
1405 }),
1406 };
1407
1408 pub const thunderx = Cpu{
1409 .name = "thunderx",
1410 .llvm_name = "thunderx",
1411 .features = featureSet(&[_]Feature{
1412 .predictable_select_expensive,
1413 .crc,
1414 .perfmon,
1415 .fp_armv8,
1416 .use_postra_scheduler,
1417 }),
1418 };
1419
1420 pub const thunderx2t99 = Cpu{
1421 .name = "thunderx2t99",
1422 .llvm_name = "thunderx2t99",
1423 .features = featureSet(&[_]Feature{
1424 .predictable_select_expensive,
1425 .aggressive_fma,
1426 .rdm,
1427 .lse,
1428 .crc,
1429 .fp_armv8,
1430 .vh,
1431 .arith_bcc_fusion,
1432 .lor,
1433 .use_postra_scheduler,
1434 .pan,
1435 }),
1436 };
1437
1438 pub const thunderxt81 = Cpu{
1439 .name = "thunderxt81",
1440 .llvm_name = "thunderxt81",
1441 .features = featureSet(&[_]Feature{
1442 .predictable_select_expensive,
1443 .crc,
1444 .perfmon,
1445 .fp_armv8,
1446 .use_postra_scheduler,
1447 }),
1448 };
1449
1450 pub const thunderxt83 = Cpu{
1451 .name = "thunderxt83",
1452 .llvm_name = "thunderxt83",
1453 .features = featureSet(&[_]Feature{
1454 .predictable_select_expensive,
1455 .crc,
1456 .perfmon,
1457 .fp_armv8,
1458 .use_postra_scheduler,
1459 }),
1460 };
1461
1462 pub const thunderxt88 = Cpu{
1463 .name = "thunderxt88",
1464 .llvm_name = "thunderxt88",
1465 .features = featureSet(&[_]Feature{
1466 .predictable_select_expensive,
1467 .crc,
1468 .perfmon,
1469 .fp_armv8,
1470 .use_postra_scheduler,
1471 }),
1472 };
1473
1474 pub const tsv110 = Cpu{
1475 .name = "tsv110",
1476 .llvm_name = "tsv110",
1477 .features = featureSet(&[_]Feature{
1478 .ccpp,
1479 .custom_cheap_as_move,
1480 .uaops,
1481 .rdm,
1482 .ras,
1483 .lse,
1484 .crc,
1485 .perfmon,
1486 .fp_armv8,
1487 .vh,
1488 .fuse_aes,
1489 .lor,
1490 .use_postra_scheduler,
1491 .dotprod,
1492 .pan,
1493 .spe,
1494 }),
1495 };
1496};
1497
1498/// All aarch64 CPUs, sorted alphabetically by name.
1499/// TODO: Replace this with usage of `std.meta.declList`. It does work, but stage1
1500/// compiler has inefficient memory and CPU usage, affecting build times.
1501pub const all_cpus = &[_]*const Cpu{
1502 &cpu.apple_latest,
1503 &cpu.cortex_a35,
1504 &cpu.cortex_a53,
1505 &cpu.cortex_a55,
1506 &cpu.cortex_a57,
1507 &cpu.cortex_a72,
1508 &cpu.cortex_a73,
1509 &cpu.cortex_a75,
1510 &cpu.cortex_a76,
1511 &cpu.cortex_a76ae,
1512 &cpu.cyclone,
1513 &cpu.exynos_m1,
1514 &cpu.exynos_m2,
1515 &cpu.exynos_m3,
1516 &cpu.exynos_m4,
1517 &cpu.exynos_m5,
1518 &cpu.falkor,
1519 &cpu.generic,
1520 &cpu.kryo,
1521 &cpu.saphira,
1522 &cpu.thunderx,
1523 &cpu.thunderx2t99,
1524 &cpu.thunderxt81,
1525 &cpu.thunderxt83,
1526 &cpu.thunderxt88,
1527 &cpu.tsv110,
16031528};
src-self-hosted/stage1.zig+147-240
......@@ -81,6 +81,9 @@ const Error = extern enum {
8181 OperationAborted,
8282 BrokenPipe,
8383 NoSpaceLeft,
84 NotLazy,
85 IsAsync,
86 ImportOutsidePkgPath,
8487};
8588
8689const FILE = std.c.FILE;
......@@ -150,7 +153,7 @@ fn fmtMain(argc: c_int, argv: [*]const [*:0]const u8) !void {
150153 const argc_usize = @intCast(usize, argc);
151154 var arg_i: usize = 0;
152155 while (arg_i < argc_usize) : (arg_i += 1) {
153 try args_list.append(std.mem.toSliceConst(u8, argv[arg_i]));
156 try args_list.append(mem.toSliceConst(u8, argv[arg_i]));
154157 }
155158
156159 stdout = &std.io.getStdOut().outStream().stream;
......@@ -532,7 +535,7 @@ export fn stage2_progress_update_node(node: *std.Progress.Node, done_count: usiz
532535// ABI warning
533536export fn stage2_list_features_for_arch(arch_name_ptr: [*]const u8, arch_name_len: usize, show_dependencies: bool) void {
534537 printFeaturesForArch(arch_name_ptr[0..arch_name_len], show_dependencies) catch |err| {
535 std.debug.warn("Failed to list features: {}\n", .{ @errorName(err) });
538 std.debug.warn("Failed to list features: {}\n", .{@errorName(err)});
536539 };
537540}
538541
......@@ -540,11 +543,11 @@ fn printFeaturesForArch(arch_name: []const u8, show_dependencies: bool) !void {
540543 const stdout_stream = &std.io.getStdOut().outStream().stream;
541544
542545 const arch = Target.parseArchTag(arch_name) catch {
543 std.debug.warn("Failed to parse arch '{}'\nInvoke 'zig targets' for a list of valid architectures\n", .{ arch_name });
546 std.debug.warn("Failed to parse arch '{}'\nInvoke 'zig targets' for a list of valid architectures\n", .{arch_name});
544547 return;
545548 };
546549
547 try stdout_stream.print("Available features for {}:\n", .{ @tagName(arch) });
550 try stdout_stream.print("Available features for {}:\n", .{@tagName(arch)});
548551
549552 const features = std.target.getFeaturesForArch(arch);
550553
......@@ -556,18 +559,18 @@ fn printFeaturesForArch(arch_name: []const u8, show_dependencies: bool) !void {
556559 }
557560
558561 for (features) |feature| {
559 try stdout_stream.print(" {}", .{ feature.name });
560
562 try stdout_stream.print(" {}", .{feature.name});
563
561564 var i: usize = 0;
562565 while (i < longest_len - feature.name.len) : (i += 1) {
563 try stdout_stream.write(" ");
566 try stdout_stream.write(" ");
564567 }
565568
566 try stdout_stream.print(" - {}\n", .{ feature.description });
569 try stdout_stream.print(" - {}\n", .{feature.description});
567570
568571 if (show_dependencies and feature.dependencies.len > 0) {
569572 for (feature.dependencies) |dependency| {
570 try stdout_stream.print(" {}\n", .{ dependency.name });
573 try stdout_stream.print(" {}\n", .{dependency.name});
571574 }
572575 }
573576 }
......@@ -576,7 +579,7 @@ fn printFeaturesForArch(arch_name: []const u8, show_dependencies: bool) !void {
576579// ABI warning
577580export fn stage2_list_cpus_for_arch(arch_name_ptr: [*]const u8, arch_name_len: usize, show_dependencies: bool) void {
578581 printCpusForArch(arch_name_ptr[0..arch_name_len], show_dependencies) catch |err| {
579 std.debug.warn("Failed to list features: {}\n", .{ @errorName(err) });
582 std.debug.warn("Failed to list features: {}\n", .{@errorName(err)});
580583 };
581584}
582585
......@@ -584,13 +587,13 @@ fn printCpusForArch(arch_name: []const u8, show_dependencies: bool) !void {
584587 const stdout_stream = &std.io.getStdOut().outStream().stream;
585588
586589 const arch = Target.parseArchTag(arch_name) catch {
587 std.debug.warn("Failed to parse arch '{}'\nInvoke 'zig targets' for a list of valid architectures\n", .{ arch_name });
590 std.debug.warn("Failed to parse arch '{}'\nInvoke 'zig targets' for a list of valid architectures\n", .{arch_name});
588591 return;
589592 };
590593
591594 const cpus = std.target.getCpusForArch(arch);
592595
593 try stdout_stream.print("Available cpus for {}:\n", .{ @tagName(arch) });
596 try stdout_stream.print("Available cpus for {}:\n", .{@tagName(arch)});
594597
595598 var longest_len: usize = 0;
596599 for (cpus) |cpu| {
......@@ -600,78 +603,97 @@ fn printCpusForArch(arch_name: []const u8, show_dependencies: bool) !void {
600603 }
601604
602605 for (cpus) |cpu| {
603 try stdout_stream.print(" {}", .{ cpu.name });
604
606 try stdout_stream.print(" {}", .{cpu.name});
607
605608 var i: usize = 0;
606609 while (i < longest_len - cpu.name.len) : (i += 1) {
607 try stdout_stream.write(" ");
610 try stdout_stream.write(" ");
608611 }
609612
610613 try stdout_stream.write("\n");
611614
612615 if (show_dependencies and cpu.dependencies.len > 0) {
613616 for (cpu.dependencies) |dependency| {
614 try stdout_stream.print(" {}\n", .{ dependency.name });
617 try stdout_stream.print(" {}\n", .{dependency.name});
615618 }
616619 }
617620 }
618621}
619622
620const null_terminated_empty_string = (&[_]u8 { 0 })[0..0 :0];
621
622fn toNullTerminatedStringAlloc(allocator: *std.mem.Allocator, str: []const u8) ![:0]const u8 {
623 var buffer = try std.Buffer.init(allocator, str);
624
625 const len = buffer.len();
626
627 // Don't deinit since we steal all the buffer's memory here.
628 return buffer.list.toOwnedSlice()[0..len :0];
629}
623const Stage2CpuFeatures = struct {
624 allocator: *mem.Allocator,
625 cpu_features: Target.CpuFeatures,
630626
631const Stage2TargetDetails = struct {
632 allocator: *std.mem.Allocator,
633 target_details: std.target.TargetDetails,
634
635 llvm_cpu_str: [:0]const u8,
636 llvm_features_str: [:0]const u8,
627 llvm_cpu_name: ?[:0]const u8,
628 llvm_features_str: ?[:0]const u8,
637629
638630 builtin_str: [:0]const u8,
631 cache_hash: [:0]const u8,
639632
640633 const Self = @This();
641634
642 fn initCpu(allocator: *std.mem.Allocator, arch: @TagType(std.Target.Arch), cpu: *const std.target.Cpu) !Self {
643 var builtin_str_buffer = try std.Buffer.init(
644 allocator,
645 "@import(\"std\").target.TargetDetails{.cpu=&@import(\"std\").target.");
635 fn initBaseline(allocator: *mem.Allocator) !Self {
636 const builtin_str = try std.fmt.allocPrint0(allocator, "CpuFeatures.baseline;\n");
637 errdefer allocator.free(builtin_str);
638
639 const cache_hash = try std.fmt.allocPrint0(allocator, "\n\n");
640 errdefer allocator.free(cache_hash);
641
642 return Self{
643 .allocator = allocator,
644 .cpu_features = .{ .cpu = cpu },
645 .llvm_cpu_name = null,
646 .llvm_features_str = null,
647 .builtin_str = builtin_str,
648 .cache_hash = cache_hash,
649 };
650 }
646651
647 try builtin_str_buffer.append(@tagName(arch));
648 try builtin_str_buffer.append(".cpu_");
649 try builtin_str_buffer.append(cpu.name);
650 try builtin_str_buffer.append("};");
652 fn initCpu(allocator: *mem.Allocator, arch: Target.Arch, cpu: *const Target.Cpu) !Self {
653 const builtin_str = try std.fmt.allocPrint0(
654 allocator,
655 "CpuFeatures{{ .cpu = &Arch.{}.cpu.{} }};\n",
656 arch.genericName(),
657 cpu.name,
658 );
659 errdefer allocator.free(builtin_str);
651660
652 const cpu_string = cpu.llvm_name orelse "";
661 const cache_hash = try std.fmt.allocPrint0(allocator, "{}\n{x}", cpu.name, cpu.features);
662 errdefer allocator.free(cache_hash);
653663
654664 return Self{
655665 .allocator = allocator,
656 .target_details = .{
657 .cpu = cpu,
658 },
659 .llvm_cpu_str = try toNullTerminatedStringAlloc(allocator, cpu_string),
660 .llvm_features_str = null_terminated_empty_string,
661 .builtin_str = builtin_str_buffer.toSliceConst(),
666 .cpu_features = .{ .cpu = cpu },
667 .llvm_cpu_name = cpu.llvm_name,
668 .llvm_features_str = null,
669 .builtin_str = builtin_str,
670 .cache_hash = cache_hash,
662671 };
663672 }
664673
665 fn initFeatures(allocator: *std.mem.Allocator, arch: @TagType(std.Target.Arch), features: []*const std.target.Feature) !Self {
666 var builtin_str_buffer = try std.Buffer.init(
667 allocator,
668 "@import(\"std\").target.TargetDetails{.features=&[_]*const @import(\"std\").target.Feature{\n");
674 fn initFeatures(
675 allocator: *mem.Allocator,
676 arch: Target.Arch,
677 features: Target.Cpu.Feature.Set,
678 ) !Self {
679 const cache_hash = try std.fmt.allocPrint0(allocator, "\n{x}", features);
680 errdefer allocator.free(cache_hash);
681
682 const generic_arch_name = arch.genericName();
683 var builtin_str_buffer = try std.Buffer.allocPrint(
684 allocator,
685 "CpuFeatures{{ .features = Arch.{}.featureSet(&[_]Arch.{}.Feature{{\n",
686 generic_arch_name,
687 generic_arch_name,
688 );
689 defer builtin_str_buffer.deinit();
669690
670691 var llvm_features_buffer = try std.Buffer.initSize(allocator, 0);
692 defer llvm_features_buffer.deinit();
671693
672694 // First, disable all features.
673695 // This way, we only get the ones the user requests.
674 for (std.target.getFeaturesForArch(arch)) |feature| {
696 for (arch.allFeatures()) |feature| {
675697 if (feature.llvm_name) |llvm_name| {
676698 try llvm_features_buffer.append("-");
677699 try llvm_features_buffer.append(llvm_name);
......@@ -684,232 +706,117 @@ const Stage2TargetDetails = struct {
684706 try llvm_features_buffer.append("+");
685707 try llvm_features_buffer.append(llvm_name);
686708 try llvm_features_buffer.append(",");
687
688 try builtin_str_buffer.append("&@import(\"std\").target.");
689 try builtin_str_buffer.append(@tagName(arch));
690 try builtin_str_buffer.append(".feature_");
691 try builtin_str_buffer.append(feature.name);
692 try builtin_str_buffer.append(",");
693709 }
710
711 try builtin_str_buffer.append(" .");
712 try builtin_str_buffer.append(feature.name);
713 try builtin_str_buffer.append(",\n");
694714 }
695715
696 try builtin_str_buffer.append("}};");
716 if (mem.endsWith(u8, llvm_features_buffer.toSliceConst(), ",")) {
717 llvm_features_buffer.shrink(llvm_features_buffer.len() - 1);
718 }
719
720 try builtin_str_buffer.append("})};\n");
697721
698722 return Self{
699723 .allocator = allocator,
700 .target_details = std.target.TargetDetails{
701 .features = features,
702 },
703 .llvm_cpu_str = null_terminated_empty_string,
704 .llvm_features_str = llvm_features_buffer.toSliceConst(),
705 .builtin_str = builtin_str_buffer.toSliceConst(),
724 .cpu_features = .{ .features = features },
725 .llvm_cpu_name = null,
726 .llvm_features_str = llvm_features_buffer.toOwnedSlice(),
727 .builtin_str = builtin_str_buffer.toOwnedSlice(),
728 .cache_hash = cache_hash,
706729 };
707730 }
708};
709731
710// ABI warning
711export fn stage2_target_details_parse_cpu(arch_str: ?[*:0]const u8, cpu_str: ?[*:0]const u8) ?*Stage2TargetDetails {
712 if (cpu_str == null) return null;
713 if (arch_str == null) return null;
714
715 const arch = Target.parseArchTag(std.mem.toSliceConst(u8, arch_str.?)) catch {
716 return null;
717 };
718 return parseCpu(arch, std.mem.toSliceConst(u8, cpu_str.?)) catch |err| {
719 switch (err) {
720 error.OutOfMemory => @panic("out of memory"),
721 else => return null,
722 }
723 };
724}
732 fn deinit(self: *Self) void {
733 self.allocator.free(self.cache_hash);
734 self.allocator.free(self.builtin_str);
735 if (self.llvm_features_str) |llvm_features_str| self.allocator.free(llvm_features_str);
736 self.* = undefined;
737 }
738};
725739
726740// ABI warning
727export fn stage2_target_details_parse_features(arch_str: ?[*:0]const u8, features_str: ?[*:0]const u8) ?*Stage2TargetDetails {
728 if (features_str == null) return null;
729 if (arch_str == null) return null;
730
731 const arch = Target.parseArchTag(std.mem.toSliceConst(u8, arch_str.?)) catch return null;
732 return parseFeatures(arch, std.mem.toSliceConst(u8, features_str.?)) catch |err| {
733 switch (err) {
734 error.OutOfMemory => @panic("out of memory"),
735 else => return null,
736 }
741export fn stage2_cpu_features_parse_cpu(arch_name: [*:0]const u8, cpu_name: [*:0]const u8) *Stage2CpuFeatures {
742 return parseCpu(arch_name, cpu_name) catch |err| switch (err) {
743 error.OutOfMemory => @panic("out of memory"),
737744 };
738745}
739746
740fn parseCpu(arch: @TagType(std.Target.Arch), str: []const u8) !*Stage2TargetDetails {
741 const allocator = std.heap.c_allocator;
747fn parseCpu(arch_name: [*:0]const u8, cpu_name: [*:0]const u8) !*Stage2CpuFeatures {
748 const arch = try Target.parseArchSub(mem.toSliceConst(u8, arch_name));
749 const cpu = try arch.parseCpu(mem.toSliceConst(u8, cpu_name));
742750
743 const cpus = std.target.getCpusForArch(arch);
744
745 for (cpus) |cpu| {
746 if (std.mem.eql(u8, str, cpu.name)) {
747 const ptr = try allocator.create(Stage2TargetDetails);
748 ptr.* = try Stage2TargetDetails.initCpu(std.heap.c_allocator, arch, cpu);
751 const ptr = try allocator.create(Stage2CpuFeatures);
752 errdefer std.heap.c_allocator.destroy(ptr);
749753
750 return ptr;
751 }
752 }
754 ptr.* = try Stage2CpuFeatures.initCpu(std.heap.c_allocator, arch, cpu);
755 errdefer ptr.deinit();
753756
754 return error.InvalidCpu;
757 return ptr;
755758}
756759
757fn parseFeatures(arch: @TagType(std.Target.Arch), str: []const u8) !*Stage2TargetDetails {
758 const allocator = std.heap.c_allocator;
759
760 const known_features = std.target.getFeaturesForArch(arch);
761
762 var features = std.ArrayList(*const std.target.Feature).init(allocator);
763 defer features.deinit();
764
765 var start: usize = 0;
766 while (start < str.len) {
767 const next_comma_pos = std.mem.indexOfScalar(u8, str[start..], ',') orelse str.len - start;
768 const feature_str = std.mem.trim(u8, str[start..start+next_comma_pos], " ");
769
770 start += next_comma_pos + 1;
771
772 if (feature_str.len == 0) continue;
773
774 var feature: ?*const std.target.Feature = null;
775 for (known_features) |known_feature| {
776 if (std.mem.eql(u8, feature_str, known_feature.name)) {
777 feature = known_feature;
778 break;
779 }
780 }
781
782 if (feature) |f| {
783 features.append(f) catch @panic("out of memory");
760// ABI warning
761export fn stage2_cpu_features_parse_features(
762 arch_name: [*:0]const u8,
763 features_text: [*:0]const u8,
764) *Stage2CpuFeatures {
765 return parseFeatures(arch_name, features_text) catch |err| switch (err) {
766 error.OutOfMemory => @panic("out of memory"),
767 };
768}
784769
785 } else {
786 return error.InvalidFeature;
787 }
788 }
770fn parseFeatures(arch_name: [*:0]const u8, features_text: [*:0]const u8) !*Stage2CpuFeatures {
771 const arch = try Target.parseArchSub(mem.toSliceConst(u8, arch_name));
772 const set = try arch.parseCpuFeatureSet(mem.toSliceConst(u8, features_text));
789773
790 const features_slice = features.toOwnedSlice();
774 const ptr = try std.heap.c_allocator.create(Stage2CpuFeatures);
775 errdefer std.heap.c_allocator.destroy(ptr);
791776
792 const ptr = try allocator.create(Stage2TargetDetails);
793 ptr.* = try Stage2TargetDetails.initFeatures(allocator, arch, features_slice);
777 ptr.* = try Stage2CpuFeatures.initFeatures(std.heap.c_allocator, arch, set);
778 errdefer ptr.deinit();
794779
795780 return ptr;
796781}
797782
798783// ABI warning
799export fn stage2_target_details_get_cache_str(target_details: ?*const Stage2TargetDetails) [*:0]const u8 {
800 if (target_details) |td| {
801 return @as([*:0]const u8, switch (td.target_details) {
802 .cpu => td.llvm_cpu_str,
803 .features => td.llvm_features_str,
804 });
805 }
806
807 return @as([*:0]const u8, null_terminated_empty_string);
808}
784export fn stage2_cpu_features_baseline() *Stage2CpuFeatures {
785 const ptr = try std.heap.c_allocator.create(Stage2CpuFeatures);
786 errdefer std.heap.c_allocator.destroy(ptr);
809787
810// ABI warning
811export fn stage2_target_details_get_llvm_cpu(target_details: ?*const Stage2TargetDetails) [*:0]const u8 {
812 if (target_details) |td| {
813 return @as([*:0]const u8, td.llvm_cpu_str);
814 }
788 ptr.* = try Stage2CpuFeatures.initBaseline(std.heap.c_allocator);
789 errdefer ptr.deinit();
815790
816 return @as([*:0]const u8, null_terminated_empty_string);
791 return ptr;
817792}
818793
819794// ABI warning
820export fn stage2_target_details_get_llvm_features(target_details: ?*const Stage2TargetDetails) [*:0]const u8 {
821 if (target_details) |td| {
822 return @as([*:0]const u8, td.llvm_features_str);
823 }
824
825 return @as([*:0]const u8, null_terminated_empty_string);
795export fn stage2_cpu_features_get_cache_hash(
796 cpu_features: *const Stage2CpuFeatures,
797 ptr: *[*:0]const u8,
798 len: *usize,
799) void {
800 ptr.* = cpu_features.cache_hash.ptr;
801 len.* = cpu_features.cache_hash.len;
826802}
827803
828804// ABI warning
829export fn stage2_target_details_get_builtin_str(target_details: ?*const Stage2TargetDetails) [*:0]const u8 {
830 if (target_details) |td| {
831 return @as([*:0]const u8, td.builtin_str);
832 }
833
834 return @as([*:0]const u8, null_terminated_empty_string);
805export fn stage2_cpu_features_get_builtin_str(
806 cpu_features: *const Stage2CpuFeatures,
807 ptr: *[*:0]const u8,
808 len: *usize,
809) void {
810 ptr.* = cpu_features.builtin_str.ptr;
811 len.* = cpu_features.builtin_str.len;
835812}
836813
837const riscv32_default_features: []*const std.target.Feature = &[_]*const std.target.Feature {
838 &std.target.riscv.feature_a,
839 &std.target.riscv.feature_c,
840 &std.target.riscv.feature_d,
841 &std.target.riscv.feature_f,
842 &std.target.riscv.feature_m,
843 &std.target.riscv.feature_relax,
844};
845
846const riscv64_default_features: []*const std.target.Feature = &[_]*const std.target.Feature {
847 &std.target.riscv.feature_bit64,
848 &std.target.riscv.feature_a,
849 &std.target.riscv.feature_c,
850 &std.target.riscv.feature_d,
851 &std.target.riscv.feature_f,
852 &std.target.riscv.feature_m,
853 &std.target.riscv.feature_relax,
854};
855
856const i386_default_features: []*const std.target.Feature = &[_]*const std.target.Feature {
857 &std.target.x86.feature_cmov,
858 &std.target.x86.feature_cx8,
859 &std.target.x86.feature_fxsr,
860 &std.target.x86.feature_mmx,
861 &std.target.x86.feature_nopl,
862 &std.target.x86.feature_sse,
863 &std.target.x86.feature_sse2,
864 &std.target.x86.feature_slowUnalignedMem16,
865 &std.target.x86.feature_x87,
866};
867
868// Same as above but without sse.
869const i386_default_features_freestanding: []*const std.target.Feature = &[_]*const std.target.Feature {
870 &std.target.x86.feature_cmov,
871 &std.target.x86.feature_cx8,
872 &std.target.x86.feature_fxsr,
873 &std.target.x86.feature_mmx,
874 &std.target.x86.feature_nopl,
875 &std.target.x86.feature_slowUnalignedMem16,
876 &std.target.x86.feature_x87,
877};
878
879814// ABI warning
880export fn stage2_target_details_get_default(arch_str: ?[*:0]const u8, os_str: ?[*:0]const u8) ?*Stage2TargetDetails {
881 if (arch_str == null) return null;
882 if (os_str == null) return null;
883
884 const arch = Target.parseArchTag(std.mem.toSliceConst(u8, arch_str.?)) catch return null;
885 const os = Target.parseOs(std.mem.toSliceConst(u8, os_str.?)) catch return null;
886
887 return createDefaultTargetDetails(arch, os) catch return null;
815export fn stage2_cpu_features_get_llvm_cpu(cpu_features: *const Stage2CpuFeatures) ?[*:0]const u8 {
816 return cpu_features.llvm_cpu_name;
888817}
889818
890fn createDefaultTargetDetails(arch: @TagType(std.Target.Arch), os: std.Target.Os) !?*Stage2TargetDetails {
891 const allocator = std.heap.c_allocator;
892
893 return switch (arch) {
894 .riscv32 => blk: {
895 const ptr = try allocator.create(Stage2TargetDetails);
896 ptr.* = try Stage2TargetDetails.initFeatures(allocator, arch, riscv32_default_features);
897 break :blk ptr;
898 },
899 .riscv64 => blk: {
900 const ptr = try allocator.create(Stage2TargetDetails);
901 ptr.* = try Stage2TargetDetails.initFeatures(allocator, arch, riscv64_default_features);
902 break :blk ptr;
903 },
904 .i386 => blk: {
905 const ptr = try allocator.create(Stage2TargetDetails);
906 const features = switch (os) {
907 .freestanding => i386_default_features_freestanding,
908 else => i386_default_features,
909 };
910 ptr.* = try Stage2TargetDetails.initFeatures(allocator, arch, features);
911 break :blk ptr;
912 },
913 else => null,
914 };
819// ABI warning
820export fn stage2_cpu_features_get_llvm_features(cpu_features: *const Stage2CpuFeatures) ?[*:0]const u8 {
821 return cpu_features.llvm_features_str;
915822}
src/all_types.hpp-2
......@@ -2215,8 +2215,6 @@ struct CodeGen {
22152215
22162216 const char **clang_argv;
22172217 size_t clang_argv_len;
2218
2219 Stage2TargetDetails *target_details;
22202218};
22212219
22222220struct ZigVar {
src/codegen.cpp+33-23
......@@ -8573,6 +8573,17 @@ Buf *codegen_generate_builtin_source(CodeGen *g) {
85738573 buf_appendf(contents, "pub const os = Os.%s;\n", cur_os);
85748574 buf_appendf(contents, "pub const arch = %s;\n", cur_arch);
85758575 buf_appendf(contents, "pub const abi = Abi.%s;\n", cur_abi);
8576 {
8577 buf_append_str(contents, "pub const cpu_features: CpuFeatures = ");
8578 if (g->zig_target->cpu_features != nullptr) {
8579 const char *ptr;
8580 size_t len;
8581 stage2_cpu_features_get_builtin_str(g->zig_target->cpu_features, &ptr, &len);
8582 buf_append_mem(contents, ptr, len);
8583 } else {
8584 buf_append_str(contents, ".baseline;\n");
8585 }
8586 }
85768587 if (g->libc_link_lib != nullptr && g->zig_target->glibc_version != nullptr) {
85778588 buf_appendf(contents,
85788589 "pub const glibc_version: ?Version = Version{.major = %d, .minor = %d, .patch = %d};\n",
......@@ -8602,14 +8613,6 @@ Buf *codegen_generate_builtin_source(CodeGen *g) {
86028613 "pub var test_functions: []TestFn = undefined; // overwritten later\n"
86038614 );
86048615 }
8605
8606 buf_appendf(contents, "pub const target_details: ?@import(\"std\").target.TargetDetails = ");
8607 if (g->target_details) {
8608 buf_appendf(contents, "%s", stage2_target_details_get_builtin_str(g->target_details));
8609 } else {
8610 buf_appendf(contents, "null;");
8611 }
8612 buf_appendf(contents, "\n");
86138616
86148617 return contents;
86158618}
......@@ -8648,6 +8651,12 @@ static Error define_builtin_compile_vars(CodeGen *g) {
86488651 cache_int(&cache_hash, g->zig_target->vendor);
86498652 cache_int(&cache_hash, g->zig_target->os);
86508653 cache_int(&cache_hash, g->zig_target->abi);
8654 if (g->zig_target->cpu_features != nullptr) {
8655 const char *ptr;
8656 size_t len;
8657 stage2_cpu_features_get_cache_hash(g->zig_target->cpu_features, &ptr, &len);
8658 cache_str(&cache_hash, ptr);
8659 }
86518660 if (g->zig_target->glibc_version != nullptr) {
86528661 cache_int(&cache_hash, g->zig_target->glibc_version->major);
86538662 cache_int(&cache_hash, g->zig_target->glibc_version->minor);
......@@ -8659,10 +8668,6 @@ static Error define_builtin_compile_vars(CodeGen *g) {
86598668 cache_bool(&cache_hash, g->link_eh_frame_hdr);
86608669 cache_int(&cache_hash, detect_subsystem(g));
86618670
8662 if (g->target_details) {
8663 cache_str(&cache_hash, stage2_target_details_get_cache_str(g->target_details));
8664 }
8665
86668671 Buf digest = BUF_INIT;
86678672 buf_resize(&digest, 0);
86688673 if ((err = cache_hit(&cache_hash, &digest))) {
......@@ -8793,9 +8798,9 @@ static void init(CodeGen *g) {
87938798 }
87948799
87958800 // Override CPU and features if defined by user.
8796 if (g->target_details) {
8797 target_specific_cpu_args = stage2_target_details_get_llvm_cpu(g->target_details);
8798 target_specific_features = stage2_target_details_get_llvm_features(g->target_details);
8801 if (g->zig_target->cpu_features != nullptr) {
8802 target_specific_cpu_args = stage2_cpu_features_get_llvm_cpu(g->zig_target->cpu_features);
8803 target_specific_features = stage2_cpu_features_get_llvm_features(g->zig_target->cpu_features);
87998804 }
88008805
88018806 g->target_machine = ZigLLVMCreateTargetMachine(target_ref, buf_ptr(&g->llvm_triple_str),
......@@ -9123,15 +9128,19 @@ void add_cc_args(CodeGen *g, ZigList<const char *> &args, const char *out_dep_pa
91239128 args.append("-target");
91249129 args.append(buf_ptr(&g->llvm_triple_str));
91259130
9126 if (g->target_details) {
9131 const char *llvm_cpu = stage2_cpu_features_get_llvm_cpu(g->zig_target->cpu_features);
9132 if (llvm_cpu != nullptr) {
91279133 args.append("-Xclang");
91289134 args.append("-target-cpu");
91299135 args.append("-Xclang");
9130 args.append(stage2_target_details_get_llvm_cpu(g->target_details));
9136 args.append(llvm_cpu);
9137 }
9138 const char *llvm_target_features = stage2_cpu_features_get_llvm_features(g->zig_target->cpu_features);
9139 if (llvm_target_features != nullptr) {
91319140 args.append("-Xclang");
91329141 args.append("-target-feature");
91339142 args.append("-Xclang");
9134 args.append(stage2_target_details_get_llvm_features(g->target_details));
9143 args.append(llvm_target_features);
91359144 }
91369145 }
91379146
......@@ -10328,6 +10337,12 @@ static Error check_cache(CodeGen *g, Buf *manifest_dir, Buf *digest) {
1032810337 cache_int(ch, g->zig_target->vendor);
1032910338 cache_int(ch, g->zig_target->os);
1033010339 cache_int(ch, g->zig_target->abi);
10340 if (g->zig_target->cpu_features != nullptr) {
10341 const char *ptr;
10342 size_t len;
10343 stage2_cpu_features_get_cache_hash(g->zig_target->cpu_features, &ptr, &len);
10344 cache_str(ch, ptr);
10345 }
1033110346 if (g->zig_target->glibc_version != nullptr) {
1033210347 cache_int(ch, g->zig_target->glibc_version->major);
1033310348 cache_int(ch, g->zig_target->glibc_version->minor);
......@@ -10375,10 +10390,6 @@ static Error check_cache(CodeGen *g, Buf *manifest_dir, Buf *digest) {
1037510390 cache_buf_opt(ch, g->dynamic_linker_path);
1037610391 cache_buf_opt(ch, g->version_script_path);
1037710392
10378 if (g->target_details) {
10379 cache_str(ch, stage2_target_details_get_cache_str(g->target_details));
10380 }
10381
1038210393 // gen_c_objects appends objects to g->link_objects which we want to include in the hash
1038310394 gen_c_objects(g);
1038410395 cache_list_of_file(ch, g->link_objects.items, g->link_objects.length);
......@@ -10661,7 +10672,6 @@ CodeGen *create_child_codegen(CodeGen *parent_gen, Buf *root_src_path, OutType o
1066110672
1066210673 CodeGen *child_gen = codegen_create(nullptr, root_src_path, parent_gen->zig_target, out_type,
1066310674 parent_gen->build_mode, parent_gen->zig_lib_dir, libc, get_global_cache_dir(), false, child_progress_node);
10664 child_gen->target_details = parent_gen->target_details;
1066510675 child_gen->root_out_name = buf_create_from_str(name);
1066610676 child_gen->disable_gen_h = true;
1066710677 child_gen->want_stack_check = WantStackCheckDisabled;
src/main.cpp+10-14
......@@ -955,9 +955,9 @@ int main(int argc, char **argv) {
955955 targets_list_features_arch = argv[i];
956956 } else if (strcmp(arg, "--list-cpus") == 0) {
957957 targets_list_cpus_arch = argv[i];
958 } else if (strcmp(arg, "--cpu") == 0) {
958 } else if (strcmp(arg, "-target-cpu") == 0) {
959959 cpu = argv[i];
960 } else if (strcmp(arg, "--features") == 0) {
960 } else if (strcmp(arg, "-target-feature") == 0) {
961961 features = argv[i];
962962 }else {
963963 fprintf(stderr, "Invalid argument: %s\n", arg);
......@@ -1074,27 +1074,26 @@ int main(int argc, char **argv) {
10741074 }
10751075 }
10761076
1077 Stage2TargetDetails *target_details = nullptr;
10781077 if (cpu && features) {
1079 fprintf(stderr, "--cpu and --features options not allowed together\n");
1078 fprintf(stderr, "-target-cpu and -target-feature options not allowed together\n");
10801079 return main_exit(root_progress_node, EXIT_FAILURE);
10811080 } else if (cpu) {
1082 target_details = stage2_target_details_parse_cpu(target_arch_name(target.arch), cpu);
1083 if (!target_details) {
1084 fprintf(stderr, "invalid --cpu value\n");
1081 target.cpu_features = stage2_cpu_features_parse_cpu(target_arch_name(target.arch), cpu);
1082 if (!target.cpu_features) {
1083 fprintf(stderr, "invalid -target-cpu value\n");
10851084 return main_exit(root_progress_node, EXIT_FAILURE);
10861085 }
10871086 } else if (features) {
1088 target_details = stage2_target_details_parse_features(target_arch_name(target.arch), features);
1089 if (!target_details) {
1090 fprintf(stderr, "invalid --features value\n");
1087 target.cpu_features = stage2_cpu_features_parse_features(target_arch_name(target.arch), features);
1088 if (!target.cpu_features) {
1089 fprintf(stderr, "invalid -target-feature value\n");
10911090 return main_exit(root_progress_node, EXIT_FAILURE);
10921091 }
10931092 } else {
10941093 // If no details are specified and we are not native, load
10951094 // cross-compilation default features.
10961095 if (!target.is_native) {
1097 target_details = stage2_target_details_get_default(target_arch_name(target.arch), target_os_name(target.os));
1096 target.cpu_features = stage2_cpu_features_baseline();
10981097 }
10991098 }
11001099
......@@ -1148,7 +1147,6 @@ int main(int argc, char **argv) {
11481147 g->want_stack_check = want_stack_check;
11491148 g->want_sanitize_c = want_sanitize_c;
11501149 g->want_single_threaded = want_single_threaded;
1151 g->target_details = target_details;
11521150 Buf *builtin_source = codegen_generate_builtin_source(g);
11531151 if (fwrite(buf_ptr(builtin_source), 1, buf_len(builtin_source), stdout) != buf_len(builtin_source)) {
11541152 fprintf(stderr, "unable to write to stdout: %s\n", strerror(ferror(stdout)));
......@@ -1303,8 +1301,6 @@ int main(int argc, char **argv) {
13031301 codegen_add_rpath(g, rpath_list.at(i));
13041302 }
13051303
1306 g->target_details = target_details;
1307
13081304 codegen_set_rdynamic(g, rdynamic);
13091305 if (mmacosx_version_min && mios_version_min) {
13101306 fprintf(stderr, "-mmacosx-version-min and -mios-version-min options not allowed together\n");
src/target.hpp+1
......@@ -91,6 +91,7 @@ struct ZigTarget {
9191 Os os;
9292 ZigLLVM_EnvironmentType abi;
9393 ZigGLibCVersion *glibc_version; // null means default
94 Stage2CpuFeatures *cpu_features;
9495 bool is_native;
9596};
9697
src/userland.cpp+34-16
......@@ -89,26 +89,44 @@ void stage2_progress_complete_one(Stage2ProgressNode *node) {}
8989void stage2_progress_disable_tty(Stage2Progress *progress) {}
9090void stage2_progress_update_node(Stage2ProgressNode *node, size_t completed_count, size_t estimated_total_items){}
9191
92void stage2_list_features_for_arch(const char *arch_name_ptr, size_t arch_name_len, bool show_subfeatures) {}
93void stage2_list_cpus_for_arch(const char *arch_name_ptr, size_t arch_name_len, bool show_subfeatures) {}
94Stage2TargetDetails *stage2_target_details_parse_cpu(const char *arch, const char *str) {
95 return nullptr;
92void stage2_list_features_for_arch(const char *arch_name_ptr, size_t arch_name_len, bool show_subfeatures) {
93 const char *msg = "stage0 called stage2_list_features_for_arch";
94 stage2_panic(msg, strlen(msg));
9695}
97Stage2TargetDetails *stage2_target_details_parse_features(const char *arch, const char *str) {
98 return nullptr;
96
97void stage2_list_cpus_for_arch(const char *arch_name_ptr, size_t arch_name_len, bool show_subfeatures) {
98 const char *msg = "stage0 called stage2_list_cpus_for_arch";
99 stage2_panic(msg, strlen(msg));
99100}
100const char *stage2_target_details_get_cache_str(const Stage2TargetDetails *target_details) {
101 return "";
101Stage2CpuFeatures *stage2_cpu_features_parse_cpu(const char *arch, const char *str) {
102 const char *msg = "stage0 called stage2_cpu_features_parse_cpu";
103 stage2_panic(msg, strlen(msg));
102104}
103const char *stage2_target_details_get_llvm_cpu(const Stage2TargetDetails *target_details) {
104 return "";
105Stage2CpuFeatures *stage2_cpu_features_parse_features(const char *arch, const char *str) {
106 const char *msg = "stage0 called stage2_cpu_features_parse_features";
107 stage2_panic(msg, strlen(msg));
105108}
106const char *stage2_target_details_get_llvm_features(const Stage2TargetDetails *target_details) {
107 return "";
109Stage2CpuFeatures *stage2_cpu_features_baseline(void) {
110 const char *msg = "stage0 called stage2_cpu_features_baseline";
111 stage2_panic(msg, strlen(msg));
108112}
109const char *stage2_target_details_get_builtin_str(const Stage2TargetDetails *target_details) {
110 return "";
113void stage2_cpu_features_get_cache_hash(const Stage2CpuFeatures *cpu_features,
114 const char **ptr, size_t *len)
115{
116 const char *msg = "stage0 called stage2_cpu_features_get_cache_hash";
117 stage2_panic(msg, strlen(msg));
111118}
112Stage2TargetDetails *stage2_target_details_get_default(const char *arch, const char *os) {
113 return nullptr;
119const char *stage2_cpu_features_get_llvm_cpu(const Stage2CpuFeatures *cpu_features) {
120 const char *msg = "stage0 called stage2_cpu_features_get_llvm_cpu";
121 stage2_panic(msg, strlen(msg));
122}
123const char *stage2_cpu_features_get_llvm_features(const Stage2CpuFeatures *cpu_features) {
124 const char *msg = "stage0 called stage2_cpu_features_get_llvm_features";
125 stage2_panic(msg, strlen(msg));
126}
127void stage2_cpu_features_get_builtin_str(const Stage2CpuFeatures *cpu_features,
128 const char **ptr, size_t *len)
129{
130 const char *msg = "stage0 called stage2_cpu_features_get_builtin_str";
131 stage2_panic(msg, strlen(msg));
114132}
src/userland.h+10-8
......@@ -181,27 +181,29 @@ ZIG_EXTERN_C void stage2_list_features_for_arch(const char *arch_name_ptr, size_
181181ZIG_EXTERN_C void stage2_list_cpus_for_arch(const char *arch_name_ptr, size_t arch_name_len, bool show_subfeatures);
182182
183183// ABI warning
184struct Stage2TargetDetails;
184struct Stage2CpuFeatures;
185185
186186// ABI warning
187ZIG_EXTERN_C Stage2TargetDetails *stage2_target_details_parse_cpu(const char *arch, const char *str);
187ZIG_EXTERN_C Stage2CpuFeatures *stage2_cpu_features_parse_cpu(const char *arch, const char *cpu_name);
188188
189189// ABI warning
190ZIG_EXTERN_C Stage2TargetDetails *stage2_target_details_parse_features(const char *arch, const char *str);
190ZIG_EXTERN_C Stage2CpuFeatures *stage2_cpu_features_parse_features(const char *arch, const char *features);
191191
192192// ABI warning
193ZIG_EXTERN_C const char *stage2_target_details_get_cache_str(const Stage2TargetDetails *target_details);
193ZIG_EXTERN_C Stage2CpuFeatures *stage2_cpu_features_baseline(void);
194194
195195// ABI warning
196ZIG_EXTERN_C const char *stage2_target_details_get_llvm_cpu(const Stage2TargetDetails *target_details);
196ZIG_EXTERN_C const char *stage2_cpu_features_get_llvm_cpu(const Stage2CpuFeatures *cpu_features);
197197
198198// ABI warning
199ZIG_EXTERN_C const char *stage2_target_details_get_llvm_features(const Stage2TargetDetails *target_details);
199ZIG_EXTERN_C const char *stage2_cpu_features_get_llvm_features(const Stage2CpuFeatures *cpu_features);
200200
201201// ABI warning
202ZIG_EXTERN_C const char *stage2_target_details_get_builtin_str(const Stage2TargetDetails *target_details);
202ZIG_EXTERN_C void stage2_cpu_features_get_builtin_str(const Stage2CpuFeatures *cpu_features,
203 const char **ptr, size_t *len);
203204
204205// ABI warning
205ZIG_EXTERN_C Stage2TargetDetails *stage2_target_details_get_default(const char *arch, const char *os);
206ZIG_EXTERN_C void stage2_cpu_features_get_cache_hash(const Stage2CpuFeatures *cpu_features,
207 const char **ptr, size_t *len);
206208
207209#endif