| ... | ... | @@ -2679,25 +2679,29 @@ pub fn addCCArgs( |
| 2679 | 2679 | try argv.append("-fPIC"); |
| 2680 | 2680 | } |
| 2681 | 2681 | }, |
| 2682 | | .shared_library, .assembly, .ll, .bc, .unknown, .static_library, .object, .zig => {}, |
| 2682 | .shared_library, .ll, .bc, .unknown, .static_library, .object, .zig => {}, |
| 2683 | .assembly => { |
| 2684 | // Argh, why doesn't the assembler accept the list of CPU features?! |
| 2685 | // I don't see a way to do this other than hard coding everything. |
| 2686 | switch (target.cpu.arch) { |
| 2687 | .riscv32, .riscv64 => { |
| 2688 | if (std.Target.riscv.featureSetHas(target.cpu.features, .relax)) { |
| 2689 | try argv.append("-mrelax"); |
| 2690 | } else { |
| 2691 | try argv.append("-mno-relax"); |
| 2692 | } |
| 2693 | }, |
| 2694 | else => { |
| 2695 | // TODO |
| 2696 | }, |
| 2697 | } |
| 2698 | if (target.cpu.model.llvm_name) |ln| |
| 2699 | try argv.append(try std.fmt.allocPrint(arena, "-mcpu={s}", .{ln})); |
| 2700 | }, |
| 2683 | 2701 | } |
| 2684 | 2702 | if (out_dep_path) |p| { |
| 2685 | 2703 | try argv.appendSlice(&[_][]const u8{ "-MD", "-MV", "-MF", p }); |
| 2686 | 2704 | } |
| 2687 | | // Argh, why doesn't the assembler accept the list of CPU features?! |
| 2688 | | // I don't see a way to do this other than hard coding everything. |
| 2689 | | switch (target.cpu.arch) { |
| 2690 | | .riscv32, .riscv64 => { |
| 2691 | | if (std.Target.riscv.featureSetHas(target.cpu.features, .relax)) { |
| 2692 | | try argv.append("-mrelax"); |
| 2693 | | } else { |
| 2694 | | try argv.append("-mno-relax"); |
| 2695 | | } |
| 2696 | | }, |
| 2697 | | else => { |
| 2698 | | // TODO |
| 2699 | | }, |
| 2700 | | } |
| 2701 | 2705 | |
| 2702 | 2706 | if (target.os.tag == .freestanding) { |
| 2703 | 2707 | try argv.append("-ffreestanding"); |
Jacob G-W <jacoblevgw@gmail.com> 2021-04-16 18:04:46-04:00
Andrew Kelley <andrew@ziglang.org> 2021-04-17 02:00:07-04:00