From 5e08d00862fb10c72cd011bf29112e12ef38d576 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= <alex@alexrp.com>
Date: Tue, 30 Jul 2024 00:12:02 +0200
Subject: [PATCH 1/9] std.Target: Add Arch.isLoongArch() function.

---
 lib/std/Target.zig | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/lib/std/Target.zig b/lib/std/Target.zig
index 8d9f596072f245ea98e7bb0039d0c894910bebae..5c2b5268a37c9174e51934682f67039792d7175a 100644
--- a/lib/std/Target.zig
+++ b/lib/std/Target.zig
@@ -1084,6 +1084,13 @@ pub const Cpu = struct {
             };
         }
 
+        pub inline fn isLoongArch(arch: Arch) bool {
+            return switch (arch) {
+                .loongarch32, .loongarch64 => true,
+                else => false,
+            };
+        }
+
         pub inline fn isRISCV(arch: Arch) bool {
             return switch (arch) {
                 .riscv32, .riscv64 => true,
-- 
2.54.0


From e5c75479c2c166c99219083fd24b70901d776367 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= <alex@alexrp.com>
Date: Tue, 30 Jul 2024 00:59:50 +0200
Subject: [PATCH 2/9] std.Target: Rework isPPC()/isPPC64() functions.

* Rename isPPC() -> isPowerPC32().
* Rename isPPC64() -> isPowerPC64().
* Add new isPowerPC() function which covers both.

There was confusion even in the standard library about what isPPC() meant. This
change makes these functions work how I think most people actually expect them
to work, and makes them consistent with isMIPS(), isSPARC(), etc.

I chose to rename from PPC to PowerPC because 1) it's more consistent with the
other functions, and 2) it'll cause loud rather than silent breakage for anyone
who might have been depending on isPPC() while misunderstanding it.
---
 lib/compiler/aro/aro/Toolchain.zig |   2 +-
 lib/compiler/aro/aro/target.zig    |   2 +-
 lib/compiler_rt/common.zig         |   2 +-
 lib/std/Target.zig                 |   8 ++-
 lib/std/os/linux.zig               |  16 ++---
 lib/std/simd.zig                   |   2 +-
 src/codegen/llvm.zig               |   4 +-
 test/behavior/union.zig            |   2 +-
 test/c_abi/main.zig                | 108 +++++++++++------------------
 9 files changed, 62 insertions(+), 84 deletions(-)

diff --git a/lib/compiler/aro/aro/Toolchain.zig b/lib/compiler/aro/aro/Toolchain.zig
index 1313675f6c8dbabbd565193cd307497efee85bf3..fca44e07ecf5952431bae57f97dd0705fcb84fd6 100644
--- a/lib/compiler/aro/aro/Toolchain.zig
+++ b/lib/compiler/aro/aro/Toolchain.zig
@@ -89,7 +89,7 @@ pub fn discover(tc: *Toolchain) !void {
             .{ .unknown = {} } // TODO
         else if (target.cpu.arch.isMIPS())
             .{ .unknown = {} } // TODO
-        else if (target.cpu.arch.isPPC())
+        else if (target.cpu.arch.isPowerPC())
             .{ .unknown = {} } // TODO
         else if (target.cpu.arch == .ve)
             .{ .unknown = {} } // TODO
diff --git a/lib/compiler/aro/aro/target.zig b/lib/compiler/aro/aro/target.zig
index 2f46ebd605404f533ef0b6ace0652d8807dbdf89..a8767233024dd1465c3ce4ddd350ca21c6dab40b 100644
--- a/lib/compiler/aro/aro/target.zig
+++ b/lib/compiler/aro/aro/target.zig
@@ -264,7 +264,7 @@ pub fn systemCompiler(target: std.Target) LangOpts.Compiler {
 pub fn hasFloat128(target: std.Target) bool {
     if (target.cpu.arch.isWasm()) return true;
     if (target.isDarwin()) return false;
-    if (target.cpu.arch.isPPC() or target.cpu.arch.isPPC64()) return std.Target.powerpc.featureSetHas(target.cpu.features, .float128);
+    if (target.cpu.arch.isPowerPC()) return std.Target.powerpc.featureSetHas(target.cpu.features, .float128);
     return switch (target.os.tag) {
         .dragonfly,
         .haiku,
diff --git a/lib/compiler_rt/common.zig b/lib/compiler_rt/common.zig
index 5b3d0324b5534a0a2b1b17ee6209b23a10246477..552fc07efd0888e21bd4eccd5d386ab3a79df0e7 100644
--- a/lib/compiler_rt/common.zig
+++ b/lib/compiler_rt/common.zig
@@ -22,7 +22,7 @@ pub const want_aeabi = switch (builtin.abi) {
     },
     else => false,
 };
-pub const want_ppc_abi = builtin.cpu.arch.isPPC() or builtin.cpu.arch.isPPC64();
+pub const want_ppc_abi = builtin.cpu.arch.isPowerPC();
 
 pub const want_float_exceptions = !builtin.cpu.arch.isWasm();
 
diff --git a/lib/std/Target.zig b/lib/std/Target.zig
index 5c2b5268a37c9174e51934682f67039792d7175a..566dd4599627a0b5ebadf4957e02d18a22633d90 100644
--- a/lib/std/Target.zig
+++ b/lib/std/Target.zig
@@ -1105,14 +1105,18 @@ pub const Cpu = struct {
             };
         }
 
-        pub inline fn isPPC(arch: Arch) bool {
+        pub inline fn isPowerPC(arch: Arch) bool {
+            return arch.isPowerPC32() or arch.isPowerPC64();
+        }
+
+        pub inline fn isPowerPC32(arch: Arch) bool {
             return switch (arch) {
                 .powerpc, .powerpcle => true,
                 else => false,
             };
         }
 
-        pub inline fn isPPC64(arch: Arch) bool {
+        pub inline fn isPowerPC64(arch: Arch) bool {
             return switch (arch) {
                 .powerpc64, .powerpc64le => true,
                 else => false,
diff --git a/lib/std/os/linux.zig b/lib/std/os/linux.zig
index 198481c373b954cb9e1303cd386bc9c0d25c6827..0a40b3a79046e242e480eb37ff1ddfefef17b033 100644
--- a/lib/std/os/linux.zig
+++ b/lib/std/os/linux.zig
@@ -16,8 +16,7 @@ const native_arch = builtin.cpu.arch;
 const native_abi = builtin.abi;
 const native_endian = native_arch.endian();
 const is_mips = native_arch.isMIPS();
-const is_ppc = native_arch.isPPC();
-const is_ppc64 = native_arch.isPPC64();
+const is_ppc = native_arch.isPowerPC();
 const is_sparc = native_arch.isSPARC();
 const iovec = std.posix.iovec;
 const iovec_const = std.posix.iovec_const;
@@ -434,10 +433,9 @@ fn getauxvalImpl(index: usize) callconv(.C) usize {
 // Some architectures (and some syscalls) require 64bit parameters to be passed
 // in a even-aligned register pair.
 const require_aligned_register_pair =
-    builtin.cpu.arch.isPPC() or
+    builtin.cpu.arch.isPowerPC32() or
     builtin.cpu.arch.isMIPS() or
-    builtin.cpu.arch.isARM() or
-    builtin.cpu.arch.isThumb();
+    builtin.cpu.arch.isArmOrThumb();
 
 // Split a 64bit value into a {LSB,MSB} pair.
 // The LE/BE variants specify the endianness to assume.
@@ -2228,7 +2226,7 @@ pub fn process_vm_writev(pid: pid_t, local: []const iovec_const, remote: []const
 }
 
 pub fn fadvise(fd: fd_t, offset: i64, len: i64, advice: usize) usize {
-    if (comptime native_arch.isARM() or native_arch.isPPC()) {
+    if (comptime native_arch.isARM() or native_arch.isPowerPC32()) {
         // These architectures reorder the arguments so that a register is not skipped to align the
         // register number that `offset` is passed in.
 
@@ -3575,7 +3573,7 @@ pub const SO = if (is_mips) struct {
     pub const RCVTIMEO_NEW = 66;
     pub const SNDTIMEO_NEW = 67;
     pub const DETACH_REUSEPORT_BPF = 68;
-} else if (is_ppc or is_ppc64) struct {
+} else if (is_ppc) struct {
     pub const DEBUG = 1;
     pub const REUSEADDR = 2;
     pub const TYPE = 3;
@@ -4023,8 +4021,8 @@ pub const T = struct {
     pub const IOCSPGRP = if (is_mips) 0x741d else 0x5410;
     pub const IOCOUTQ = if (is_mips) 0x7472 else 0x5411;
     pub const IOCSTI = if (is_mips) 0x5472 else 0x5412;
-    pub const IOCGWINSZ = if (is_mips or is_ppc64) 0x40087468 else 0x5413;
-    pub const IOCSWINSZ = if (is_mips or is_ppc64) 0x80087467 else 0x5414;
+    pub const IOCGWINSZ = if (is_mips or is_ppc) 0x40087468 else 0x5413;
+    pub const IOCSWINSZ = if (is_mips or is_ppc) 0x80087467 else 0x5414;
     pub const IOCMGET = if (is_mips) 0x741d else 0x5415;
     pub const IOCMBIS = if (is_mips) 0x741b else 0x5416;
     pub const IOCMBIC = if (is_mips) 0x741c else 0x5417;
diff --git a/lib/std/simd.zig b/lib/std/simd.zig
index f5eef1cf9707d5ce1b62f63e33a5ac2d2315e3cf..a0f84b1a1dd00ca30cbfdce026a708e7d66dde09 100644
--- a/lib/std/simd.zig
+++ b/lib/std/simd.zig
@@ -26,7 +26,7 @@ pub fn suggestVectorLengthForCpu(comptime T: type, comptime cpu: std.Target.Cpu)
             // TODO: Check on this return when bigger values are more common
             if (std.Target.aarch64.featureSetHas(cpu.features, .sve)) break :blk 128;
             if (std.Target.aarch64.featureSetHas(cpu.features, .neon)) break :blk 128;
-        } else if (cpu.arch.isPPC() or cpu.arch.isPPC64()) {
+        } else if (cpu.arch.isPowerPC()) {
             if (std.Target.powerpc.featureSetHas(cpu.features, .altivec)) break :blk 128;
         } else if (cpu.arch.isMIPS()) {
             if (std.Target.mips.featureSetHas(cpu.features, .msa)) break :blk 128;
diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig
index 23e39caa987a7f8130700211bafa1a14f7c958c1..1ba1ed8b6fe6852be0ef44cf7b8c9bebcf6b4957 100644
--- a/src/codegen/llvm.zig
+++ b/src/codegen/llvm.zig
@@ -399,7 +399,7 @@ const DataLayoutBuilder = struct {
         else if (self.target.cpu.arch == .powerpc64 and
             self.target.os.tag != .freebsd and self.target.abi != .musl)
             try writer.writeAll("-Fi64")
-        else if (self.target.cpu.arch.isPPC() or self.target.cpu.arch.isPPC64())
+        else if (self.target.cpu.arch.isPowerPC())
             try writer.writeAll("-Fn32");
         if (self.target.cpu.arch != .hexagon) {
             if (self.target.cpu.arch == .arc or self.target.cpu.arch == .s390x)
@@ -659,7 +659,7 @@ const DataLayoutBuilder = struct {
                     128 => abi = 64,
                     else => {},
                 }
-            } else if ((self.target.cpu.arch.isPPC64() and self.target.os.tag == .linux and
+            } else if ((self.target.cpu.arch.isPowerPC64() and self.target.os.tag == .linux and
                 (size == 256 or size == 512)) or
                 (self.target.cpu.arch.isNvptx() and (size == 16 or size == 32)))
             {
diff --git a/test/behavior/union.zig b/test/behavior/union.zig
index b1c36c42cc5ea7b566283b3bcaec817c64729706..f5cd61f6f4b3294154e74429a9808b6908d1ffbd 100644
--- a/test/behavior/union.zig
+++ b/test/behavior/union.zig
@@ -1903,7 +1903,7 @@ test "reinterpret packed union" {
     try comptime S.doTheTest();
 
     if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest; // TODO
+    if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest; // TODO
     if (builtin.cpu.arch.isWasm()) return error.SkipZigTest; // TODO
     try S.doTheTest();
 }
diff --git a/test/c_abi/main.zig b/test/c_abi/main.zig
index 2bc93cc89e69f853ba075ffe6ffd3321cce121f9..86b9584a6ee780b69aa723ad378ab0bb16e51d3d 100644
--- a/test/c_abi/main.zig
+++ b/test/c_abi/main.zig
@@ -11,7 +11,7 @@ const print = std.debug.print;
 const expect = std.testing.expect;
 const expectEqual = std.testing.expectEqual;
 const have_i128 = builtin.cpu.arch != .x86 and !builtin.cpu.arch.isARM() and
-    !builtin.cpu.arch.isMIPS() and !builtin.cpu.arch.isPPC();
+    !builtin.cpu.arch.isMIPS() and !builtin.cpu.arch.isPowerPC32();
 
 const have_f128 = builtin.cpu.arch.isX86() and !builtin.os.tag.isDarwin();
 const have_f80 = builtin.cpu.arch.isX86();
@@ -123,8 +123,7 @@ test "C ABI floats" {
 }
 
 test "C ABI long double" {
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
 
     c_long_double(12.34);
 }
@@ -182,7 +181,7 @@ extern fn c_cmultf(a: ComplexFloat, b: ComplexFloat) ComplexFloat;
 extern fn c_cmultd(a: ComplexDouble, b: ComplexDouble) ComplexDouble;
 
 const complex_abi_compatible = builtin.cpu.arch != .x86 and !builtin.cpu.arch.isMIPS() and
-    !builtin.cpu.arch.isARM() and !builtin.cpu.arch.isPPC() and !builtin.cpu.arch.isRISCV();
+    !builtin.cpu.arch.isARM() and !builtin.cpu.arch.isPowerPC32() and !builtin.cpu.arch.isRISCV();
 
 test "C ABI complex float" {
     if (!complex_abi_compatible) return error.SkipZigTest;
@@ -324,7 +323,7 @@ extern fn c_struct_u64_u64_8(usize, usize, usize, usize, usize, usize, usize, us
 
 test "C ABI struct u64 u64" {
     if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;
 
     const s = c_ret_struct_u64_u64();
     try expect(s.a == 21);
@@ -361,7 +360,7 @@ extern fn c_struct_f32f32_f32(Struct_f32f32_f32) void;
 
 test "C ABI struct {f32,f32} f32" {
     if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;
 
     const s = c_ret_struct_f32f32_f32();
     try expect(s.a.b == 1.0);
@@ -391,7 +390,7 @@ extern fn c_struct_f32_f32f32(Struct_f32_f32f32) void;
 
 test "C ABI struct f32 {f32,f32}" {
     if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;
 
     const s = c_ret_struct_f32_f32f32();
     try expect(s.a == 1.0);
@@ -426,8 +425,7 @@ extern fn c_struct_u32_union_u32_u32u32(Struct_u32_Union_u32_u32u32) void;
 
 test "C ABI struct{u32,union{u32,struct{u32,u32}}}" {
     if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
 
     const s = c_ret_struct_u32_union_u32_u32u32();
     try expect(s.a == 1);
@@ -447,7 +445,7 @@ extern fn c_big_struct(BigStruct) void;
 
 test "C ABI big struct" {
     if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;
 
     const s = BigStruct{
         .a = 1,
@@ -473,7 +471,7 @@ const BigUnion = extern union {
 extern fn c_big_union(BigUnion) void;
 
 test "C ABI big union" {
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;
 
     const x = BigUnion{
         .a = BigStruct{
@@ -506,8 +504,7 @@ extern fn c_ret_med_struct_mixed() MedStructMixed;
 
 test "C ABI medium struct of ints and floats" {
     if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
 
     const s = MedStructMixed{
         .a = 1234,
@@ -539,8 +536,7 @@ extern fn c_ret_small_struct_ints() SmallStructInts;
 test "C ABI small struct of ints" {
     if (builtin.cpu.arch == .x86) return error.SkipZigTest;
     if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
 
     const s = SmallStructInts{
         .a = 1,
@@ -573,8 +569,7 @@ extern fn c_ret_med_struct_ints() MedStructInts;
 
 test "C ABI medium struct of ints" {
     if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
 
     const s = MedStructInts{
         .x = 1,
@@ -652,8 +647,7 @@ extern fn c_split_struct_ints(SplitStructInt) void;
 test "C ABI split struct of ints" {
     if (builtin.cpu.arch == .x86) return error.SkipZigTest;
     if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
 
     const s = SplitStructInt{
         .a = 1234,
@@ -680,8 +674,7 @@ extern fn c_ret_split_struct_mixed() SplitStructMixed;
 test "C ABI split struct of ints and floats" {
     if (builtin.cpu.arch == .x86) return error.SkipZigTest;
     if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
 
     const s = SplitStructMixed{
         .a = 1234,
@@ -708,7 +701,7 @@ extern fn c_multiple_struct_floats(FloatRect, FloatRect) void;
 
 test "C ABI sret and byval together" {
     if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;
 
     const s = BigStruct{
         .a = 1,
@@ -760,8 +753,7 @@ extern fn c_big_struct_floats(Vector5) void;
 
 test "C ABI structs of floats as parameter" {
     if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
 
     const v3 = Vector3{
         .x = 3.0,
@@ -800,8 +792,7 @@ export fn zig_multiple_struct_ints(x: Rect, y: Rect) void {
 }
 
 test "C ABI structs of ints as multiple parameters" {
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
 
     const r1 = Rect{
         .left = 1,
@@ -838,7 +829,7 @@ export fn zig_multiple_struct_floats(x: FloatRect, y: FloatRect) void {
 
 test "C ABI structs of floats as multiple parameters" {
     if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;
 
     const r1 = FloatRect{
         .left = 1,
@@ -951,8 +942,7 @@ extern fn c_ret_struct_with_array() StructWithArray;
 test "Struct with array as padding." {
     if (builtin.cpu.arch == .x86) return error.SkipZigTest;
     if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
 
     c_struct_with_array(.{ .a = 1, .padding = undefined, .b = 2 });
 
@@ -977,7 +967,7 @@ extern fn c_ret_float_array_struct() FloatArrayStruct;
 
 test "Float array like struct" {
     if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;
 
     c_float_array_struct(.{
         .origin = .{
@@ -1004,7 +994,7 @@ extern fn c_ret_small_vec() SmallVec;
 
 test "small simd vector" {
     if (builtin.cpu.arch == .x86) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
 
     c_small_vec(.{ 1, 2 });
 
@@ -1022,7 +1012,7 @@ test "medium simd vector" {
     if (builtin.zig_backend == .stage2_x86_64 and
         !comptime std.Target.x86.featureSetHas(builtin.cpu.features, .avx)) return error.SkipZigTest;
 
-    if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
 
     c_medium_vec(.{ 1, 2, 3, 4 });
 
@@ -1042,7 +1032,7 @@ test "big simd vector" {
     if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
 
     if (builtin.cpu.arch.isMIPS() and builtin.mode != .Debug) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC64()) return error.SkipZigTest;
     if (builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .x86_64 and builtin.os.tag == .macos and builtin.mode != .Debug) return error.SkipZigTest;
 
     c_big_vec(.{ 1, 2, 3, 4, 5, 6, 7, 8 });
@@ -5352,7 +5342,7 @@ extern fn c_ret_ptr_size_float_struct() Vector2;
 test "C ABI pointer sized float struct" {
     if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
     if (builtin.cpu.arch.isRISCV()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;
 
     c_ptr_size_float_struct(.{ .x = 1, .y = 2 });
 
@@ -5374,29 +5364,25 @@ const DC = extern struct { v1: f64, v2: u8 };
 test "DC: Zig passes to C" {
     if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
     if (builtin.cpu.arch.isRISCV()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
     try expectOk(c_assert_DC(.{ .v1 = -0.25, .v2 = 15 }));
 }
 test "DC: Zig returns to C" {
     if (builtin.cpu.arch.isMIPS() and builtin.mode != .Debug) return error.SkipZigTest;
     if (builtin.cpu.arch.isRISCV()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
     try expectOk(c_assert_ret_DC());
 }
 test "DC: C passes to Zig" {
     if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
     if (builtin.cpu.arch.isRISCV()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
     try expectOk(c_send_DC());
 }
 test "DC: C returns to Zig" {
     if (builtin.cpu.arch.isMIPS() and builtin.mode != .Debug) return error.SkipZigTest;
     if (builtin.cpu.arch.isRISCV()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
     try expectEqual(DC{ .v1 = -0.25, .v2 = 15 }, c_ret_DC());
 }
 
@@ -5421,14 +5407,12 @@ const CFF = extern struct { v1: u8, v2: f32, v3: f32 };
 test "CFF: Zig passes to C" {
     if (builtin.target.cpu.arch == .x86) return error.SkipZigTest;
     if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
     try expectOk(c_assert_CFF(.{ .v1 = 39, .v2 = 0.875, .v3 = 1.0 }));
 }
 test "CFF: Zig returns to C" {
     if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
     try expectOk(c_assert_ret_CFF());
 }
 test "CFF: C passes to Zig" {
@@ -5436,8 +5420,7 @@ test "CFF: C passes to Zig" {
     if (builtin.cpu.arch.isRISCV() and builtin.mode != .Debug) return error.SkipZigTest;
     if (builtin.cpu.arch == .aarch64 and builtin.mode != .Debug) return error.SkipZigTest;
     if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
 
     try expectOk(c_send_CFF());
 }
@@ -5445,8 +5428,7 @@ test "CFF: C returns to Zig" {
     if (builtin.cpu.arch == .aarch64 and builtin.mode != .Debug) return error.SkipZigTest;
     if (builtin.cpu.arch.isRISCV() and builtin.mode != .Debug) return error.SkipZigTest;
     if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
     try expectEqual(CFF{ .v1 = 39, .v2 = 0.875, .v3 = 1.0 }, c_ret_CFF());
 }
 pub extern fn c_assert_CFF(lv: CFF) c_int;
@@ -5470,26 +5452,22 @@ const PD = extern struct { v1: ?*anyopaque, v2: f64 };
 
 test "PD: Zig passes to C" {
     if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
     try expectOk(c_assert_PD(.{ .v1 = null, .v2 = 0.5 }));
 }
 test "PD: Zig returns to C" {
     if (builtin.cpu.arch.isMIPS() and builtin.mode != .Debug) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
     try expectOk(c_assert_ret_PD());
 }
 test "PD: C passes to Zig" {
     if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
     try expectOk(c_send_PD());
 }
 test "PD: C returns to Zig" {
     if (builtin.cpu.arch.isMIPS() and builtin.mode != .Debug) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
     try expectEqual(PD{ .v1 = null, .v2 = 0.5 }, c_ret_PD());
 }
 pub extern fn c_assert_PD(lv: PD) c_int;
@@ -5521,7 +5499,7 @@ const ByRef = extern struct {
 extern fn c_modify_by_ref_param(ByRef) ByRef;
 
 test "C function modifies by ref param" {
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;
 
     const res = c_modify_by_ref_param(.{ .val = 1, .arr = undefined });
     try expect(res.val == 42);
@@ -5543,7 +5521,7 @@ const ByVal = extern struct {
 extern fn c_func_ptr_byval(*anyopaque, *anyopaque, ByVal, c_ulong, *anyopaque, c_ulong) void;
 test "C function that takes byval struct called via function pointer" {
     if (builtin.cpu.arch.isMIPS() and builtin.mode != .Debug) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;
 
     var fn_ptr = &c_func_ptr_byval;
     _ = &fn_ptr;
@@ -5574,8 +5552,7 @@ const f16_struct = extern struct {
 extern fn c_f16_struct(f16_struct) f16_struct;
 test "f16 struct" {
     if (builtin.target.cpu.arch.isMIPS()) return error.SkipZigTest;
-    if (builtin.target.cpu.arch.isPPC()) return error.SkipZigTest;
-    if (builtin.target.cpu.arch.isPPC()) return error.SkipZigTest;
+    if (builtin.target.cpu.arch.isPowerPC32()) return error.SkipZigTest;
     if (builtin.cpu.arch.isARM() and builtin.mode != .Debug) return error.SkipZigTest;
 
     const a = c_f16_struct(.{ .a = 12 });
@@ -5690,8 +5667,7 @@ const Coord2 = extern struct {
 extern fn stdcall_coord2(Coord2, Coord2, Coord2) callconv(stdcall_callconv) Coord2;
 test "Stdcall ABI structs" {
     if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC64()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest;
 
     const res = stdcall_coord2(
         .{ .x = 0x1111, .y = 0x2222 },
@@ -5704,7 +5680,7 @@ test "Stdcall ABI structs" {
 
 extern fn stdcall_big_union(BigUnion) callconv(stdcall_callconv) void;
 test "Stdcall ABI big union" {
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;
 
     const x = BigUnion{
         .a = BigStruct{
@@ -5776,7 +5752,7 @@ const byval_tail_callsite_attr = struct {
 
 test "byval tail callsite attribute" {
     if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest;
-    if (builtin.cpu.arch.isPPC()) return error.SkipZigTest;
+    if (builtin.cpu.arch.isPowerPC32()) return error.SkipZigTest;
 
     // Originally reported at https://github.com/ziglang/zig/issues/16290
     // the bug was that the extern function had the byval attribute, but
-- 
2.54.0


From 5a97045644b91cdc5fb6e684eeabd596d5fb671e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= <alex@alexrp.com>
Date: Tue, 30 Jul 2024 01:06:05 +0200
Subject: [PATCH 3/9] std.Target: Add isMIPS32()/isMIPS64() functions.

---
 lib/std/Target.zig | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/lib/std/Target.zig b/lib/std/Target.zig
index 566dd4599627a0b5ebadf4957e02d18a22633d90..bc8f7b637c53e1534bdac5951eefcdd317999eaa 100644
--- a/lib/std/Target.zig
+++ b/lib/std/Target.zig
@@ -1099,8 +1099,19 @@ pub const Cpu = struct {
         }
 
         pub inline fn isMIPS(arch: Arch) bool {
+            return arch.isMIPS32() or arch.isMIPS64();
+        }
+
+        pub inline fn isMIPS32(arch: Arch) bool {
             return switch (arch) {
-                .mips, .mipsel, .mips64, .mips64el => true,
+                .mips, .mipsel => true,
+                else => false,
+            };
+        }
+
+        pub inline fn isMIPS64(arch: Arch) bool {
+            return switch (arch) {
+                .mips64, .mips64el => true,
                 else => false,
             };
         }
-- 
2.54.0


From a2868147b12985a660fa8f642b08385acc6d41df Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= <alex@alexrp.com>
Date: Tue, 30 Jul 2024 01:57:56 +0200
Subject: [PATCH 4/9] std.os.linux: Fix require_aligned_register_pair to check
 isMIPS32().

Only 32-bit architectures need this.
---
 lib/std/os/linux.zig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/std/os/linux.zig b/lib/std/os/linux.zig
index 0a40b3a79046e242e480eb37ff1ddfefef17b033..7d1f0439f009bd64da3cf557293d936d572103f2 100644
--- a/lib/std/os/linux.zig
+++ b/lib/std/os/linux.zig
@@ -434,7 +434,7 @@ fn getauxvalImpl(index: usize) callconv(.C) usize {
 // in a even-aligned register pair.
 const require_aligned_register_pair =
     builtin.cpu.arch.isPowerPC32() or
-    builtin.cpu.arch.isMIPS() or
+    builtin.cpu.arch.isMIPS32() or
     builtin.cpu.arch.isArmOrThumb();
 
 // Split a 64bit value into a {LSB,MSB} pair.
-- 
2.54.0


From f7d07b44d1c6eb05e9695f8ae28a0c64fbd14dd9 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= <alex@alexrp.com>
Date: Tue, 30 Jul 2024 02:00:44 +0200
Subject: [PATCH 5/9] std.os.linux: Fix arm check in fadvise() to also include
 thumb.

---
 lib/std/os/linux.zig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/std/os/linux.zig b/lib/std/os/linux.zig
index 7d1f0439f009bd64da3cf557293d936d572103f2..4e1dd8cda3b51142e2c33d7333710224069ecc8c 100644
--- a/lib/std/os/linux.zig
+++ b/lib/std/os/linux.zig
@@ -2226,7 +2226,7 @@ pub fn process_vm_writev(pid: pid_t, local: []const iovec_const, remote: []const
 }
 
 pub fn fadvise(fd: fd_t, offset: i64, len: i64, advice: usize) usize {
-    if (comptime native_arch.isARM() or native_arch.isPowerPC32()) {
+    if (comptime native_arch.isArmOrThumb() or native_arch.isPowerPC32()) {
         // These architectures reorder the arguments so that a register is not skipped to align the
         // register number that `offset` is passed in.
 
-- 
2.54.0


From 7cc257957e6229a1abe675128f1fdbb7078eb342 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= <alex@alexrp.com>
Date: Tue, 30 Jul 2024 02:38:24 +0200
Subject: [PATCH 6/9] glibc: Fix some target architecture checks to include
 thumb and powerpcle.

---
 src/glibc.zig | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/glibc.zig b/src/glibc.zig
index 85f1828ad43221cfff3a212f9cfca9c90e180608..576e7f813797d3996e4359aabf672290d9e6cbfb 100644
--- a/src/glibc.zig
+++ b/src/glibc.zig
@@ -403,9 +403,9 @@ pub fn buildCRTFile(comp: *Compilation, crt_file: CRTFile, prog_node: std.Progre
 
 fn start_asm_path(comp: *Compilation, arena: Allocator, basename: []const u8) ![]const u8 {
     const arch = comp.getTarget().cpu.arch;
-    const is_ppc = arch == .powerpc or arch == .powerpc64 or arch == .powerpc64le;
-    const is_aarch64 = arch == .aarch64 or arch == .aarch64_be;
-    const is_sparc = arch == .sparc or arch == .sparc64;
+    const is_ppc = arch.isPowerPC();
+    const is_aarch64 = arch.isAARCH64();
+    const is_sparc = arch.isSPARC();
     const is_64 = comp.getTarget().ptrBitWidth() == 64;
 
     const s = path.sep_str;
@@ -423,7 +423,7 @@ fn start_asm_path(comp: *Compilation, arena: Allocator, basename: []const u8) ![
                 try result.appendSlice("sparc" ++ s ++ "sparc32");
             }
         }
-    } else if (arch.isARM()) {
+    } else if (arch.isArmOrThumb()) {
         try result.appendSlice("arm");
     } else if (arch.isMIPS()) {
         if (!mem.eql(u8, basename, "crti.S") and !mem.eql(u8, basename, "crtn.S")) {
@@ -540,10 +540,10 @@ fn add_include_dirs_arch(
     dir: []const u8,
 ) error{OutOfMemory}!void {
     const arch = target.cpu.arch;
-    const is_x86 = arch == .x86 or arch == .x86_64;
-    const is_aarch64 = arch == .aarch64 or arch == .aarch64_be;
-    const is_ppc = arch == .powerpc or arch == .powerpc64 or arch == .powerpc64le;
-    const is_sparc = arch == .sparc or arch == .sparc64;
+    const is_x86 = arch.isX86();
+    const is_aarch64 = arch.isAARCH64();
+    const is_ppc = arch.isPowerPC();
+    const is_sparc = arch.isSPARC();
     const is_64 = target.ptrBitWidth() == 64;
 
     const s = path.sep_str;
@@ -573,7 +573,7 @@ fn add_include_dirs_arch(
             try args.append("-I");
             try args.append(try path.join(arena, &[_][]const u8{ dir, "x86" }));
         }
-    } else if (arch.isARM()) {
+    } else if (arch.isArmOrThumb()) {
         if (opt_nptl) |nptl| {
             try args.append("-I");
             try args.append(try path.join(arena, &[_][]const u8{ dir, "arm", nptl }));
-- 
2.54.0


From 5cd92a6b51f37d91a5063c5ee36167e96f030526 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= <alex@alexrp.com>
Date: Tue, 30 Jul 2024 02:57:43 +0200
Subject: [PATCH 7/9] libunwind: Fix an isARM() check to use isArmOrThumb()
 instead.

---
 src/libunwind.zig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/libunwind.zig b/src/libunwind.zig
index 77838768272b11522048773803cea87f5ff1c41f..dd2ed391300ce4e09acf10075bfa26f10d367cce 100644
--- a/src/libunwind.zig
+++ b/src/libunwind.zig
@@ -131,7 +131,7 @@ pub fn buildStaticLib(comp: *Compilation, prog_node: std.Progress.Node) BuildErr
         if (!comp.config.any_non_single_threaded) {
             try cflags.append("-D_LIBUNWIND_HAS_NO_THREADS");
         }
-        if (target.cpu.arch.isARM() and target.abi.floatAbi() == .hard) {
+        if (target.cpu.arch.isArmOrThumb() and target.abi.floatAbi() == .hard) {
             try cflags.append("-DCOMPILER_RT_ARMHF_TARGET");
         }
         try cflags.append("-Wno-bitwise-conditional-parentheses");
-- 
2.54.0


From a9c78185120fd1dd731c00f1bd961f0b2e2b2c83 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= <alex@alexrp.com>
Date: Tue, 30 Jul 2024 02:56:29 +0200
Subject: [PATCH 8/9] start: Fix an isARM() check to use isArmOrThumb()
 instead.

---
 lib/std/start.zig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/std/start.zig b/lib/std/start.zig
index fd8661660b0ccb03af87a9a833b92a2939cd5ad0..c975c888aface187a7825e75e112af7b9a8a0c17 100644
--- a/lib/std/start.zig
+++ b/lib/std/start.zig
@@ -495,7 +495,7 @@ fn posixCallMainAndExit(argc_argv_ptr: [*]usize) callconv(.C) noreturn {
             // ARMv6 targets (and earlier) have no support for TLS in hardware.
             // FIXME: Elide the check for targets >= ARMv7 when the target feature API
             // becomes less verbose (and more usable).
-            if (comptime native_arch.isARM()) {
+            if (comptime native_arch.isArmOrThumb()) {
                 if (at_hwcap & std.os.linux.HWCAP.TLS == 0) {
                     // FIXME: Make __aeabi_read_tp call the kernel helper kuser_get_tls
                     // For the time being use a simple trap instead of a @panic call to
-- 
2.54.0


From 7d88bd0b9c4ca12235769a04c45842dab3b54827 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= <alex@alexrp.com>
Date: Tue, 30 Jul 2024 02:55:49 +0200
Subject: [PATCH 9/9] std.simd: Fix an isARM() check to use isArmOrThumb()
 instead.

Thumb can have NEON instructions too.
---
 lib/std/simd.zig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/std/simd.zig b/lib/std/simd.zig
index a0f84b1a1dd00ca30cbfdce026a708e7d66dde09..236b9fbab8eff0103e4ccaedb8d0830a12aad036 100644
--- a/lib/std/simd.zig
+++ b/lib/std/simd.zig
@@ -18,7 +18,7 @@ pub fn suggestVectorLengthForCpu(comptime T: type, comptime cpu: std.Target.Cpu)
             if (std.Target.x86.featureSetHasAny(cpu.features, .{ .prefer_256_bit, .avx2 }) and !std.Target.x86.featureSetHas(cpu.features, .prefer_128_bit)) break :blk 256;
             if (std.Target.x86.featureSetHas(cpu.features, .sse)) break :blk 128;
             if (std.Target.x86.featureSetHasAny(cpu.features, .{ .mmx, .@"3dnow" })) break :blk 64;
-        } else if (cpu.arch.isARM()) {
+        } else if (cpu.arch.isArmOrThumb()) {
             if (std.Target.arm.featureSetHas(cpu.features, .neon)) break :blk 128;
         } else if (cpu.arch.isAARCH64()) {
             // SVE allows up to 2048 bits in the specification, as of 2022 the most powerful machine has implemented 512-bit
-- 
2.54.0